From: Jiaxun Yang <jiaxun.yang@flygoat.com>
To: "Philippe Mathieu-Daudé" <f4bug@amsat.org>,
"Richard Henderson" <richard.henderson@linaro.org>,
qemu-devel@nongnu.org, "Aurelien Jarno" <aurelien@aurel32.net>
Cc: Aleksandar Rikalo <aleksandar.rikalo@syrmia.com>,
kvm@vger.kernel.org, Huacai Chen <chenhuacai@kernel.org>,
Paolo Bonzini <pbonzini@redhat.com>
Subject: Re: [PATCH v2 03/24] target/mips/cpu: Introduce isa_rel6_available() helper
Date: Wed, 16 Dec 2020 10:50:05 +0800 [thread overview]
Message-ID: <af357960-40f2-b9e6-485f-d1cf36a4e95d@flygoat.com> (raw)
In-Reply-To: <40e8df0f-01ab-6693-785b-257b8d3144bf@amsat.org>
在 2020/12/16 上午7:48, Philippe Mathieu-Daudé 写道:
> On 12/16/20 12:27 AM, Richard Henderson wrote:
>> On 12/15/20 4:57 PM, Philippe Mathieu-Daudé wrote:
>>> +bool isa_rel6_available(const CPUMIPSState *env)
>>> +{
>>> + if (TARGET_LONG_BITS == 64) {
>>> + return cpu_supports_isa(env, ISA_MIPS64R6);
>>> + }
>>> + return cpu_supports_isa(env, ISA_MIPS32R6);
>>> +}
>> So... does qemu-system-mips64 support 32-bit cpus?
> Well... TBH I never tested it :S It looks the TCG code
> is compiled with 64-bit TL registers, the machine address
> space is 64-bit regardless the CPU, and I see various
> #ifdef MIPS64 code that look dubious with 32-bit CPU.
qemu-system-mips64 and qemu-system-mips64el do support 32bit
CPUs like M14Kc and P5600 :-)
Sometimes I'm just curious about the necessity of having mips/mipsel
targets
>> If so, this needs to be written
>>
>> if (TARGET_LONG_BITS == 64 && cpu_supports_isa(...)) {
>> return true;
>> }
>>
>> Otherwise, this will return false for a mips32r6 cpu.
> I see. Rel6 is new to me, so I'll have to look at the ISA
> manuals before returning to this thread with an answer.
TBH I do think it doesn't sounds like a good idea to make 32-bit
and 64-bit different. In fact ISA_MIPS32R6 is always set for targets
with ISA_MIPS64R6.
We're treating MIPS64R6 as a superset of MIPS32R6, and ISA_MIPS3
is used to tell if a CPU supports 64-bit.
FYI: https://commons.wikimedia.org/wiki/File:MIPS_instruction_set_family.svg
Thanks.
- Jiaxun
>
> Thanks for reviewing the series!
>
> Phil.
next prev parent reply other threads:[~2020-12-16 2:53 UTC|newest]
Thread overview: 48+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-12-15 22:57 [PATCH v2 00/24] target/mips: Convert MSA ASE to decodetree Philippe Mathieu-Daudé
2020-12-15 22:57 ` [PATCH v2 01/24] target/mips/translate: Extract decode_opc_legacy() from decode_opc() Philippe Mathieu-Daudé
2020-12-15 23:23 ` Richard Henderson
2020-12-15 22:57 ` [PATCH v2 02/24] target/mips/translate: Expose check_mips_64() to 32-bit mode Philippe Mathieu-Daudé
2021-01-06 18:20 ` Philippe Mathieu-Daudé
2021-01-06 18:37 ` Philippe Mathieu-Daudé
2021-01-07 3:56 ` Jiaxun Yang
2020-12-15 22:57 ` [PATCH v2 03/24] target/mips/cpu: Introduce isa_rel6_available() helper Philippe Mathieu-Daudé
2020-12-15 23:27 ` Richard Henderson
2020-12-15 23:48 ` Philippe Mathieu-Daudé
2020-12-16 2:50 ` Jiaxun Yang [this message]
2020-12-16 3:14 ` Jiaxun Yang
2020-12-16 10:50 ` Philippe Mathieu-Daudé
2020-12-16 10:59 ` Philippe Mathieu-Daudé
2020-12-16 11:30 ` Jiaxun Yang
2020-12-16 11:36 ` Jiaxun Yang
2021-01-07 9:04 ` Philippe Mathieu-Daudé
2021-01-07 13:17 ` Philippe Mathieu-Daudé
2020-12-16 10:55 ` Philippe Mathieu-Daudé
2020-12-15 22:57 ` [PATCH v2 04/24] target/mips: Introduce ase_msa_available() helper Philippe Mathieu-Daudé
2020-12-15 22:57 ` [PATCH v2 05/24] target/mips: Simplify msa_reset() Philippe Mathieu-Daudé
2020-12-15 22:57 ` [PATCH v2 06/24] target/mips: Use CP0_Config3 to set MIPS_HFLAG_MSA Philippe Mathieu-Daudé
2020-12-15 22:57 ` [PATCH v2 07/24] target/mips: Simplify MSA TCG logic Philippe Mathieu-Daudé
2020-12-15 22:57 ` [PATCH v2 08/24] target/mips: Remove now unused ASE_MSA definition Philippe Mathieu-Daudé
2020-12-15 22:57 ` [PATCH v2 09/24] target/mips: Alias MSA vector registers on FPU scalar registers Philippe Mathieu-Daudé
2020-12-15 22:57 ` [PATCH v2 10/24] target/mips: Extract msa_translate_init() from mips_tcg_init() Philippe Mathieu-Daudé
2020-12-15 22:57 ` [PATCH v2 11/24] target/mips: Remove CPUMIPSState* argument from gen_msa*() methods Philippe Mathieu-Daudé
2020-12-15 22:57 ` [PATCH v2 12/24] target/mips: Explode gen_msa_branch() as gen_msa_BxZ_V/BxZ() Philippe Mathieu-Daudé
2020-12-15 22:57 ` [PATCH v2 13/24] target/mips: Rename msa_helper.c as mod-msa_helper.c Philippe Mathieu-Daudé
2020-12-15 22:57 ` [PATCH v2 14/24] target/mips: Move msa_reset() to mod-msa_helper.c Philippe Mathieu-Daudé
2020-12-15 23:09 ` Richard Henderson
2020-12-15 22:57 ` [PATCH v2 15/24] target/mips: Extract MSA helpers from op_helper.c Philippe Mathieu-Daudé
2020-12-15 22:57 ` [PATCH v2 16/24] target/mips: Extract MSA helper definitions Philippe Mathieu-Daudé
2020-12-15 22:57 ` [PATCH v2 17/24] target/mips: Declare gen_msa/_branch() in 'translate.h' Philippe Mathieu-Daudé
2020-12-15 23:10 ` Richard Henderson
2020-12-15 22:57 ` [PATCH v2 19/24] target/mips: Introduce decode tree bindings for MSA opcodes Philippe Mathieu-Daudé
2020-12-15 23:11 ` Richard Henderson
2020-12-15 22:57 ` [PATCH v2 20/24] target/mips: Use decode_ase_msa() generated from decodetree Philippe Mathieu-Daudé
2020-12-15 23:15 ` Richard Henderson
2020-12-15 22:57 ` [PATCH v2 21/24] target/mips: Extract LSA/DLSA translation generators Philippe Mathieu-Daudé
2020-12-15 23:17 ` Richard Henderson
2020-12-15 22:57 ` [PATCH v2 22/24] target/mips: Introduce decodetree helpers for MSA LSA/DLSA opcodes Philippe Mathieu-Daudé
2020-12-15 23:19 ` Richard Henderson
2020-12-15 22:57 ` [PATCH v2 23/24] target/mips: Introduce decodetree helpers for Release6 " Philippe Mathieu-Daudé
2020-12-15 23:21 ` Richard Henderson
2020-12-15 22:57 ` [RFC PATCH v2 24/24] target/mips/mod-msa: Pass TCGCond argument to gen_check_zero_element() Philippe Mathieu-Daudé
2020-12-15 23:22 ` Richard Henderson
2021-01-07 18:29 ` [PATCH v2 00/24] target/mips: Convert MSA ASE to decodetree Philippe Mathieu-Daudé
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