From: Jue Wang <juew@google.com>
To: Paolo Bonzini <pbonzini@redhat.com>,
Sean Christopherson <seanjc@google.com>,
Vitaly Kuznetsov <vkuznets@redhat.com>,
Wanpeng Li <wanpengli@tencent.com>,
Jim Mattson <jmattson@google.com>, Joerg Roedel <joro@8bytes.org>,
David Matlack <dmatlack@google.com>
Cc: Tony Luck <tony.luck@intel.com>,
kvm@vger.kernel.org, Greg Thelen <gthelen@google.com>,
Jiaqi Yan <jiaqiyan@google.com>, Jue Wang <juew@google.com>
Subject: [PATCH v5 1/8] KVM: x86: Make APIC_VERSION capture only the magic 0x14UL.
Date: Fri, 10 Jun 2022 10:11:27 -0700 [thread overview]
Message-ID: <20220610171134.772566-2-juew@google.com> (raw)
In-Reply-To: <20220610171134.772566-1-juew@google.com>
Refactor APIC_VERSION so that the maximum number of LVT entries is
inserted at runtime rather than compile time. This will be used in a
subsequent commit to expose the LVT CMCI Register to VMs that support
Corrected Machine Check error counting/signaling
(IA32_MCG_CAP.MCG_CMCI_P=1).
Suggested-by: Sean Christopherson <seanjc@google.com>
Signed-off-by: Jue Wang <juew@google.com>
---
arch/x86/kvm/lapic.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lapic.c
index 66b0eb0bda94..a5caa77e279f 100644
--- a/arch/x86/kvm/lapic.c
+++ b/arch/x86/kvm/lapic.c
@@ -54,7 +54,7 @@
#define PRIo64 "o"
/* 14 is the version for Xeon and Pentium 8.4.8*/
-#define APIC_VERSION (0x14UL | ((KVM_APIC_LVT_NUM - 1) << 16))
+#define APIC_VERSION 0x14UL
#define LAPIC_MMIO_LENGTH (1 << 12)
/* followed define is not in apicdef.h */
#define MAX_APIC_VECTOR 256
@@ -401,7 +401,7 @@ static inline int apic_lvt_nmi_mode(u32 lvt_val)
void kvm_apic_set_version(struct kvm_vcpu *vcpu)
{
struct kvm_lapic *apic = vcpu->arch.apic;
- u32 v = APIC_VERSION;
+ u32 v = APIC_VERSION | ((KVM_APIC_LVT_NUM - 1) << 16);
if (!lapic_in_kernel(vcpu))
return;
--
2.36.1.255.ge46751e96f-goog
next prev parent reply other threads:[~2022-06-10 17:11 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-06-10 17:11 [PATCH v5 0/8] KVM: x86: Add CMCI and UCNA emulation Jue Wang
2022-06-10 17:11 ` Jue Wang [this message]
2022-06-10 17:11 ` [PATCH v5 2/8] KVM: x86: Fill apic_lvt_mask with enums / explicit entries Jue Wang
2022-06-10 17:11 ` [PATCH v5 3/8] KVM: x86: Add APIC_LVTx() macro Jue Wang
2022-06-10 17:11 ` [PATCH v5 4/8] KVM: x86: Add Corrected Machine Check Interrupt (CMCI) emulation to lapic Jue Wang
2022-07-01 2:07 ` Xiaoyao Li
2022-07-01 4:40 ` Jue Wang
2022-07-01 16:53 ` Jue Wang
2022-06-10 17:11 ` [PATCH v5 5/8] KVM: x86: Use kcalloc to allocate the mce_banks array Jue Wang
2022-06-10 17:11 ` [PATCH v5 6/8] KVM: x86: Add emulation for MSR_IA32_MCx_CTL2 MSRs Jue Wang
2022-06-10 17:11 ` [PATCH v5 7/8] KVM: x86: Enable CMCI capability by default and handle injected UCNA errors Jue Wang
2022-06-10 17:11 ` [PATCH v5 8/8] KVM: selftests: Add a self test for CMCI and UCNA emulations Jue Wang
2022-06-23 17:25 ` [PATCH v5 0/8] KVM: x86: Add CMCI and UCNA emulation Paolo Bonzini
2022-06-30 13:48 ` Xiaoyao Li
2022-06-30 14:05 ` Jue Wang
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