From: Jue Wang <juew@google.com>
To: Paolo Bonzini <pbonzini@redhat.com>,
Sean Christopherson <seanjc@google.com>,
Vitaly Kuznetsov <vkuznets@redhat.com>,
Wanpeng Li <wanpengli@tencent.com>,
Jim Mattson <jmattson@google.com>, Joerg Roedel <joro@8bytes.org>,
David Matlack <dmatlack@google.com>
Cc: Tony Luck <tony.luck@intel.com>,
kvm@vger.kernel.org, Greg Thelen <gthelen@google.com>,
Jiaqi Yan <jiaqiyan@google.com>, Jue Wang <juew@google.com>
Subject: [PATCH v5 3/8] KVM: x86: Add APIC_LVTx() macro.
Date: Fri, 10 Jun 2022 10:11:29 -0700 [thread overview]
Message-ID: <20220610171134.772566-4-juew@google.com> (raw)
In-Reply-To: <20220610171134.772566-1-juew@google.com>
An APIC_LVTx macro is introduced to calcualte the APIC_LVTx register
offset based on the index in the lapic_lvt_entry enum. Later patches
will extend the APIC_LVTx macro to support the APIC_LVTCMCI register
in order to implement Corrected Machine Check Interrupt signaling.
Suggested-by: Sean Christopherson <seanjc@google.com>
Signed-off-by: Jue Wang <juew@google.com>
---
arch/x86/kvm/lapic.c | 7 +++----
arch/x86/kvm/lapic.h | 2 ++
2 files changed, 5 insertions(+), 4 deletions(-)
diff --git a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lapic.c
index 73f5cd248a63..db12d2ef1aef 100644
--- a/arch/x86/kvm/lapic.c
+++ b/arch/x86/kvm/lapic.c
@@ -2086,9 +2086,8 @@ static int kvm_lapic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val)
u32 lvt_val;
for (i = 0; i < KVM_APIC_MAX_NR_LVT_ENTRIES; i++) {
- lvt_val = kvm_lapic_get_reg(apic,
- APIC_LVTT + 0x10 * i);
- kvm_lapic_set_reg(apic, APIC_LVTT + 0x10 * i,
+ lvt_val = kvm_lapic_get_reg(apic, APIC_LVTx(i));
+ kvm_lapic_set_reg(apic, APIC_LVTx(i),
lvt_val | APIC_LVT_MASKED);
}
apic_update_lvtt(apic);
@@ -2385,7 +2384,7 @@ void kvm_lapic_reset(struct kvm_vcpu *vcpu, bool init_event)
kvm_apic_set_version(apic->vcpu);
for (i = 0; i < KVM_APIC_MAX_NR_LVT_ENTRIES; i++)
- kvm_lapic_set_reg(apic, APIC_LVTT + 0x10 * i, APIC_LVT_MASKED);
+ kvm_lapic_set_reg(apic, APIC_LVTx(i), APIC_LVT_MASKED);
apic_update_lvtt(apic);
if (kvm_vcpu_is_reset_bsp(vcpu) &&
kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_LINT0_REENABLED))
diff --git a/arch/x86/kvm/lapic.h b/arch/x86/kvm/lapic.h
index 4990793c2034..2d197ed0b8ce 100644
--- a/arch/x86/kvm/lapic.h
+++ b/arch/x86/kvm/lapic.h
@@ -39,6 +39,8 @@ enum lapic_lvt_entry {
KVM_APIC_MAX_NR_LVT_ENTRIES,
};
+#define APIC_LVTx(x) (APIC_LVTT + 0x10 * (x))
+
struct kvm_timer {
struct hrtimer timer;
s64 period; /* unit: ns */
--
2.36.1.255.ge46751e96f-goog
next prev parent reply other threads:[~2022-06-10 17:11 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-06-10 17:11 [PATCH v5 0/8] KVM: x86: Add CMCI and UCNA emulation Jue Wang
2022-06-10 17:11 ` [PATCH v5 1/8] KVM: x86: Make APIC_VERSION capture only the magic 0x14UL Jue Wang
2022-06-10 17:11 ` [PATCH v5 2/8] KVM: x86: Fill apic_lvt_mask with enums / explicit entries Jue Wang
2022-06-10 17:11 ` Jue Wang [this message]
2022-06-10 17:11 ` [PATCH v5 4/8] KVM: x86: Add Corrected Machine Check Interrupt (CMCI) emulation to lapic Jue Wang
2022-07-01 2:07 ` Xiaoyao Li
2022-07-01 4:40 ` Jue Wang
2022-07-01 16:53 ` Jue Wang
2022-06-10 17:11 ` [PATCH v5 5/8] KVM: x86: Use kcalloc to allocate the mce_banks array Jue Wang
2022-06-10 17:11 ` [PATCH v5 6/8] KVM: x86: Add emulation for MSR_IA32_MCx_CTL2 MSRs Jue Wang
2022-06-10 17:11 ` [PATCH v5 7/8] KVM: x86: Enable CMCI capability by default and handle injected UCNA errors Jue Wang
2022-06-10 17:11 ` [PATCH v5 8/8] KVM: selftests: Add a self test for CMCI and UCNA emulations Jue Wang
2022-06-23 17:25 ` [PATCH v5 0/8] KVM: x86: Add CMCI and UCNA emulation Paolo Bonzini
2022-06-30 13:48 ` Xiaoyao Li
2022-06-30 14:05 ` Jue Wang
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