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From: Like Xu <like.xu.linux@gmail.com>
To: Sean Christopherson <seanjc@google.com>
Cc: Paolo Bonzini <pbonzini@redhat.com>,
	kvm@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: [PATCH V5 02/10] KVM: x86/pmu: Return #GP if user sets the GLOBAL_STATUS reserved bits
Date: Mon, 10 Apr 2023 18:50:48 +0800	[thread overview]
Message-ID: <20230410105056.60973-3-likexu@tencent.com> (raw)
In-Reply-To: <20230410105056.60973-1-likexu@tencent.com>

From: Like Xu <likexu@tencent.com>

Return #GP if KVM user space attempts to set a reserved bit for guest.
If the user space sets reserved bits when restoring the MSR_CORE_
PERF_GLOBAL_STATUS register, these bits will be accidentally returned
when the guest runs a read access to this register, and cannot be cleared
up inside the guest, which makes the guest's PMI handler very confused.

Note, reusing global_ovf_ctrl_mask as global_status_mask will be broken
if KVM supports higher versions of Intel arch pmu.

Signed-off-by: Like Xu <likexu@tencent.com>
---
 arch/x86/kvm/vmx/pmu_intel.c | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/arch/x86/kvm/vmx/pmu_intel.c b/arch/x86/kvm/vmx/pmu_intel.c
index 1f9c3e916a21..343b3182b7f4 100644
--- a/arch/x86/kvm/vmx/pmu_intel.c
+++ b/arch/x86/kvm/vmx/pmu_intel.c
@@ -399,7 +399,11 @@ static int intel_pmu_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
 			reprogram_fixed_counters(pmu, data);
 		break;
 	case MSR_CORE_PERF_GLOBAL_STATUS:
-		if (!msr_info->host_initiated)
+		/*
+		 * Caution, the assumption here is that some of the bits (such as
+		 * ASCI, CTR_FREEZE, and LBR_FREEZE) are not yet supported by KVM.
+		 */
+		if (!msr_info->host_initiated || (data & pmu->global_ovf_ctrl_mask))
 			return 1; /* RO MSR */
 
 		pmu->global_status = data;
-- 
2.40.0


  parent reply	other threads:[~2023-04-10 10:51 UTC|newest]

Thread overview: 19+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-04-10 10:50 [PATCH V5 00/10] KVM: x86: Add AMD Guest PerfMonV2 PMU support Like Xu
2023-04-10 10:50 ` [PATCH V5 01/10] KVM: x86/pmu: Expose reprogram_counters() in pmu.h Like Xu
2023-04-10 10:50 ` Like Xu [this message]
2023-04-10 10:50 ` [PATCH V5 03/10] KVM: x86/pmu: Make part of the Intel v2 PMU MSRs handling x86 generic Like Xu
2023-04-10 10:50 ` [PATCH V5 04/10] KVM: x86: Explicitly zero cpuid "0xa" leaf when PMU is disabled Like Xu
2023-04-10 10:50 ` [PATCH V5 05/10] KVM: x86/pmu: Disable vPMU if the minimum num of counters isn't met Like Xu
2023-04-11  5:36   ` Jim Mattson
2023-04-11  6:17     ` Like Xu
2023-04-11 12:58       ` Jim Mattson
2023-04-11 13:17         ` Like Xu
2023-04-11 14:58           ` Jim Mattson
2023-04-19  9:34             ` Like Xu
2023-05-24 23:37               ` Sean Christopherson
2023-05-29 14:25                 ` Like Xu
2023-04-10 10:50 ` [PATCH V5 06/10] KVM: x86/pmu: Forget PERFCTR_CORE if the min " Like Xu
2023-04-10 10:50 ` [PATCH V5 07/10] KVM: x86/pmu: Constrain the num of guest counters with kvm_pmu_cap Like Xu
2023-04-10 10:50 ` [PATCH V5 08/10] KVM: x86/cpuid: Add a KVM-only leaf to redirect AMD PerfMonV2 flag Like Xu
2023-04-10 10:50 ` [PATCH V5 09/10] KVM: x86/svm/pmu: Add AMD PerfMonV2 support Like Xu
2023-04-10 10:50 ` [PATCH V5 10/10] KVM: x86/cpuid: Add AMD CPUID ExtPerfMonAndDbg leaf 0x80000022 Like Xu

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