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From: Like Xu <like.xu.linux@gmail.com>
To: Sean Christopherson <seanjc@google.com>
Cc: Paolo Bonzini <pbonzini@redhat.com>,
	kvm@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: [PATCH V5 05/10] KVM: x86/pmu: Disable vPMU if the minimum num of counters isn't met
Date: Mon, 10 Apr 2023 18:50:51 +0800	[thread overview]
Message-ID: <20230410105056.60973-6-likexu@tencent.com> (raw)
In-Reply-To: <20230410105056.60973-1-likexu@tencent.com>

From: Like Xu <likexu@tencent.com>

Disable PMU support when running on AMD and perf reports fewer than four
general purpose counters. All AMD PMUs must define at least four counters
due to AMD's legacy architecture hardcoding the number of counters
without providing a way to enumerate the number of counters to software,
e.g. from AMD's APM:

 The legacy architecture defines four performance counters (PerfCtrn)
 and corresponding event-select registers (PerfEvtSeln).

Virtualizing fewer than four counters can lead to guest instability as
software expects four counters to be available.

Suggested-by: Sean Christopherson <seanjc@google.com>
Signed-off-by: Like Xu <likexu@tencent.com>
---
 arch/x86/kvm/pmu.h | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/x86/kvm/pmu.h b/arch/x86/kvm/pmu.h
index dd7c7d4ffe3b..002b527360f4 100644
--- a/arch/x86/kvm/pmu.h
+++ b/arch/x86/kvm/pmu.h
@@ -182,6 +182,9 @@ static inline void kvm_init_pmu_capability(const struct kvm_pmu_ops *pmu_ops)
 			enable_pmu = false;
 	}
 
+	if (!is_intel && kvm_pmu_cap.num_counters_gp < AMD64_NUM_COUNTERS)
+		enable_pmu = false;
+
 	if (!enable_pmu) {
 		memset(&kvm_pmu_cap, 0, sizeof(kvm_pmu_cap));
 		return;
-- 
2.40.0


  parent reply	other threads:[~2023-04-10 10:51 UTC|newest]

Thread overview: 19+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-04-10 10:50 [PATCH V5 00/10] KVM: x86: Add AMD Guest PerfMonV2 PMU support Like Xu
2023-04-10 10:50 ` [PATCH V5 01/10] KVM: x86/pmu: Expose reprogram_counters() in pmu.h Like Xu
2023-04-10 10:50 ` [PATCH V5 02/10] KVM: x86/pmu: Return #GP if user sets the GLOBAL_STATUS reserved bits Like Xu
2023-04-10 10:50 ` [PATCH V5 03/10] KVM: x86/pmu: Make part of the Intel v2 PMU MSRs handling x86 generic Like Xu
2023-04-10 10:50 ` [PATCH V5 04/10] KVM: x86: Explicitly zero cpuid "0xa" leaf when PMU is disabled Like Xu
2023-04-10 10:50 ` Like Xu [this message]
2023-04-11  5:36   ` [PATCH V5 05/10] KVM: x86/pmu: Disable vPMU if the minimum num of counters isn't met Jim Mattson
2023-04-11  6:17     ` Like Xu
2023-04-11 12:58       ` Jim Mattson
2023-04-11 13:17         ` Like Xu
2023-04-11 14:58           ` Jim Mattson
2023-04-19  9:34             ` Like Xu
2023-05-24 23:37               ` Sean Christopherson
2023-05-29 14:25                 ` Like Xu
2023-04-10 10:50 ` [PATCH V5 06/10] KVM: x86/pmu: Forget PERFCTR_CORE if the min " Like Xu
2023-04-10 10:50 ` [PATCH V5 07/10] KVM: x86/pmu: Constrain the num of guest counters with kvm_pmu_cap Like Xu
2023-04-10 10:50 ` [PATCH V5 08/10] KVM: x86/cpuid: Add a KVM-only leaf to redirect AMD PerfMonV2 flag Like Xu
2023-04-10 10:50 ` [PATCH V5 09/10] KVM: x86/svm/pmu: Add AMD PerfMonV2 support Like Xu
2023-04-10 10:50 ` [PATCH V5 10/10] KVM: x86/cpuid: Add AMD CPUID ExtPerfMonAndDbg leaf 0x80000022 Like Xu

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