* [PATCH v5 2/5] target/riscv: check the in-kernel irqchip support [not found] <20230713084405.24545-1-yongxuan.wang@sifive.com> @ 2023-07-13 8:43 ` Yong-Xuan Wang 2023-07-13 9:26 ` Andrew Jones 2023-07-13 8:43 ` [PATCH v5 3/5] target/riscv: Create an KVM AIA irqchip Yong-Xuan Wang 1 sibling, 1 reply; 4+ messages in thread From: Yong-Xuan Wang @ 2023-07-13 8:43 UTC (permalink / raw) To: qemu-devel, qemu-riscv Cc: rkanwal, anup, dbarboza, ajones, atishp, vincent.chen, greentime.hu, frank.chang, jim.shu, Yong-Xuan Wang, Palmer Dabbelt, Alistair Francis, Bin Meng, Weiwei Li, Liu Zhiwei, Paolo Bonzini, kvm We check the in-kernel irqchip support when using KVM acceleration. Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com> Reviewed-by: Jim Shu <jim.shu@sifive.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> --- target/riscv/kvm.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c index 9d8a8982f9..005e054604 100644 --- a/target/riscv/kvm.c +++ b/target/riscv/kvm.c @@ -914,7 +914,15 @@ int kvm_arch_init(MachineState *ms, KVMState *s) int kvm_arch_irqchip_create(KVMState *s) { - return 0; + if (kvm_kernel_irqchip_split()) { + error_report("-machine kernel_irqchip=split is not supported on RISC-V."); + exit(1); + } + + /* + * We can create the VAIA using the newer device control API. + */ + return kvm_check_extension(s, KVM_CAP_DEVICE_CTRL); } int kvm_arch_process_async_events(CPUState *cs) -- 2.17.1 ^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [PATCH v5 2/5] target/riscv: check the in-kernel irqchip support 2023-07-13 8:43 ` [PATCH v5 2/5] target/riscv: check the in-kernel irqchip support Yong-Xuan Wang @ 2023-07-13 9:26 ` Andrew Jones 0 siblings, 0 replies; 4+ messages in thread From: Andrew Jones @ 2023-07-13 9:26 UTC (permalink / raw) To: Yong-Xuan Wang Cc: qemu-devel, qemu-riscv, rkanwal, anup, dbarboza, atishp, vincent.chen, greentime.hu, frank.chang, jim.shu, Palmer Dabbelt, Alistair Francis, Bin Meng, Weiwei Li, Liu Zhiwei, Paolo Bonzini, kvm On Thu, Jul 13, 2023 at 08:43:54AM +0000, Yong-Xuan Wang wrote: > We check the in-kernel irqchip support when using KVM acceleration. > > Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com> > Reviewed-by: Jim Shu <jim.shu@sifive.com> > Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> > --- > target/riscv/kvm.c | 10 +++++++++- > 1 file changed, 9 insertions(+), 1 deletion(-) > > diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c > index 9d8a8982f9..005e054604 100644 > --- a/target/riscv/kvm.c > +++ b/target/riscv/kvm.c > @@ -914,7 +914,15 @@ int kvm_arch_init(MachineState *ms, KVMState *s) > > int kvm_arch_irqchip_create(KVMState *s) > { > - return 0; > + if (kvm_kernel_irqchip_split()) { > + error_report("-machine kernel_irqchip=split is not supported on RISC-V."); > + exit(1); > + } > + > + /* > + * We can create the VAIA using the newer device control API. > + */ > + return kvm_check_extension(s, KVM_CAP_DEVICE_CTRL); > } > > int kvm_arch_process_async_events(CPUState *cs) > -- > 2.17.1 > Reviewed-by: Andrew Jones <ajones@ventanamicro.com> ^ permalink raw reply [flat|nested] 4+ messages in thread
* [PATCH v5 3/5] target/riscv: Create an KVM AIA irqchip [not found] <20230713084405.24545-1-yongxuan.wang@sifive.com> 2023-07-13 8:43 ` [PATCH v5 2/5] target/riscv: check the in-kernel irqchip support Yong-Xuan Wang @ 2023-07-13 8:43 ` Yong-Xuan Wang 2023-07-13 9:36 ` Andrew Jones 1 sibling, 1 reply; 4+ messages in thread From: Yong-Xuan Wang @ 2023-07-13 8:43 UTC (permalink / raw) To: qemu-devel, qemu-riscv Cc: rkanwal, anup, dbarboza, ajones, atishp, vincent.chen, greentime.hu, frank.chang, jim.shu, Yong-Xuan Wang, Palmer Dabbelt, Alistair Francis, Bin Meng, Weiwei Li, Liu Zhiwei, Paolo Bonzini, kvm We create a vAIA chip by using the KVM_DEV_TYPE_RISCV_AIA and then set up the chip with the KVM_DEV_RISCV_AIA_GRP_* APIs. Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com> Reviewed-by: Jim Shu <jim.shu@sifive.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> --- target/riscv/kvm.c | 160 +++++++++++++++++++++++++++++++++++++++ target/riscv/kvm_riscv.h | 6 ++ 2 files changed, 166 insertions(+) diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c index 005e054604..64156c15ec 100644 --- a/target/riscv/kvm.c +++ b/target/riscv/kvm.c @@ -36,6 +36,7 @@ #include "exec/address-spaces.h" #include "hw/boards.h" #include "hw/irq.h" +#include "hw/intc/riscv_imsic.h" #include "qemu/log.h" #include "hw/loader.h" #include "kvm_riscv.h" @@ -43,6 +44,7 @@ #include "chardev/char-fe.h" #include "migration/migration.h" #include "sysemu/runstate.h" +#include "hw/riscv/numa.h" static uint64_t kvm_riscv_reg_id(CPURISCVState *env, uint64_t type, uint64_t idx) @@ -1026,3 +1028,161 @@ bool kvm_arch_cpu_check_are_resettable(void) void kvm_arch_accel_class_init(ObjectClass *oc) { } + +char *kvm_aia_mode_str(uint64_t aia_mode) +{ + const char *val; + + switch (aia_mode) { + case KVM_DEV_RISCV_AIA_MODE_EMUL: + return "emul"; + case KVM_DEV_RISCV_AIA_MODE_HWACCEL: + return "hwaccel"; + case KVM_DEV_RISCV_AIA_MODE_AUTO: + default: + return "auto"; + }; +} + +void kvm_riscv_aia_create(MachineState *machine, + uint64_t aia_mode, uint64_t group_shift, + uint64_t aia_irq_num, uint64_t aia_msi_num, + uint64_t aplic_base, uint64_t imsic_base, + uint64_t guest_num) +{ + int ret, i; + int aia_fd = -1; + uint64_t default_aia_mode; + uint64_t socket_count = riscv_socket_count(machine); + uint64_t max_hart_per_socket = 0; + uint64_t socket, base_hart, hart_count, socket_imsic_base, imsic_addr; + uint64_t socket_bits, hart_bits, guest_bits; + + aia_fd = kvm_create_device(kvm_state, KVM_DEV_TYPE_RISCV_AIA, false); + + if (aia_fd < 0) { + error_report("Unable to create in-kernel irqchip"); + exit(1); + } + + ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, + KVM_DEV_RISCV_AIA_CONFIG_MODE, + &default_aia_mode, false, NULL); + if (ret < 0) { + error_report("KVM AIA: failed to get current KVM AIA mode"); + exit(1); + } + qemu_log("KVM AIA: default mode is %s\n", + kvm_aia_mode_str(default_aia_mode)); + + if (default_aia_mode != aia_mode) { + ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, + KVM_DEV_RISCV_AIA_CONFIG_MODE, + &aia_mode, true, NULL); + if (ret < 0) + warn_report("KVM AIA: failed to set KVM AIA mode"); + else + qemu_log("KVM AIA: set current mode to %s\n", + kvm_aia_mode_str(aia_mode)); + } + + ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, + KVM_DEV_RISCV_AIA_CONFIG_SRCS, + &aia_irq_num, true, NULL); + if (ret < 0) { + error_report("KVM AIA: failed to set number of input irq lines"); + exit(1); + } + + ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, + KVM_DEV_RISCV_AIA_CONFIG_IDS, + &aia_msi_num, true, NULL); + if (ret < 0) { + error_report("KVM AIA: failed to set number of msi"); + exit(1); + } + + socket_bits = find_last_bit(&socket_count, BITS_PER_LONG) + 1; + ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, + KVM_DEV_RISCV_AIA_CONFIG_GROUP_BITS, + &socket_bits, true, NULL); + if (ret < 0) { + error_report("KVM AIA: failed to set group_bits"); + exit(1); + } + + ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, + KVM_DEV_RISCV_AIA_CONFIG_GROUP_SHIFT, + &group_shift, true, NULL); + if (ret < 0) { + error_report("KVM AIA: failed to set group_shift"); + exit(1); + } + + guest_bits = guest_num == 0 ? 0 : + find_last_bit(&guest_num, BITS_PER_LONG) + 1; + ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, + KVM_DEV_RISCV_AIA_CONFIG_GUEST_BITS, + &guest_bits, true, NULL); + if (ret < 0) { + error_report("KVM AIA: failed to set guest_bits"); + exit(1); + } + + ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_ADDR, + KVM_DEV_RISCV_AIA_ADDR_APLIC, + &aplic_base, true, NULL); + if (ret < 0) { + error_report("KVM AIA: failed to set the base address of APLIC"); + exit(1); + } + + for (socket = 0; socket < socket_count; socket++) { + socket_imsic_base = imsic_base + socket * (1U << group_shift); + hart_count = riscv_socket_hart_count(machine, socket); + base_hart = riscv_socket_first_hartid(machine, socket); + + if (max_hart_per_socket < hart_count) { + max_hart_per_socket = hart_count; + } + + for (i = 0; i < hart_count; i++) { + imsic_addr = socket_imsic_base + i * IMSIC_HART_SIZE(guest_bits); + ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_ADDR, + KVM_DEV_RISCV_AIA_ADDR_IMSIC(i + base_hart), + &imsic_addr, true, NULL); + if (ret < 0) { + error_report("KVM AIA: failed to set the address of IMSICs"); + exit(1); + } + } + } + + hart_bits = find_last_bit(&max_hart_per_socket, BITS_PER_LONG) + 1; + ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, + KVM_DEV_RISCV_AIA_CONFIG_HART_BITS, + &hart_bits, true, NULL); + if (ret < 0) { + error_report("KVM AIA: failed to set hart_bits"); + exit(1); + } + + if (kvm_has_gsi_routing()) { + for (uint64_t idx = 0; idx < aia_irq_num + 1; ++idx) { + /* KVM AIA only has one APLIC instance */ + kvm_irqchip_add_irq_route(kvm_state, idx, 0, idx); + } + kvm_gsi_routing_allowed = true; + kvm_irqchip_commit_routes(kvm_state); + } + + ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CTRL, + KVM_DEV_RISCV_AIA_CTRL_INIT, + NULL, true, NULL); + if (ret < 0) { + error_report("KVM AIA: initialized fail"); + exit(1); + } + + kvm_msi_via_irqfd_allowed = kvm_irqfds_enabled(); +} diff --git a/target/riscv/kvm_riscv.h b/target/riscv/kvm_riscv.h index e3ba935808..c6745dd29a 100644 --- a/target/riscv/kvm_riscv.h +++ b/target/riscv/kvm_riscv.h @@ -22,5 +22,11 @@ void kvm_riscv_init_user_properties(Object *cpu_obj); void kvm_riscv_reset_vcpu(RISCVCPU *cpu); void kvm_riscv_set_irq(RISCVCPU *cpu, int irq, int level); +char *kvm_aia_mode_str(uint64_t aia_mode); +void kvm_riscv_aia_create(MachineState *machine, + uint64_t aia_mode, uint64_t group_shift, + uint64_t aia_irq_num, uint64_t aia_msi_num, + uint64_t aplic_base, uint64_t imsic_base, + uint64_t guest_num); #endif -- 2.17.1 ^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [PATCH v5 3/5] target/riscv: Create an KVM AIA irqchip 2023-07-13 8:43 ` [PATCH v5 3/5] target/riscv: Create an KVM AIA irqchip Yong-Xuan Wang @ 2023-07-13 9:36 ` Andrew Jones 0 siblings, 0 replies; 4+ messages in thread From: Andrew Jones @ 2023-07-13 9:36 UTC (permalink / raw) To: Yong-Xuan Wang Cc: qemu-devel, qemu-riscv, rkanwal, anup, dbarboza, atishp, vincent.chen, greentime.hu, frank.chang, jim.shu, Palmer Dabbelt, Alistair Francis, Bin Meng, Weiwei Li, Liu Zhiwei, Paolo Bonzini, kvm On Thu, Jul 13, 2023 at 08:43:55AM +0000, Yong-Xuan Wang wrote: > We create a vAIA chip by using the KVM_DEV_TYPE_RISCV_AIA and then set up > the chip with the KVM_DEV_RISCV_AIA_GRP_* APIs. > > Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com> > Reviewed-by: Jim Shu <jim.shu@sifive.com> > Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> > --- > target/riscv/kvm.c | 160 +++++++++++++++++++++++++++++++++++++++ > target/riscv/kvm_riscv.h | 6 ++ > 2 files changed, 166 insertions(+) > > diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c > index 005e054604..64156c15ec 100644 > --- a/target/riscv/kvm.c > +++ b/target/riscv/kvm.c > @@ -36,6 +36,7 @@ > #include "exec/address-spaces.h" > #include "hw/boards.h" > #include "hw/irq.h" > +#include "hw/intc/riscv_imsic.h" > #include "qemu/log.h" > #include "hw/loader.h" > #include "kvm_riscv.h" > @@ -43,6 +44,7 @@ > #include "chardev/char-fe.h" > #include "migration/migration.h" > #include "sysemu/runstate.h" > +#include "hw/riscv/numa.h" > > static uint64_t kvm_riscv_reg_id(CPURISCVState *env, uint64_t type, > uint64_t idx) > @@ -1026,3 +1028,161 @@ bool kvm_arch_cpu_check_are_resettable(void) > void kvm_arch_accel_class_init(ObjectClass *oc) > { > } > + > +char *kvm_aia_mode_str(uint64_t aia_mode) > +{ > + const char *val; > + > + switch (aia_mode) { > + case KVM_DEV_RISCV_AIA_MODE_EMUL: > + return "emul"; > + case KVM_DEV_RISCV_AIA_MODE_HWACCEL: > + return "hwaccel"; > + case KVM_DEV_RISCV_AIA_MODE_AUTO: > + default: > + return "auto"; > + }; > +} > + > +void kvm_riscv_aia_create(MachineState *machine, > + uint64_t aia_mode, uint64_t group_shift, > + uint64_t aia_irq_num, uint64_t aia_msi_num, > + uint64_t aplic_base, uint64_t imsic_base, > + uint64_t guest_num) > +{ > + int ret, i; > + int aia_fd = -1; > + uint64_t default_aia_mode; > + uint64_t socket_count = riscv_socket_count(machine); > + uint64_t max_hart_per_socket = 0; > + uint64_t socket, base_hart, hart_count, socket_imsic_base, imsic_addr; > + uint64_t socket_bits, hart_bits, guest_bits; > + > + aia_fd = kvm_create_device(kvm_state, KVM_DEV_TYPE_RISCV_AIA, false); > + > + if (aia_fd < 0) { > + error_report("Unable to create in-kernel irqchip"); > + exit(1); > + } > + > + ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, > + KVM_DEV_RISCV_AIA_CONFIG_MODE, > + &default_aia_mode, false, NULL); > + if (ret < 0) { > + error_report("KVM AIA: failed to get current KVM AIA mode"); > + exit(1); > + } > + qemu_log("KVM AIA: default mode is %s\n", > + kvm_aia_mode_str(default_aia_mode)); > + > + if (default_aia_mode != aia_mode) { > + ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, > + KVM_DEV_RISCV_AIA_CONFIG_MODE, > + &aia_mode, true, NULL); > + if (ret < 0) > + warn_report("KVM AIA: failed to set KVM AIA mode"); > + else > + qemu_log("KVM AIA: set current mode to %s\n", > + kvm_aia_mode_str(aia_mode)); > + } > + > + ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, > + KVM_DEV_RISCV_AIA_CONFIG_SRCS, > + &aia_irq_num, true, NULL); > + if (ret < 0) { > + error_report("KVM AIA: failed to set number of input irq lines"); > + exit(1); > + } > + > + ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, > + KVM_DEV_RISCV_AIA_CONFIG_IDS, > + &aia_msi_num, true, NULL); > + if (ret < 0) { > + error_report("KVM AIA: failed to set number of msi"); > + exit(1); > + } > + > + socket_bits = find_last_bit(&socket_count, BITS_PER_LONG) + 1; > + ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, > + KVM_DEV_RISCV_AIA_CONFIG_GROUP_BITS, > + &socket_bits, true, NULL); > + if (ret < 0) { > + error_report("KVM AIA: failed to set group_bits"); > + exit(1); > + } > + > + ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, > + KVM_DEV_RISCV_AIA_CONFIG_GROUP_SHIFT, > + &group_shift, true, NULL); > + if (ret < 0) { > + error_report("KVM AIA: failed to set group_shift"); > + exit(1); > + } > + > + guest_bits = guest_num == 0 ? 0 : > + find_last_bit(&guest_num, BITS_PER_LONG) + 1; > + ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, > + KVM_DEV_RISCV_AIA_CONFIG_GUEST_BITS, > + &guest_bits, true, NULL); > + if (ret < 0) { > + error_report("KVM AIA: failed to set guest_bits"); > + exit(1); > + } > + > + ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_ADDR, > + KVM_DEV_RISCV_AIA_ADDR_APLIC, > + &aplic_base, true, NULL); > + if (ret < 0) { > + error_report("KVM AIA: failed to set the base address of APLIC"); > + exit(1); > + } > + > + for (socket = 0; socket < socket_count; socket++) { > + socket_imsic_base = imsic_base + socket * (1U << group_shift); > + hart_count = riscv_socket_hart_count(machine, socket); > + base_hart = riscv_socket_first_hartid(machine, socket); > + > + if (max_hart_per_socket < hart_count) { > + max_hart_per_socket = hart_count; > + } > + > + for (i = 0; i < hart_count; i++) { > + imsic_addr = socket_imsic_base + i * IMSIC_HART_SIZE(guest_bits); > + ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_ADDR, > + KVM_DEV_RISCV_AIA_ADDR_IMSIC(i + base_hart), > + &imsic_addr, true, NULL); > + if (ret < 0) { > + error_report("KVM AIA: failed to set the address of IMSICs"); Maybe not worth respinning for, but I'd probably include the hart index in this output error_report("KVM AIA: failed to set the IMSIC address for hart %d", i); > + exit(1); > + } > + } > + } > + > + hart_bits = find_last_bit(&max_hart_per_socket, BITS_PER_LONG) + 1; > + ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, > + KVM_DEV_RISCV_AIA_CONFIG_HART_BITS, > + &hart_bits, true, NULL); > + if (ret < 0) { > + error_report("KVM AIA: failed to set hart_bits"); > + exit(1); > + } > + > + if (kvm_has_gsi_routing()) { > + for (uint64_t idx = 0; idx < aia_irq_num + 1; ++idx) { > + /* KVM AIA only has one APLIC instance */ > + kvm_irqchip_add_irq_route(kvm_state, idx, 0, idx); > + } > + kvm_gsi_routing_allowed = true; > + kvm_irqchip_commit_routes(kvm_state); > + } > + > + ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CTRL, > + KVM_DEV_RISCV_AIA_CTRL_INIT, > + NULL, true, NULL); > + if (ret < 0) { > + error_report("KVM AIA: initialized fail"); > + exit(1); > + } > + > + kvm_msi_via_irqfd_allowed = kvm_irqfds_enabled(); > +} > diff --git a/target/riscv/kvm_riscv.h b/target/riscv/kvm_riscv.h > index e3ba935808..c6745dd29a 100644 > --- a/target/riscv/kvm_riscv.h > +++ b/target/riscv/kvm_riscv.h > @@ -22,5 +22,11 @@ > void kvm_riscv_init_user_properties(Object *cpu_obj); > void kvm_riscv_reset_vcpu(RISCVCPU *cpu); > void kvm_riscv_set_irq(RISCVCPU *cpu, int irq, int level); > +char *kvm_aia_mode_str(uint64_t aia_mode); > +void kvm_riscv_aia_create(MachineState *machine, > + uint64_t aia_mode, uint64_t group_shift, > + uint64_t aia_irq_num, uint64_t aia_msi_num, > + uint64_t aplic_base, uint64_t imsic_base, > + uint64_t guest_num); > > #endif > -- > 2.17.1 > Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Thanks, drew ^ permalink raw reply [flat|nested] 4+ messages in thread
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[not found] <20230713084405.24545-1-yongxuan.wang@sifive.com>
2023-07-13 8:43 ` [PATCH v5 2/5] target/riscv: check the in-kernel irqchip support Yong-Xuan Wang
2023-07-13 9:26 ` Andrew Jones
2023-07-13 8:43 ` [PATCH v5 3/5] target/riscv: Create an KVM AIA irqchip Yong-Xuan Wang
2023-07-13 9:36 ` Andrew Jones
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