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From: Samuel Holland <samuel.holland@sifive.com>
To: kvm@vger.kernel.org
Cc: Samuel Holland <samuel.holland@sifive.com>
Subject: [kvm-unit-tests PATCH 1/3] riscv: Add Image header to flat binaries
Date: Mon,  9 Dec 2024 22:44:40 -0600	[thread overview]
Message-ID: <20241210044442.91736-2-samuel.holland@sifive.com> (raw)
In-Reply-To: <20241210044442.91736-1-samuel.holland@sifive.com>

This allows flat binaries to be understood by U-Boot's booti command and
its PXE boot flow.

Signed-off-by: Samuel Holland <samuel.holland@sifive.com>
---
 riscv/cstart.S | 16 +++++++++++++++-
 1 file changed, 15 insertions(+), 1 deletion(-)

diff --git a/riscv/cstart.S b/riscv/cstart.S
index b7ee9b9c..106737a1 100644
--- a/riscv/cstart.S
+++ b/riscv/cstart.S
@@ -39,15 +39,29 @@
  * The hartid of the current core is in a0
  * The address of the devicetree is in a1
  *
- * See Linux kernel doc Documentation/riscv/boot.rst
+ * See Linux kernel doc Documentation/arch/riscv/boot.rst and
+ * Documentation/arch/riscv/boot-image-header.rst
  */
 .global start
 start:
+	j	1f
+	.balign	8
+	.dword	0				// text offset
+	.dword	stacktop - ImageBase		// image size
+	.dword	0				// flags
+	.word	(0 << 16 | 2 << 0)		// version
+	.word	0				// res1
+	.dword	0				// res2
+	.ascii	"RISCV\0\0\0"			// magic
+	.ascii	"RSC\x05"			// magic2
+	.word	0				// res3
+
 	/*
 	 * Stash the hartid in scratch and shift the dtb address into a0.
 	 * thread_info_init() will later promote scratch to point at thread
 	 * local storage.
 	 */
+1:
 	csrw	CSR_SSCRATCH, a0
 	mv	a0, a1
 
-- 
2.39.3 (Apple Git-146)


  reply	other threads:[~2024-12-10  4:48 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-12-10  4:44 [kvm-unit-tests PATCH 0/3] riscv: Improved bare metal support Samuel Holland
2024-12-10  4:44 ` Samuel Holland [this message]
2024-12-18 10:13   ` [kvm-unit-tests PATCH 1/3] riscv: Add Image header to flat binaries Andrew Jones
2024-12-18 23:06     ` Samuel Holland
2024-12-19  8:27       ` Andrew Jones
2025-03-22  9:18       ` Andrew Jones
2024-12-10  4:44 ` [kvm-unit-tests PATCH 2/3] riscv: Rate limit UART output to avoid FIFO overflows Samuel Holland
2024-12-10  4:44 ` [kvm-unit-tests PATCH 3/3] riscv: Support UARTs with different I/O widths Samuel Holland
2025-03-22 10:16   ` Andrew Jones
2024-12-18 10:06 ` [kvm-unit-tests PATCH 0/3] riscv: Improved bare metal support Andrew Jones
2025-03-22  9:16 ` [kvm-unit-tests PATCH 4/3] riscv: Support using SBI DBCN for the console Andrew Jones
2025-03-22  9:19 ` [kvm-unit-tests PATCH 0/3] riscv: Improved bare metal support Andrew Jones
2025-03-22 10:45 ` Andrew Jones

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