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From: Alex Williamson <alex@shazbot.org>
To: Longfang Liu <liulongfang@huawei.com>
Cc: <alex.williamson@redhat.com>, <jgg@nvidia.com>,
	<herbert@gondor.apana.org.au>, <shameerkolothum@gmail.com>,
	<jonathan.cameron@huawei.com>, <linux-crypto@vger.kernel.org>,
	<kvm@vger.kernel.org>, <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v12 2/2] hisi_acc_vfio_pci: adapt to new migration configuration
Date: Wed, 5 Nov 2025 15:32:33 -0700	[thread overview]
Message-ID: <20251105153233.59a504ae.alex@shazbot.org> (raw)
In-Reply-To: <20251030015744.131771-3-liulongfang@huawei.com>

On Thu, 30 Oct 2025 09:57:44 +0800
Longfang Liu <liulongfang@huawei.com> wrote:
> diff --git a/drivers/vfio/pci/hisilicon/hisi_acc_vfio_pci.h b/drivers/vfio/pci/hisilicon/hisi_acc_vfio_pci.h
> index 91002ceeebc1..419a378c3d1d 100644
> --- a/drivers/vfio/pci/hisilicon/hisi_acc_vfio_pci.h
> +++ b/drivers/vfio/pci/hisilicon/hisi_acc_vfio_pci.h
> @@ -50,8 +50,10 @@
>  #define QM_QUE_ISO_CFG_V	0x0030
>  #define QM_PAGE_SIZE		0x0034
>  
> -#define QM_EQC_DW0		0X8000
> -#define QM_AEQC_DW0		0X8020
> +#define QM_EQC_VF_DW0		0X8000
> +#define QM_AEQC_VF_DW0		0X8020
> +#define QM_EQC_PF_DW0		0x1c00
> +#define QM_AEQC_PF_DW0		0x1c20
>  
>  #define ACC_DRV_MAJOR_VER 1
>  #define ACC_DRV_MINOR_VER 0
> @@ -59,6 +61,22 @@
>  #define ACC_DEV_MAGIC_V1	0XCDCDCDCDFEEDAACC
>  #define ACC_DEV_MAGIC_V2	0xAACCFEEDDECADEDE
>  
> +#define QM_MIG_REGION_OFFSET		0x180000
> +#define QM_MIG_REGION_SIZE		0x2000
> +
> +/**
> + * On HW_ACC_MIG_VF_CTRL mode, the configuration domain supporting live
> + * migration functionality is located in the latter 32KB of the VF's BAR2.
> + * The Guest is only provided with the first 32KB of the VF's BAR2.
> + * On HW_ACC_MIG_PF_CTRL mode, the configuration domain supporting live
> + * migration functionality is located in the PF's BAR2, and the entire 64KB
> + * of the VF's BAR2 is allocated to the Guest.
> + */
> +enum hw_drv_mode {
> +	HW_ACC_MIG_VF_CTRL = 0,
> +	HW_ACC_MIG_PF_CTRL,
> +};
> +
>  struct acc_vf_data {
>  #define QM_MATCH_SIZE offsetofend(struct acc_vf_data, qm_rsv_state)
>  	/* QM match information */
> @@ -125,6 +143,7 @@ struct hisi_acc_vf_core_device {
>  	struct pci_dev *vf_dev;
>  	struct hisi_qm *pf_qm;
>  	struct hisi_qm vf_qm;
> +	int drv_mode;

I can fix this on commit rather than send a new version, but is there
any reason we wouldn't make use of the enum here:

	enum hw_drv_mode drv_mode;

?  Thanks,

Alex

>  	/*
>  	 * vf_qm_state represents the QM_VF_STATE register value.
>  	 * It is set by Guest driver for the ACC VF dev indicating


  reply	other threads:[~2025-11-05 22:32 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-10-30  1:57 [PATCH v12 0/2] update live migration configuration region Longfang Liu
2025-10-30  1:57 ` [PATCH v12 1/2] crypto: hisilicon - qm updates BAR configuration Longfang Liu
2025-10-30  1:57 ` [PATCH v12 2/2] hisi_acc_vfio_pci: adapt to new migration configuration Longfang Liu
2025-11-05 22:32   ` Alex Williamson [this message]
2025-11-06  2:26     ` liulongfang
2025-11-07  4:34 ` [PATCH v12 0/2] update live migration configuration region Alex Williamson

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