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From: sashiko-bot@kernel.org
To: "Ewan Hai-oc" <ewanhai-oc@zhaoxin.com>
Cc: kvm@vger.kernel.org
Subject: Re: [PATCH v3 1/5] KVM: x86: Expose Zhaoxin SM2 CPUID feature
Date: Wed, 10 Jun 2026 02:43:50 +0000	[thread overview]
Message-ID: <20260610024350.F13471F00893@smtp.kernel.org> (raw)
In-Reply-To: <20260610023512.3690734-2-ewanhai-oc@zhaoxin.com>

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Low] The newly added CPU feature flags `X86_FEATURE_SM2` and `X86_FEATURE_SM2_EN` in `arch/x86/include/asm/cpufeatures.h` are not mirrored to `tools/arch/x86/include/asm/cpufeatures.h`. This discrepancy triggers a 'Kernel ABI header ... differs from latest version' warning from `tools/perf/check-headers.sh` when building kernel tools.
--

commit 9ee6d6c060dd6911df4ff4999acdeb3563ea4667
Author: Ewan Hai-oc <ewanhai-oc@zhaoxin.com>

KVM: x86: Expose Zhaoxin SM2 CPUID feature

This commit advertises Zhaoxin SM2 instruction support to guests via
CPUID 0xC0000001 EDX bits 0 (SM2) and 1 (SM2_EN). It registers the new
capabilities in the KVM CPU caps initialization and the x86 architecture
feature lists.

> diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
> index 1d506e5d6f46a..20b33413189c2 100644
> --- a/arch/x86/include/asm/cpufeatures.h
> +++ b/arch/x86/include/asm/cpufeatures.h
> @@ -136,6 +136,8 @@
>  #define X86_FEATURE_HYPERVISOR		( 4*32+31) /* "hypervisor" Running on a hypervisor */
>  
>  /* VIA/Cyrix/Centaur-defined CPU features, CPUID level 0xC0000001, word 5 */
> +#define X86_FEATURE_SM2			( 5*32+ 0) /* "sm2" SM2 algorithm */
> +#define X86_FEATURE_SM2_EN		( 5*32+ 1) /* "sm2_en" SM2 enabled */

[Severity: Low]
This isn't a bug, but should these new feature flags also be added to
tools/arch/x86/include/asm/cpufeatures.h?

Leaving the tools copy out of sync with the main architecture header
triggers a warning from tools/perf/check-headers.sh indicating that the
Kernel ABI header differs from the latest version when building kernel
tools.

>  #define X86_FEATURE_XSTORE		( 5*32+ 2) /* "rng" RNG present (xstore) */
>  #define X86_FEATURE_XSTORE_EN		( 5*32+ 3) /* "rng_en" RNG enabled */

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260610023512.3690734-1-ewanhai-oc@zhaoxin.com?part=1

  reply	other threads:[~2026-06-10  2:43 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-06-10  2:35 [PATCH v3 0/5] KVM: x86: Expose Zhaoxin CPUID 0xC0000001 EDX cryptographic features Ewan Hai-oc
2026-06-10  2:35 ` [PATCH v3 1/5] KVM: x86: Expose Zhaoxin SM2 CPUID feature Ewan Hai-oc
2026-06-10  2:43   ` sashiko-bot [this message]
2026-06-10  2:35 ` [PATCH v3 2/5] KVM: x86: Expose Zhaoxin CCS (SM3 + SM4) " Ewan Hai-oc
2026-06-10  2:42   ` sashiko-bot
2026-06-10  2:35 ` [PATCH v3 3/5] KVM: x86: Expose Zhaoxin RNG2 " Ewan Hai-oc
2026-06-10  2:44   ` sashiko-bot
2026-06-10  2:35 ` [PATCH v3 4/5] KVM: x86: Expose Zhaoxin PHE2 " Ewan Hai-oc
2026-06-10  2:45   ` sashiko-bot
2026-06-10  2:35 ` [PATCH v3 5/5] KVM: x86: Expose Zhaoxin RSA " Ewan Hai-oc

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