From: sashiko-bot@kernel.org
To: "Inochi Amaoto" <inochiama@gmail.com>
Cc: kvm@vger.kernel.org
Subject: Re: [PATCH v5 1/8] RISC-V: KVM: Add support for Svadu FWFT features
Date: Mon, 06 Jul 2026 02:40:06 +0000 [thread overview]
Message-ID: <20260706024007.CCB2E1F000E9@smtp.kernel.org> (raw)
In-Reply-To: <20260706022046.214956-2-inochiama@gmail.com>
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] Calling ncsr_write() with preemption enabled causes per-CPU memory corruption when NACL is active, and unsafe host CSR modifications.
--
commit 08e867d22007707b3dd632ffff55b12837db2498
Author: Inochi Amaoto <inochiama@gmail.com>
RISC-V: KVM: Add support for Svadu FWFT features
This patch adds support for the Svadu FWFT feature, controlling hardware
updating of PTE A/D bits through the ADUE bit in henvcfg. It allows the
guest and VMM to enable or disable this feature dynamically.
> diff --git a/arch/riscv/kvm/vcpu_sbi_fwft.c b/arch/riscv/kvm/vcpu_sbi_fwft.c
> index ab39ac464ffd8..01db40b532951 100644
> --- a/arch/riscv/kvm/vcpu_sbi_fwft.c
> +++ b/arch/riscv/kvm/vcpu_sbi_fwft.c
[ ... ]
> @@ -94,6 +95,45 @@ static bool kvm_fwft_is_defined_feature(enum sbi_fwft_feature_t feature)
> return false;
> }
>
> +static void kvm_sbi_fwft_env_flag_reset_helper(struct kvm_vcpu *vcpu,
> + u64 flag)
> +{
> + vcpu->arch.cfg.henvcfg &= ~flag;
> +}
> +
> +static long kvm_sbi_fwft_env_flag_set_helper(struct kvm_vcpu *vcpu,
> + struct kvm_sbi_fwft_config *conf,
> + bool one_reg_access,
> + unsigned long value, u64 flag)
> +{
> + struct kvm_vcpu_config *cfg = &vcpu->arch.cfg;
> +
> + if (value == 0)
> + cfg->henvcfg &= ~flag;
> + else if (value == 1)
> + cfg->henvcfg |= flag;
> + else
> + return SBI_ERR_INVALID_PARAM;
> +
> + if (!one_reg_access) {
> + ncsr_write(CSR_HENVCFG, vcpu->arch.cfg.henvcfg);
> + if (IS_ENABLED(CONFIG_32BIT))
> + ncsr_write(CSR_HENVCFGH, vcpu->arch.cfg.henvcfg >> 32);
[Severity: High]
Is it safe to call ncsr_write() here without preemption disabled?
KVM handles SBI ecalls with preemption enabled. The ncsr_write() macro
evaluates nacl_shmem(), which relies on this_cpu_ptr(). Using this_cpu_ptr()
with preemption enabled will trigger a CONFIG_DEBUG_PREEMPT warning.
Could the thread be migrated to another CPU after computing the pointer but
before writing to it, resulting in per-CPU memory corruption by writing to
the NACL shared memory of another physical CPU?
Additionally, when NACL is disabled, it falls back to csr_write(), which
writes directly to the physical CPU's host CSRs (CSR_HENVCFG). Could this
leave the host with modified hardware state if the vCPU thread migrates?
> + }
> +
> + return SBI_SUCCESS;
> +}
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260706022046.214956-1-inochiama@gmail.com?part=1
next prev parent reply other threads:[~2026-07-06 2:40 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-07-06 2:20 [PATCH v5 0/8] RISC-V: KVM: Add Svadu/Zicfiss/Zicfilp FWFT support Inochi Amaoto
2026-07-06 2:20 ` [PATCH v5 1/8] RISC-V: KVM: Add support for Svadu FWFT features Inochi Amaoto
2026-07-06 2:40 ` sashiko-bot [this message]
2026-07-06 2:20 ` [PATCH v5 2/8] KVM: riscv: selftests: add Svadu FWFT extension to get-reg-list test Inochi Amaoto
2026-07-06 2:20 ` [PATCH v5 3/8] RISC-V: KVM: Allow Zicfiss/Zicfilp extensions for Guest/VM Inochi Amaoto
2026-07-06 2:20 ` [PATCH v5 4/8] RISC-V: KVM: Add ssp context save/restore Inochi Amaoto
2026-07-06 2:20 ` [PATCH v5 5/8] RISC-V: KVM: Handle software-check exits for VCPU Inochi Amaoto
2026-07-06 2:20 ` [PATCH v5 6/8] RISC-V: KVM: Delegate SPELP bit to VS/VU mode if landing pad is enabled Inochi Amaoto
2026-07-06 2:20 ` [PATCH v5 7/8] RISC-V: KVM: Add support for control-flow integrity FWFT features Inochi Amaoto
2026-07-06 2:42 ` sashiko-bot
2026-07-06 2:20 ` [PATCH v5 8/8] KVM: riscv: selftests: add Zicfiss/Zicfilp extension to get-reg-list test Inochi Amaoto
2026-07-06 2:39 ` sashiko-bot
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