[PATCH v2 0/5] LoongArch: KVM: Add separate vmid support

[PATCH v2 0/5] LoongArch: KVM: Add separate vmid support

[Bibo Mao]

LoongArch KVM hypervisor supports two-level MMU, vpid index is used
for stage1 MMU and vmid index is used for stage2 MMU.

On 3A5000, vmid must be the same with vpid. On 3A6000 platform vmid
may separate from vpid. There are such advantages if separated vmid
is supported.
  1. One VM uses one vmid, vCPUs on the same VM can share the same vmid.
  2. If one vCPU switch between different physical CPUs, old vmid can be
     still useful if it is not expired.
  3. For remote tlb flush, it is to flush TLBs which are mapping
     GPA --> HPA, only vmid need update and vpid need not.

Here add separate vmid feature support, vmid feature detecting method
comes from CPUCFG8 capability when LVZ is enabled.
---
v1 ... v2:
  1. Move vmid together with vpid in patch1, rename it with hw_vmid.
  2. Rename kvm_check_vcpuid() with __kvm_check_vpid(), and function
     kvm_check_vmid() with __kvm_check_vmid().
  3. Merge part of patch 2, patch 3/4 together.
  4. Use bit8 of CPUCFG8 as guestid capability rather than LVZ version,
     since it is hard to decide whether this feature exists with high LVZ
     version in future.
  5. Set cpu bit with vcpu->kvm->arch.tlb_flush_pending rather than
     using add request KVM_REQ_TLB_FLUSH_GPA, it needs flush TLB on CPU
     where page fault happens and vCPU maybe migrates to other CPUs.
---
Bibo Mao (5):
  LoongArch: KVM: Add vmid support for stage2 MMU
  LoongArch: KVM: Add separate vCPU and VM id update function
  LoongArch: KVM: Add separate vmid feature support
  LoongArch: KVM: Implement vmid updating logic
  LoongArch: KVM: Enable separate vmid feature

 arch/loongarch/include/asm/kvm_host.h  | 10 ++++
 arch/loongarch/include/asm/loongarch.h |  5 ++
 arch/loongarch/kernel/asm-offsets.c    |  1 +
 arch/loongarch/kernel/cpu-probe.c      |  6 +++
 arch/loongarch/kvm/main.c              | 70 ++++++++++++++++++++++++--
 arch/loongarch/kvm/mmu.c               | 23 ++++++++-
 arch/loongarch/kvm/switch.S            |  5 +-
 arch/loongarch/kvm/tlb.c               | 19 ++++++-
 arch/loongarch/kvm/vcpu.c              |  3 +-
 9 files changed, 131 insertions(+), 11 deletions(-)


base-commit: c21bb4193868a8de71fc4693fa741e195fdf5d86
-- 
2.39.3

[PATCH v2 1/5] LoongArch: KVM: Add vmid support for stage2 MMU

[Bibo Mao]

LoongArch KVM hypervisor supports two-level MMU, vpid index is used
for stage1 MMU and vmid index is used for stage2 MMU.

On 3A5000, vmid must be the same with vpid. On 3A6000 platform vmid
may separate from vpid. If vCPU migrate to different physical CPUs,
vpid need change however vmid can keep unchanged, so that TLB entries
for stage2 MMU is valid still. Also vmid index of the whole VM machine
is the same on one physical CPU, all vCPUs on the VM can share the
same vmid index on one physical CPU.

Here hw vmid index is added and it keeps the same with hw vpid still.

Signed-off-by: Bibo Mao <maobibo@loongson.cn>
---
 arch/loongarch/include/asm/kvm_host.h | 3 +++
 arch/loongarch/kernel/asm-offsets.c   | 1 +
 arch/loongarch/kvm/main.c             | 1 +
 arch/loongarch/kvm/switch.S           | 5 ++---
 arch/loongarch/kvm/tlb.c              | 5 ++++-
 5 files changed, 11 insertions(+), 4 deletions(-)

diff --git a/arch/loongarch/include/asm/kvm_host.h b/arch/loongarch/include/asm/kvm_host.h
index 23cfbecebbd7..78f97dea124d 100644
--- a/arch/loongarch/include/asm/kvm_host.h
+++ b/arch/loongarch/include/asm/kvm_host.h
@@ -232,6 +232,9 @@ struct kvm_vcpu_arch {
 	/* Cache for pages needed inside spinlock regions */
 	struct kvm_mmu_memory_cache mmu_page_cache;
 
+	/* hw vmid info for guest VM */
+	unsigned long hw_vmid;
+
 	/* vcpu's vpid */
 	u64 vpid;
 	gpa_t flush_gpa;
diff --git a/arch/loongarch/kernel/asm-offsets.c b/arch/loongarch/kernel/asm-offsets.c
index 1b861cbc5e10..065ced1f3c1f 100644
--- a/arch/loongarch/kernel/asm-offsets.c
+++ b/arch/loongarch/kernel/asm-offsets.c
@@ -300,6 +300,7 @@ static void __used output_kvm_defines(void)
 	OFFSET(KVM_ARCH_HSP, kvm_vcpu_arch, host_sp);
 	OFFSET(KVM_ARCH_HTP, kvm_vcpu_arch, host_tp);
 	OFFSET(KVM_ARCH_HPGD, kvm_vcpu_arch, host_pgd);
+	OFFSET(KVM_ARCH_VMID, kvm_vcpu_arch, hw_vmid);
 	OFFSET(KVM_ARCH_KVMPGD, kvm_vcpu_arch, kvm_pgd);
 	OFFSET(KVM_ARCH_HANDLE_EXIT, kvm_vcpu_arch, handle_exit);
 	OFFSET(KVM_ARCH_HEENTRY, kvm_vcpu_arch, host_eentry);
diff --git a/arch/loongarch/kvm/main.c b/arch/loongarch/kvm/main.c
index 3e1005526f4b..401c84f38e8c 100644
--- a/arch/loongarch/kvm/main.c
+++ b/arch/loongarch/kvm/main.c
@@ -223,6 +223,7 @@ static void kvm_update_vpid(struct kvm_vcpu *vcpu, int cpu)
 
 	context->vpid_cache = vpid;
 	vcpu->arch.vpid = vpid;
+	vcpu->arch.hw_vmid = vcpu->arch.vpid & vpid_mask;
 }
 
 void kvm_check_vpid(struct kvm_vcpu *vcpu)
diff --git a/arch/loongarch/kvm/switch.S b/arch/loongarch/kvm/switch.S
index 936e4ae3e408..af972394fd55 100644
--- a/arch/loongarch/kvm/switch.S
+++ b/arch/loongarch/kvm/switch.S
@@ -66,9 +66,8 @@
 	ld.d	t0, a2, KVM_ARCH_KVMPGD
 	csrwr	t0, LOONGARCH_CSR_PGDL
 
-	/* Mix GID and RID */
-	csrrd		t1, LOONGARCH_CSR_GSTAT
-	bstrpick.w	t1, t1, CSR_GSTAT_GID_SHIFT_END, CSR_GSTAT_GID_SHIFT
+	/* Set VMID for gpa --> hpa mapping */
+	ld.d		t1, a2, KVM_ARCH_VMID
 	csrrd		t0, LOONGARCH_CSR_GTLBC
 	bstrins.w	t0, t1, CSR_GTLBC_TGID_SHIFT_END, CSR_GTLBC_TGID_SHIFT
 	csrwr		t0, LOONGARCH_CSR_GTLBC
diff --git a/arch/loongarch/kvm/tlb.c b/arch/loongarch/kvm/tlb.c
index ebdbe9264e9c..b25847aab968 100644
--- a/arch/loongarch/kvm/tlb.c
+++ b/arch/loongarch/kvm/tlb.c
@@ -23,7 +23,10 @@ void kvm_flush_tlb_all(void)
 
 void kvm_flush_tlb_gpa(struct kvm_vcpu *vcpu, unsigned long gpa)
 {
+	unsigned int vmid;
+
 	lockdep_assert_irqs_disabled();
 	gpa &= (PAGE_MASK << 1);
-	invtlb(INVTLB_GID_ADDR, read_csr_gstat() & CSR_GSTAT_GID, gpa);
+	vmid = (vcpu->arch.hw_vmid << CSR_GSTAT_GID_SHIFT) & CSR_GSTAT_GID;
+	invtlb(INVTLB_GID_ADDR, vmid, gpa);
 }
-- 
2.39.3

[PATCH v2 2/5] LoongArch: KVM: Add separate vCPU and VM id update function

[Bibo Mao]

There are two-level MMU on LoongArch KVM system, the first level (stage1)
MMU is mapping for GVA --> GPA, the second level (stage2) is mapping
for GPA --> HPA. Similar with ASID, there is different ID management
to support multiple VMs and vCPUs. The stage1 MMU is called VPID, and
the second MMU is called VMID, the corresponding ID management function
is __kvm_check_vpid() and __kvm_check_vmid().

Signed-off-by: Bibo Mao <maobibo@loongson.cn>
---
 arch/loongarch/kvm/main.c | 21 ++++++++++++++++++---
 1 file changed, 18 insertions(+), 3 deletions(-)

diff --git a/arch/loongarch/kvm/main.c b/arch/loongarch/kvm/main.c
index 401c84f38e8c..ac804e77e844 100644
--- a/arch/loongarch/kvm/main.c
+++ b/arch/loongarch/kvm/main.c
@@ -223,10 +223,9 @@ static void kvm_update_vpid(struct kvm_vcpu *vcpu, int cpu)
 
 	context->vpid_cache = vpid;
 	vcpu->arch.vpid = vpid;
-	vcpu->arch.hw_vmid = vcpu->arch.vpid & vpid_mask;
 }
 
-void kvm_check_vpid(struct kvm_vcpu *vcpu)
+static void __kvm_check_vpid(struct kvm_vcpu *vcpu)
 {
 	int cpu;
 	bool migrated;
@@ -254,7 +253,6 @@ void kvm_check_vpid(struct kvm_vcpu *vcpu)
 		kvm_update_vpid(vcpu, cpu);
 		trace_kvm_vpid_change(vcpu, vcpu->arch.vpid);
 		vcpu->cpu = cpu;
-		kvm_clear_request(KVM_REQ_TLB_FLUSH_GPA, vcpu);
 
 		/*
 		 * LLBCTL is a separated guest CSR register from host, a general
@@ -280,6 +278,23 @@ void kvm_check_vpid(struct kvm_vcpu *vcpu)
 	}
 }
 
+static void __kvm_check_vmid(struct kvm_vcpu *vcpu)
+{
+	unsigned long vmid;
+
+	vmid = vcpu->arch.vpid & vpid_mask;
+	if (vcpu->arch.hw_vmid != vmid) {
+		vcpu->arch.hw_vmid = vcpu->arch.vpid & vpid_mask;
+		kvm_clear_request(KVM_REQ_TLB_FLUSH_GPA, vcpu);
+	}
+}
+
+void kvm_check_vpid(struct kvm_vcpu *vcpu)
+{
+	__kvm_check_vpid(vcpu);
+	__kvm_check_vmid(vcpu);
+}
+
 void kvm_init_vmcs(struct kvm *kvm)
 {
 	kvm->arch.vmcs = vmcs;
-- 
2.39.3

[PATCH v2 3/5] LoongArch: KVM: Add separate vmid feature support

[Bibo Mao]

Feature cpu_has_guestid is used to check whether separate vmid/vpid
is supported or not. It is disabled by default, add this feature
checking, there is no function change.

Signed-off-by: Bibo Mao <maobibo@loongson.cn>
---
 arch/loongarch/kvm/main.c | 14 +++++++++-----
 arch/loongarch/kvm/mmu.c  |  6 ++++--
 arch/loongarch/kvm/vcpu.c |  3 ++-
 3 files changed, 15 insertions(+), 8 deletions(-)

diff --git a/arch/loongarch/kvm/main.c b/arch/loongarch/kvm/main.c
index ac804e77e844..c36e62ab0d91 100644
--- a/arch/loongarch/kvm/main.c
+++ b/arch/loongarch/kvm/main.c
@@ -218,7 +218,8 @@ static void kvm_update_vpid(struct kvm_vcpu *vcpu, int cpu)
 		++vpid; /* vpid 0 reserved for root */
 
 		/* start new vpid cycle */
-		kvm_flush_tlb_all();
+		if (!cpu_has_guestid)
+			kvm_flush_tlb_all();
 	}
 
 	context->vpid_cache = vpid;
@@ -282,10 +283,13 @@ static void __kvm_check_vmid(struct kvm_vcpu *vcpu)
 {
 	unsigned long vmid;
 
-	vmid = vcpu->arch.vpid & vpid_mask;
-	if (vcpu->arch.hw_vmid != vmid) {
-		vcpu->arch.hw_vmid = vcpu->arch.vpid & vpid_mask;
-		kvm_clear_request(KVM_REQ_TLB_FLUSH_GPA, vcpu);
+	/* On some machines like 3A5000, vmid needs the same with vpid */
+	if (!cpu_has_guestid) {
+		vmid = vcpu->arch.vpid & vpid_mask;
+		if (vcpu->arch.hw_vmid != vmid) {
+			vcpu->arch.hw_vmid = vcpu->arch.vpid & vpid_mask;
+			kvm_clear_request(KVM_REQ_TLB_FLUSH_GPA, vcpu);
+		}
 	}
 }
 
diff --git a/arch/loongarch/kvm/mmu.c b/arch/loongarch/kvm/mmu.c
index e104897aa532..714640a2e614 100644
--- a/arch/loongarch/kvm/mmu.c
+++ b/arch/loongarch/kvm/mmu.c
@@ -929,8 +929,10 @@ int kvm_handle_mm_fault(struct kvm_vcpu *vcpu, unsigned long gpa, bool write, in
 		 *
 		 * With SW PTW, invalid TLB is added in TLB refill exception.
 		 */
-		vcpu->arch.flush_gpa = gpa;
-		kvm_make_request(KVM_REQ_TLB_FLUSH_GPA, vcpu);
+		if (!cpu_has_guestid) {
+			vcpu->arch.flush_gpa = gpa;
+			kvm_make_request(KVM_REQ_TLB_FLUSH_GPA, vcpu);
+		}
 	}
 
 	return 0;
diff --git a/arch/loongarch/kvm/vcpu.c b/arch/loongarch/kvm/vcpu.c
index 20c207d80e31..0b2355aec932 100644
--- a/arch/loongarch/kvm/vcpu.c
+++ b/arch/loongarch/kvm/vcpu.c
@@ -210,7 +210,8 @@ static int kvm_check_requests(struct kvm_vcpu *vcpu)
 		return RESUME_GUEST;
 
 	if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
-		vcpu->arch.vpid = 0;  /* Drop vpid for this vCPU */
+		if (!cpu_has_guestid)
+			vcpu->arch.vpid = 0;  /* Drop vpid for this vCPU */
 
 	if (kvm_dirty_ring_check_request(vcpu))
 		return RESUME_HOST;
-- 
2.39.3

[PATCH v2 4/5] LoongArch: KVM: Implement vmid updating logic

[Bibo Mao]

VMID calculation method is the same with ASID on LoongArch, it is
percpu vmid calculation method. For every physical CPU, VMID of
different VM is different, and it is the same for different vCPUs
of the same VM.

When vCPU is scheduled on the physical CPU, it checked vmid of this
VM and the global cached vmid, and judge whether it is valid or not.

Signed-off-by: Bibo Mao <maobibo@loongson.cn>
---
 arch/loongarch/include/asm/kvm_host.h |  7 +++++
 arch/loongarch/kvm/main.c             | 42 ++++++++++++++++++++++++++-
 arch/loongarch/kvm/mmu.c              | 19 +++++++++++-
 arch/loongarch/kvm/tlb.c              | 14 +++++++++
 4 files changed, 80 insertions(+), 2 deletions(-)

diff --git a/arch/loongarch/include/asm/kvm_host.h b/arch/loongarch/include/asm/kvm_host.h
index 78f97dea124d..e623f781e2a5 100644
--- a/arch/loongarch/include/asm/kvm_host.h
+++ b/arch/loongarch/include/asm/kvm_host.h
@@ -79,6 +79,7 @@ struct kvm_arch_memory_slot {
 #define HOST_MAX_PMNUM			16
 struct kvm_context {
 	unsigned long vpid_cache;
+	unsigned long vmid_cache;
 	struct kvm_vcpu *last_vcpu;
 	/* Host PMU CSR */
 	u64 perf_ctrl[HOST_MAX_PMNUM];
@@ -132,6 +133,8 @@ struct kvm_arch {
 	unsigned long kvm_features;
 
 	s64 time_offset;
+	cpumask_t tlb_flush_pending;
+	unsigned long vmid[NR_CPUS];
 	struct kvm_context __percpu *vmcs;
 	struct loongarch_ipi *ipi;
 	struct loongarch_dmsintc *dmsintc;
@@ -319,6 +322,8 @@ bool kvm_arch_pmi_in_guest(struct kvm_vcpu *vcpu);
 int kvm_arch_vcpu_dump_regs(struct kvm_vcpu *vcpu);
 
 /* MMU handling */
+void kvm_flush_tlb_all_stage1(void);
+void kvm_flush_tlb_all_stage2(void);
 void kvm_flush_tlb_all(void);
 void kvm_flush_tlb_gpa(struct kvm_vcpu *vcpu, unsigned long gpa);
 int kvm_handle_mm_fault(struct kvm_vcpu *vcpu, unsigned long badv, bool write, int ecode);
@@ -353,6 +358,8 @@ static inline void kvm_arch_vcpu_block_finish(struct kvm_vcpu *vcpu) {}
 static inline void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *slot) {}
 void kvm_check_vpid(struct kvm_vcpu *vcpu);
 enum hrtimer_restart kvm_swtimer_wakeup(struct hrtimer *timer);
+#define __KVM_HAVE_ARCH_FLUSH_REMOTE_TLBS
+int kvm_arch_flush_remote_tlbs(struct kvm *kvm);
 void kvm_arch_flush_remote_tlbs_memslot(struct kvm *kvm, const struct kvm_memory_slot *memslot);
 void kvm_init_vmcs(struct kvm *kvm);
 void kvm_exc_entry(void);
diff --git a/arch/loongarch/kvm/main.c b/arch/loongarch/kvm/main.c
index c36e62ab0d91..72c1d23156e5 100644
--- a/arch/loongarch/kvm/main.c
+++ b/arch/loongarch/kvm/main.c
@@ -220,6 +220,8 @@ static void kvm_update_vpid(struct kvm_vcpu *vcpu, int cpu)
 		/* start new vpid cycle */
 		if (!cpu_has_guestid)
 			kvm_flush_tlb_all();
+		else
+			kvm_flush_tlb_all_stage1();
 	}
 
 	context->vpid_cache = vpid;
@@ -279,9 +281,32 @@ static void __kvm_check_vpid(struct kvm_vcpu *vcpu)
 	}
 }
 
-static void __kvm_check_vmid(struct kvm_vcpu *vcpu)
+static void kvm_update_vmid(struct kvm_vcpu *vcpu, int cpu)
 {
 	unsigned long vmid;
+	struct kvm_context *context;
+
+	context = per_cpu_ptr(vcpu->kvm->arch.vmcs, cpu);
+	vmid = context->vmid_cache + 1;
+	if (!(vmid & vpid_mask)) {
+		/* finish round of vmid loop */
+		if (unlikely(!vmid))
+			vmid = vpid_mask + 1;
+
+		++vmid; /* vmid 0 reserved for root */
+
+		/* start new vmid cycle */
+		kvm_flush_tlb_all_stage2();
+	}
+
+	context->vmid_cache = vmid;
+	vcpu->kvm->arch.vmid[cpu] = vmid;
+}
+
+static void __kvm_check_vmid(struct kvm_vcpu *vcpu)
+{
+	int cpu;
+	unsigned long ver, old, vmid;
 
 	/* On some machines like 3A5000, vmid needs the same with vpid */
 	if (!cpu_has_guestid) {
@@ -291,6 +316,20 @@ static void __kvm_check_vmid(struct kvm_vcpu *vcpu)
 			kvm_clear_request(KVM_REQ_TLB_FLUSH_GPA, vcpu);
 		}
 	}
+
+	cpu = smp_processor_id();
+	if (cpumask_test_and_clear_cpu(cpu, &vcpu->kvm->arch.tlb_flush_pending))
+		vcpu->kvm->arch.vmid[cpu] = 0;
+
+	/*
+	 * Check if our vmid is of an older version
+	 */
+	ver = vcpu->kvm->arch.vmid[cpu] & ~vpid_mask;
+	old = this_cpu_ptr(vcpu->kvm->arch.vmcs)->vmid_cache & ~vpid_mask;
+	if (ver != old)
+		kvm_update_vmid(vcpu, cpu);
+
+	vcpu->arch.hw_vmid = vcpu->kvm->arch.vmid[cpu] & vpid_mask;
 }
 
 void kvm_check_vpid(struct kvm_vcpu *vcpu)
@@ -396,6 +435,7 @@ static int kvm_loongarch_env_init(void)
 	for_each_possible_cpu(cpu) {
 		context = per_cpu_ptr(vmcs, cpu);
 		context->vpid_cache = vpid_mask + 1;
+		context->vmid_cache = vpid_mask + 1;
 		context->last_vcpu = NULL;
 	}
 
diff --git a/arch/loongarch/kvm/mmu.c b/arch/loongarch/kvm/mmu.c
index 714640a2e614..80e7a8bdc344 100644
--- a/arch/loongarch/kvm/mmu.c
+++ b/arch/loongarch/kvm/mmu.c
@@ -932,7 +932,8 @@ int kvm_handle_mm_fault(struct kvm_vcpu *vcpu, unsigned long gpa, bool write, in
 		if (!cpu_has_guestid) {
 			vcpu->arch.flush_gpa = gpa;
 			kvm_make_request(KVM_REQ_TLB_FLUSH_GPA, vcpu);
-		}
+		} else
+			cpumask_set_cpu(vcpu->cpu, &vcpu->kvm->arch.tlb_flush_pending);
 	}
 
 	return 0;
@@ -942,6 +943,22 @@ void kvm_arch_sync_dirty_log(struct kvm *kvm, struct kvm_memory_slot *memslot)
 {
 }
 
+int kvm_arch_flush_remote_tlbs(struct kvm *kvm)
+{
+	/*
+	 * Queue a TLB invalidation for each CPU to perform on next
+	 * vcpu loading
+	 */
+	if (cpu_has_guestid) {
+		cpumask_setall(&kvm->arch.tlb_flush_pending);
+		/* Be sure that other CPUS can watch the changes */
+		smp_wmb();
+	}
+
+	/* Return 1 continue to send ipi to running vCPUs */
+	return 1;
+}
+
 void kvm_arch_flush_remote_tlbs_memslot(struct kvm *kvm,
 					const struct kvm_memory_slot *memslot)
 {
diff --git a/arch/loongarch/kvm/tlb.c b/arch/loongarch/kvm/tlb.c
index b25847aab968..a573db026e01 100644
--- a/arch/loongarch/kvm/tlb.c
+++ b/arch/loongarch/kvm/tlb.c
@@ -21,6 +21,20 @@ void kvm_flush_tlb_all(void)
 	local_irq_restore(flags);
 }
 
+/* Invalidate all stage1 TLB entries including GVA-->GPA mappings */
+void kvm_flush_tlb_all_stage1(void)
+{
+	lockdep_assert_irqs_disabled();
+	invtlb_all(INVGTLB_ALLGID_GVA_TO_GPA, 0, 0);
+}
+
+/* Invalidate all stage2 TLB entries including GPA-->HPA  mappings */
+void kvm_flush_tlb_all_stage2(void)
+{
+	lockdep_assert_irqs_disabled();
+	invtlb_all(INVTLB_ALLGID_GPA_TO_HPA, 0, 0);
+}
+
 void kvm_flush_tlb_gpa(struct kvm_vcpu *vcpu, unsigned long gpa)
 {
 	unsigned int vmid;
-- 
2.39.3

[PATCH v2 5/5] LoongArch: KVM: Enable separate vmid feature

[Bibo Mao]

With CSR GTLBC shortname for Guest TLB Control Register, separate vmid
feature will be enabled if bit 14 CSR_GTLBC_USEVMID is set. Enable
this feature if cpu_has_guestid is true when LVZ is enabled and the LVZ
version is 2.

Signed-off-by: Bibo Mao <maobibo@loongson.cn>
---
 arch/loongarch/include/asm/loongarch.h | 5 +++++
 arch/loongarch/kernel/cpu-probe.c      | 6 ++++++
 arch/loongarch/kvm/main.c              | 4 +++-
 3 files changed, 14 insertions(+), 1 deletion(-)

diff --git a/arch/loongarch/include/asm/loongarch.h b/arch/loongarch/include/asm/loongarch.h
index 2a6bc99177d8..a20fb68d8ac4 100644
--- a/arch/loongarch/include/asm/loongarch.h
+++ b/arch/loongarch/include/asm/loongarch.h
@@ -138,6 +138,9 @@
 #define  CPUCFG6_PMBITS_SHIFT		8
 #define  CPUCFG6_UPM			BIT(14)
 
+#define LOONGARCH_CPUCFG8		0x8
+#define  CPUCFG8_VMID			BIT(8)
+
 #define LOONGARCH_CPUCFG16		0x10
 #define  CPUCFG16_L1_IUPRE		BIT(0)
 #define  CPUCFG16_L1_IUUNIFY		BIT(1)
@@ -350,6 +353,8 @@
 #define  CSR_GTLBC_TGID_WIDTH		8
 #define  CSR_GTLBC_TGID_SHIFT_END	(CSR_GTLBC_TGID_SHIFT + CSR_GTLBC_TGID_WIDTH - 1)
 #define  CSR_GTLBC_TGID			(_ULCAST_(0xff) << CSR_GTLBC_TGID_SHIFT)
+#define  CSR_GTLBC_USEVMID_SHIFT	14
+#define  CSR_GTLBC_USEVMID		(_ULCAST_(0x1) << CSR_GTLBC_USEVMID_SHIFT)
 #define  CSR_GTLBC_TOTI_SHIFT		13
 #define  CSR_GTLBC_TOTI			(_ULCAST_(0x1) << CSR_GTLBC_TOTI_SHIFT)
 #define  CSR_GTLBC_USETGID_SHIFT	12
diff --git a/arch/loongarch/kernel/cpu-probe.c b/arch/loongarch/kernel/cpu-probe.c
index 74d31f260dfd..fc68f695d49c 100644
--- a/arch/loongarch/kernel/cpu-probe.c
+++ b/arch/loongarch/kernel/cpu-probe.c
@@ -241,6 +241,12 @@ static void cpu_probe_common(struct cpuinfo_loongarch *c)
 	if (config & CPUCFG6_PMP)
 		c->options |= LOONGARCH_CPU_PMP;
 
+	if (c->options & LOONGARCH_CPU_LVZ) {
+		config = read_cpucfg(LOONGARCH_CPUCFG8);
+		if (config & CPUCFG8_VMID)
+			c->options |= LOONGARCH_CPU_GUESTID;
+	}
+
 	config = csr_read32(LOONGARCH_CSR_ASID);
 	config = (config & CSR_ASID_BIT) >> CSR_ASID_BIT_SHIFT;
 	asid_mask = GENMASK(config - 1, 0);
diff --git a/arch/loongarch/kvm/main.c b/arch/loongarch/kvm/main.c
index 72c1d23156e5..712b078db0d5 100644
--- a/arch/loongarch/kvm/main.c
+++ b/arch/loongarch/kvm/main.c
@@ -359,7 +359,7 @@ int kvm_arch_enable_virtualization_cpu(void)
 	write_csr_gcfg(0);
 	write_csr_gstat(0);
 	write_csr_gintc(0);
-	clear_csr_gtlbc(CSR_GTLBC_USETGID | CSR_GTLBC_TOTI);
+	clear_csr_gtlbc(CSR_GTLBC_USETGID | CSR_GTLBC_TOTI | CSR_GTLBC_USEVMID);
 
 	/*
 	 * Enable virtualization features granting guest direct control of
@@ -382,6 +382,8 @@ int kvm_arch_enable_virtualization_cpu(void)
 
 	/* Enable using TGID  */
 	set_csr_gtlbc(CSR_GTLBC_USETGID);
+	if (cpu_has_guestid)
+		set_csr_gtlbc(CSR_GTLBC_USEVMID);
 	kvm_debug("GCFG:%lx GSTAT:%lx GINTC:%lx GTLBC:%lx",
 		  read_csr_gcfg(), read_csr_gstat(), read_csr_gintc(), read_csr_gtlbc());
 
-- 
2.39.3

Re: [PATCH v2 4/5] LoongArch: KVM: Implement vmid updating logic

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 3 potential issue(s) to consider:
- [High] Missing early return in `__kvm_check_vmid` for machines without guest ID support breaks VMID/VPID synchronization.
- [Medium] Data race between non-atomic `cpumask_setall()` and atomic bitwise operations on `tlb_flush_pending`.
- [Low] Dead code: `kvm_arch_flush_remote_tlbs_memslot` is a fictitious arch hook not called by KVM core.
--

--- Patch [4]: [PATCH v2 4/5] LoongArch: KVM: Implement vmid updating logic ---
commit 1626f2256d93ca3c5c607a6a950ca7531c03169a
Author: Bibo Mao <maobibo@loongson.cn>
Date:   Thu Aug 6 02:07:38 2026 +0000

    LoongArch: KVM: Implement vmid updating logic
    
    VMID calculation method is the same with ASID on LoongArch, it is
    percpu vmid calculation method. For every physical CPU, VMID of
    different VM is different, and it is the same for different vCPUs
    of the same VM.

> diff --git a/arch/loongarch/kvm/main.c b/arch/loongarch/kvm/main.c
> index c36e62ab0d917..72c1d23156e50 100644
> --- a/arch/loongarch/kvm/main.c
> +++ b/arch/loongarch/kvm/main.c
[ ... ]
> @@ -291,6 +316,20 @@ static void __kvm_check_vmid(struct kvm_vcpu *vcpu)
>  			kvm_clear_request(KVM_REQ_TLB_FLUSH_GPA, vcpu);
>  		}
>  	}
> +
> +	cpu = smp_processor_id();
> +	if (cpumask_test_and_clear_cpu(cpu, &vcpu->kvm->arch.tlb_flush_pending))
> +		vcpu->kvm->arch.vmid[cpu] = 0;
> +
> +	/*
> +	 * Check if our vmid is of an older version
> +	 */
> +	ver = vcpu->kvm->arch.vmid[cpu] & ~vpid_mask;
> +	old = this_cpu_ptr(vcpu->kvm->arch.vmcs)->vmid_cache & ~vpid_mask;
> +	if (ver != old)
> +		kvm_update_vmid(vcpu, cpu);
> +
> +	vcpu->arch.hw_vmid = vcpu->kvm->arch.vmid[cpu] & vpid_mask;

[Severity: High]
Does this unconditionally overwrite vcpu->arch.hw_vmid for machines without
guest ID support? On machines like 3A5000, hw_vmid is set to match vpid
above, but without an early return or else block, it falls through and gets
overwritten here with a dynamically allocated vmid.

>  }
>  
>  void kvm_check_vpid(struct kvm_vcpu *vcpu)
> diff --git a/arch/loongarch/kvm/mmu.c b/arch/loongarch/kvm/mmu.c
> index 714640a2e6142..80e7a8bdc344a 100644
> --- a/arch/loongarch/kvm/mmu.c
> +++ b/arch/loongarch/kvm/mmu.c
[ ... ]
> @@ -942,6 +943,22 @@ void kvm_arch_sync_dirty_log(struct kvm *kvm, struct kvm_memory_slot *memslot)
>  {
>  }
>  
> +int kvm_arch_flush_remote_tlbs(struct kvm *kvm)
> +{
> +	/*
> +	 * Queue a TLB invalidation for each CPU to perform on next
> +	 * vcpu loading
> +	 */
> +	if (cpu_has_guestid) {
> +		cpumask_setall(&kvm->arch.tlb_flush_pending);

[Severity: Medium]
Could calling cpumask_setall() cause a data race with concurrent atomic
bit operations? 

cpumask_setall() uses a non-atomic memset() internally, while
__kvm_check_vmid() and kvm_handle_mm_fault() use atomic read-modify-write
operations like cpumask_test_and_clear_cpu() and cpumask_set_cpu() on the
same cpumask.

> +		/* Be sure that other CPUS can watch the changes */
> +		smp_wmb();
> +	}
> +
> +	/* Return 1 continue to send ipi to running vCPUs */
> +	return 1;
> +}
> +
> +void kvm_arch_flush_remote_tlbs_memslot(struct kvm *kvm,
> +					const struct kvm_memory_slot *memslot)
> +{
> +	kvm_flush_remote_tlbs(kvm);
> +}

[Severity: Low]
Is kvm_arch_flush_remote_tlbs_memslot() dead code? There does not appear to be
a KVM core hook by this name, so this architecture-specific function won't be
called by the KVM core during memslot updates.

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260806020739.2149268-1-maobibo@loongson.cn?part=4

Re: [PATCH v2 3/5] LoongArch: KVM: Add separate vmid feature support

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Critical] The patch introduces `if (!cpu_has_guestid)` feature gates to bypass existing VPID and TLB flush mechanisms, but completely omits the alternative logic for when the feature is enabled, introducing severe latent vulnerabilities (broken VM isolation, skipped TLB flushes).
--

--- Patch [3]: [PATCH v2 3/5] LoongArch: KVM: Add separate vmid feature support ---
commit 6bfee108dace797d9e6015bf026032adaef591e9
Author: Bibo Mao <maobibo@loongson.cn>

LoongArch: KVM: Add separate vmid feature support

Feature cpu_has_guestid is used to check whether separate vmid/vpid
is supported or not. It is disabled by default, add this feature
checking, there is no function change.

> diff --git a/arch/loongarch/kvm/main.c b/arch/loongarch/kvm/main.c
> index ac804e77e844f..c36e62ab0d917 100644
> --- a/arch/loongarch/kvm/main.c
> +++ b/arch/loongarch/kvm/main.c
> @@ -218,7 +218,8 @@ static void kvm_update_vpid(struct kvm_vcpu *vcpu, int cpu)
>  		++vpid; /* vpid 0 reserved for root */
>  
>  		/* start new vpid cycle */
> -		kvm_flush_tlb_all();
> +		if (!cpu_has_guestid)
> +			kvm_flush_tlb_all();

[Severity: Critical]
If cpu_has_guestid is true, this skips the global TLB flush on VPID
wrap-around. Is there an alternative flush mechanism that should be
implemented here when the feature is enabled?

>  	}
>  
>  	context->vpid_cache = vpid;
> @@ -282,10 +283,13 @@ static void __kvm_check_vmid(struct kvm_vcpu *vcpu)
>  {
>  	unsigned long vmid;
>  
> -	vmid = vcpu->arch.vpid & vpid_mask;
> -	if (vcpu->arch.hw_vmid != vmid) {
> -		vcpu->arch.hw_vmid = vcpu->arch.vpid & vpid_mask;
> -		kvm_clear_request(KVM_REQ_TLB_FLUSH_GPA, vcpu);
> +	/* On some machines like 3A5000, vmid needs the same with vpid */
> +	if (!cpu_has_guestid) {
> +		vmid = vcpu->arch.vpid & vpid_mask;
> +		if (vcpu->arch.hw_vmid != vmid) {
> +			vcpu->arch.hw_vmid = vcpu->arch.vpid & vpid_mask;
> +			kvm_clear_request(KVM_REQ_TLB_FLUSH_GPA, vcpu);
> +		}
>  	}
>  }

[Severity: Critical]
When cpu_has_guestid is true, the hw_vmid update is skipped entirely without
alternative logic, leaving hw_vmid uninitialized (0).

When kvm_switch_to_guest() in arch/loongarch/kvm/switch.S loads hw_vmid into
the hardware Guest ID register (LOONGARCH_CSR_GTLBC), will all VMs share
VMID 0, breaking stage-2 VM isolation?

> diff --git a/arch/loongarch/kvm/mmu.c b/arch/loongarch/kvm/mmu.c
> index e104897aa5328..714640a2e6142 100644
> --- a/arch/loongarch/kvm/mmu.c
> +++ b/arch/loongarch/kvm/mmu.c
> @@ -929,8 +929,10 @@ int kvm_handle_mm_fault(struct kvm_vcpu *vcpu, unsigned long gpa, bool write, in
>  		 *
>  		 * With SW PTW, invalid TLB is added in TLB refill exception.
>  		 */
> -		vcpu->arch.flush_gpa = gpa;
> -		kvm_make_request(KVM_REQ_TLB_FLUSH_GPA, vcpu);
> +		if (!cpu_has_guestid) {
> +			vcpu->arch.flush_gpa = gpa;
> +			kvm_make_request(KVM_REQ_TLB_FLUSH_GPA, vcpu);
> +		}
>  	}
>  
>  	return 0;

[Severity: Critical]
Are we missing a TLB flush request for stale translation entries when
cpu_has_guestid is enabled?

> diff --git a/arch/loongarch/kvm/vcpu.c b/arch/loongarch/kvm/vcpu.c
> index 20c207d80e31a..0b2355aec9322 100644
> --- a/arch/loongarch/kvm/vcpu.c
> +++ b/arch/loongarch/kvm/vcpu.c
> @@ -210,7 +210,8 @@ static int kvm_check_requests(struct kvm_vcpu *vcpu)
>  		return RESUME_GUEST;
>  
>  	if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
> -		vcpu->arch.vpid = 0;  /* Drop vpid for this vCPU */
> +		if (!cpu_has_guestid)
> +			vcpu->arch.vpid = 0;  /* Drop vpid for this vCPU */
>  
>  	if (kvm_dirty_ring_check_request(vcpu))
>  		return RESUME_HOST;

[Severity: Critical]
This consumes the KVM_REQ_TLB_FLUSH request but skips dropping the VPID when
cpu_has_guestid is true. Could this effectively swallow the request without
performing the actual flush logic?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260806020739.2149268-1-maobibo@loongson.cn?part=3

Re: [PATCH v2 5/5] LoongArch: KVM: Enable separate vmid feature

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] The `CSR_GTLBC_USEVMID` bit is not cleared when virtualization is disabled, leaking guest TLB hardware state into the host execution environment.
--

--- Patch [5]: [PATCH v2 5/5] LoongArch: KVM: Enable separate vmid feature ---
commit 3bea8b9a7dbd607efeb389e6233ef3a1a4c29bf9
Author: Bibo Mao <maobibo@loongson.cn>

LoongArch: KVM: Enable separate vmid feature

This commit enables the separate VMID feature on LoongArch KVM if
cpu_has_guestid is true when LVZ is enabled and the LVZ version is 2.
It updates cpu-probe to set LOONGARCH_CPU_GUESTID and modifies
kvm_arch_enable_virtualization_cpu() to configure the new bit.

[ ... ]

> diff --git a/arch/loongarch/kvm/main.c b/arch/loongarch/kvm/main.c
> index 72c1d23156e50..712b078db0d54 100644
> --- a/arch/loongarch/kvm/main.c
> +++ b/arch/loongarch/kvm/main.c
> @@ -359,7 +359,7 @@ int kvm_arch_enable_virtualization_cpu(void)
>  	write_csr_gcfg(0);
>  	write_csr_gstat(0);
>  	write_csr_gintc(0);
> -	clear_csr_gtlbc(CSR_GTLBC_USETGID | CSR_GTLBC_TOTI);
> +	clear_csr_gtlbc(CSR_GTLBC_USETGID | CSR_GTLBC_TOTI | CSR_GTLBC_USEVMID);

[Severity: Medium]
Should CSR_GTLBC_USEVMID also be cleared when virtualization is disabled?

When KVM is unloaded or a CPU is brought offline, the hardware virtualization
state is supposed to be fully restored. While this patch updates
kvm_arch_enable_virtualization_cpu() to clear CSR_GTLBC_USEVMID during
initialization, the corresponding disable function seems to miss it:

arch/loongarch/kvm/main.c:kvm_arch_disable_virtualization_cpu() {
	write_csr_gcfg(0);
	write_csr_gstat(0);
	write_csr_gintc(0);
	clear_csr_gtlbc(CSR_GTLBC_USETGID | CSR_GTLBC_TOTI);
	...
}

Does this cause the USEVMID configuration to leak into the host execution
environment?

Although the host operates in root mode (VMID 0), leaving hypervisor
hardware features enabled could potentially interfere with kexec or
secondary hypervisor setups.

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260806020739.2149268-1-maobibo@loongson.cn?part=5

Re: [PATCH v2 4/5] LoongArch: KVM: Implement vmid updating logic

[Bibo Mao]

On 2026/8/6 上午10:30, sashiko-bot@kernel.org wrote:
> Thank you for your contribution! Sashiko AI review found 3 potential issue(s) to consider:
> - [High] Missing early return in `__kvm_check_vmid` for machines without guest ID support breaks VMID/VPID synchronization.
> - [Medium] Data race between non-atomic `cpumask_setall()` and atomic bitwise operations on `tlb_flush_pending`.
> - [Low] Dead code: `kvm_arch_flush_remote_tlbs_memslot` is a fictitious arch hook not called by KVM core.
> --
> 
> --- Patch [4]: [PATCH v2 4/5] LoongArch: KVM: Implement vmid updating logic ---
> commit 1626f2256d93ca3c5c607a6a950ca7531c03169a
> Author: Bibo Mao <maobibo@loongson.cn>
> Date:   Thu Aug 6 02:07:38 2026 +0000
> 
>      LoongArch: KVM: Implement vmid updating logic
>      
>      VMID calculation method is the same with ASID on LoongArch, it is
>      percpu vmid calculation method. For every physical CPU, VMID of
>      different VM is different, and it is the same for different vCPUs
>      of the same VM.
> 
>> diff --git a/arch/loongarch/kvm/main.c b/arch/loongarch/kvm/main.c
>> index c36e62ab0d917..72c1d23156e50 100644
>> --- a/arch/loongarch/kvm/main.c
>> +++ b/arch/loongarch/kvm/main.c
> [ ... ]
>> @@ -291,6 +316,20 @@ static void __kvm_check_vmid(struct kvm_vcpu *vcpu)
>>   			kvm_clear_request(KVM_REQ_TLB_FLUSH_GPA, vcpu);
>>   		}
>>   	}
>> +
>> +	cpu = smp_processor_id();
>> +	if (cpumask_test_and_clear_cpu(cpu, &vcpu->kvm->arch.tlb_flush_pending))
>> +		vcpu->kvm->arch.vmid[cpu] = 0;
>> +
>> +	/*
>> +	 * Check if our vmid is of an older version
>> +	 */
>> +	ver = vcpu->kvm->arch.vmid[cpu] & ~vpid_mask;
>> +	old = this_cpu_ptr(vcpu->kvm->arch.vmcs)->vmid_cache & ~vpid_mask;
>> +	if (ver != old)
>> +		kvm_update_vmid(vcpu, cpu);
>> +
>> +	vcpu->arch.hw_vmid = vcpu->kvm->arch.vmid[cpu] & vpid_mask;
> 
> [Severity: High]
> Does this unconditionally overwrite vcpu->arch.hw_vmid for machines without
> guest ID support? On machines like 3A5000, hw_vmid is set to match vpid
> above, but without an early return or else block, it falls through and gets
> overwritten here with a dynamically allocated vmid.
yes, early return is missing in if (!cpu_has_guestid) sentence.
--- a/arch/loongarch/kvm/main.c
+++ b/arch/loongarch/kvm/main.c
@@ -315,6 +315,7 @@ static void __kvm_check_vmid(struct kvm_vcpu *vcpu)
                         vcpu->arch.hw_vmid = vcpu->arch.vpid & vpid_mask;
                         kvm_clear_request(KVM_REQ_TLB_FLUSH_GPA, vcpu);
                 }
+               return;
         }
> 
>>   }
>>   
>>   void kvm_check_vpid(struct kvm_vcpu *vcpu)
>> diff --git a/arch/loongarch/kvm/mmu.c b/arch/loongarch/kvm/mmu.c
>> index 714640a2e6142..80e7a8bdc344a 100644
>> --- a/arch/loongarch/kvm/mmu.c
>> +++ b/arch/loongarch/kvm/mmu.c
> [ ... ]
>> @@ -942,6 +943,22 @@ void kvm_arch_sync_dirty_log(struct kvm *kvm, struct kvm_memory_slot *memslot)
>>   {
>>   }
>>   
>> +int kvm_arch_flush_remote_tlbs(struct kvm *kvm)
>> +{
>> +	/*
>> +	 * Queue a TLB invalidation for each CPU to perform on next
>> +	 * vcpu loading
>> +	 */
>> +	if (cpu_has_guestid) {
>> +		cpumask_setall(&kvm->arch.tlb_flush_pending);
> 
> [Severity: Medium]
> Could calling cpumask_setall() cause a data race with concurrent atomic
> bit operations?
> 
> cpumask_setall() uses a non-atomic memset() internally, while
> __kvm_check_vmid() and kvm_handle_mm_fault() use atomic read-modify-write
> operations like cpumask_test_and_clear_cpu() and cpumask_set_cpu() on the
> same cpumask.
This is under investigation, if data of memset() is not lost or 
invalidated, it will send IPI to destination vCPU and check the flag again.

Regards
Bibo Mao
> 
>> +		/* Be sure that other CPUS can watch the changes */
>> +		smp_wmb();
>> +	}
>> +
>> +	/* Return 1 continue to send ipi to running vCPUs */
>> +	return 1;
>> +}
>> +
>> +void kvm_arch_flush_remote_tlbs_memslot(struct kvm *kvm,
>> +					const struct kvm_memory_slot *memslot)
>> +{
>> +	kvm_flush_remote_tlbs(kvm);
>> +}
> 
> [Severity: Low]
> Is kvm_arch_flush_remote_tlbs_memslot() dead code? There does not appear to be
> a KVM core hook by this name, so this architecture-specific function won't be
> called by the KVM core during memslot updates.
> 

Re: [PATCH v2 1/5] LoongArch: KVM: Add vmid support for stage2 MMU

[Huacai Chen]

Hi, Bibo,

On Thu, Aug 6, 2026 at 10:14 AM Bibo Mao <maobibo@loongson.cn> wrote:
>
> LoongArch KVM hypervisor supports two-level MMU, vpid index is used
> for stage1 MMU and vmid index is used for stage2 MMU.
>
> On 3A5000, vmid must be the same with vpid. On 3A6000 platform vmid
> may separate from vpid. If vCPU migrate to different physical CPUs,
> vpid need change however vmid can keep unchanged, so that TLB entries
> for stage2 MMU is valid still. Also vmid index of the whole VM machine
> is the same on one physical CPU, all vCPUs on the VM can share the
> same vmid index on one physical CPU.
>
> Here hw vmid index is added and it keeps the same with hw vpid still.
HW VPID means GSTAT.GID, HW VMID means GTLBC.TGID, right? It is useful
to describe it in the commit message.


>
> Signed-off-by: Bibo Mao <maobibo@loongson.cn>
> ---
>  arch/loongarch/include/asm/kvm_host.h | 3 +++
>  arch/loongarch/kernel/asm-offsets.c   | 1 +
>  arch/loongarch/kvm/main.c             | 1 +
>  arch/loongarch/kvm/switch.S           | 5 ++---
>  arch/loongarch/kvm/tlb.c              | 5 ++++-
>  5 files changed, 11 insertions(+), 4 deletions(-)
>
> diff --git a/arch/loongarch/include/asm/kvm_host.h b/arch/loongarch/include/asm/kvm_host.h
> index 23cfbecebbd7..78f97dea124d 100644
> --- a/arch/loongarch/include/asm/kvm_host.h
> +++ b/arch/loongarch/include/asm/kvm_host.h
> @@ -232,6 +232,9 @@ struct kvm_vcpu_arch {
>         /* Cache for pages needed inside spinlock regions */
>         struct kvm_mmu_memory_cache mmu_page_cache;
>
> +       /* hw vmid info for guest VM */
> +       unsigned long hw_vmid;
Since this is only used to write GCNTC.TGID, simply rename it to tgid
can eliminate confusion.

> +
>         /* vcpu's vpid */
>         u64 vpid;
>         gpa_t flush_gpa;
> diff --git a/arch/loongarch/kernel/asm-offsets.c b/arch/loongarch/kernel/asm-offsets.c
> index 1b861cbc5e10..065ced1f3c1f 100644
> --- a/arch/loongarch/kernel/asm-offsets.c
> +++ b/arch/loongarch/kernel/asm-offsets.c
> @@ -300,6 +300,7 @@ static void __used output_kvm_defines(void)
>         OFFSET(KVM_ARCH_HSP, kvm_vcpu_arch, host_sp);
>         OFFSET(KVM_ARCH_HTP, kvm_vcpu_arch, host_tp);
>         OFFSET(KVM_ARCH_HPGD, kvm_vcpu_arch, host_pgd);
> +       OFFSET(KVM_ARCH_VMID, kvm_vcpu_arch, hw_vmid);
>         OFFSET(KVM_ARCH_KVMPGD, kvm_vcpu_arch, kvm_pgd);
>         OFFSET(KVM_ARCH_HANDLE_EXIT, kvm_vcpu_arch, handle_exit);
>         OFFSET(KVM_ARCH_HEENTRY, kvm_vcpu_arch, host_eentry);
> diff --git a/arch/loongarch/kvm/main.c b/arch/loongarch/kvm/main.c
> index 3e1005526f4b..401c84f38e8c 100644
> --- a/arch/loongarch/kvm/main.c
> +++ b/arch/loongarch/kvm/main.c
> @@ -223,6 +223,7 @@ static void kvm_update_vpid(struct kvm_vcpu *vcpu, int cpu)
>
>         context->vpid_cache = vpid;
>         vcpu->arch.vpid = vpid;
> +       vcpu->arch.hw_vmid = vcpu->arch.vpid & vpid_mask;
Merge Patch#1 and Patch#2, then we can avoid adding this line and then
remove it immediately.


>  }
>
>  void kvm_check_vpid(struct kvm_vcpu *vcpu)
> diff --git a/arch/loongarch/kvm/switch.S b/arch/loongarch/kvm/switch.S
> index 936e4ae3e408..af972394fd55 100644
> --- a/arch/loongarch/kvm/switch.S
> +++ b/arch/loongarch/kvm/switch.S
> @@ -66,9 +66,8 @@
>         ld.d    t0, a2, KVM_ARCH_KVMPGD
>         csrwr   t0, LOONGARCH_CSR_PGDL
>
> -       /* Mix GID and RID */
> -       csrrd           t1, LOONGARCH_CSR_GSTAT
> -       bstrpick.w      t1, t1, CSR_GSTAT_GID_SHIFT_END, CSR_GSTAT_GID_SHIFT
> +       /* Set VMID for gpa --> hpa mapping */
> +       ld.d            t1, a2, KVM_ARCH_VMID
>         csrrd           t0, LOONGARCH_CSR_GTLBC
>         bstrins.w       t0, t1, CSR_GTLBC_TGID_SHIFT_END, CSR_GTLBC_TGID_SHIFT
>         csrwr           t0, LOONGARCH_CSR_GTLBC
> diff --git a/arch/loongarch/kvm/tlb.c b/arch/loongarch/kvm/tlb.c
> index ebdbe9264e9c..b25847aab968 100644
> --- a/arch/loongarch/kvm/tlb.c
> +++ b/arch/loongarch/kvm/tlb.c
> @@ -23,7 +23,10 @@ void kvm_flush_tlb_all(void)
>
>  void kvm_flush_tlb_gpa(struct kvm_vcpu *vcpu, unsigned long gpa)
>  {
> +       unsigned int vmid;
> +
>         lockdep_assert_irqs_disabled();
>         gpa &= (PAGE_MASK << 1);
> -       invtlb(INVTLB_GID_ADDR, read_csr_gstat() & CSR_GSTAT_GID, gpa);
> +       vmid = (vcpu->arch.hw_vmid << CSR_GSTAT_GID_SHIFT) & CSR_GSTAT_GID;
> +       invtlb(INVTLB_GID_ADDR, vmid, gpa);
>  }
> --
> 2.39.3
>

Re: [PATCH v2 3/5] LoongArch: KVM: Add separate vmid feature support

[Huacai Chen]

Hi, Bibo,

On Thu, Aug 6, 2026 at 10:15 AM Bibo Mao <maobibo@loongson.cn> wrote:
>
> Feature cpu_has_guestid is used to check whether separate vmid/vpid
> is supported or not. It is disabled by default, add this feature
> checking, there is no function change.
>
> Signed-off-by: Bibo Mao <maobibo@loongson.cn>
> ---
>  arch/loongarch/kvm/main.c | 14 +++++++++-----
>  arch/loongarch/kvm/mmu.c  |  6 ++++--
>  arch/loongarch/kvm/vcpu.c |  3 ++-
>  3 files changed, 15 insertions(+), 8 deletions(-)
>
> diff --git a/arch/loongarch/kvm/main.c b/arch/loongarch/kvm/main.c
> index ac804e77e844..c36e62ab0d91 100644
> --- a/arch/loongarch/kvm/main.c
> +++ b/arch/loongarch/kvm/main.c
> @@ -218,7 +218,8 @@ static void kvm_update_vpid(struct kvm_vcpu *vcpu, int cpu)
>                 ++vpid; /* vpid 0 reserved for root */
>
>                 /* start new vpid cycle */
> -               kvm_flush_tlb_all();
> +               if (!cpu_has_guestid)
> +                       kvm_flush_tlb_all();
>         }
>
>         context->vpid_cache = vpid;
> @@ -282,10 +283,13 @@ static void __kvm_check_vmid(struct kvm_vcpu *vcpu)
>  {
>         unsigned long vmid;
>
> -       vmid = vcpu->arch.vpid & vpid_mask;
> -       if (vcpu->arch.hw_vmid != vmid) {
> -               vcpu->arch.hw_vmid = vcpu->arch.vpid & vpid_mask;
> -               kvm_clear_request(KVM_REQ_TLB_FLUSH_GPA, vcpu);
> +       /* On some machines like 3A5000, vmid needs the same with vpid */
> +       if (!cpu_has_guestid) {
> +               vmid = vcpu->arch.vpid & vpid_mask;
> +               if (vcpu->arch.hw_vmid != vmid) {
> +                       vcpu->arch.hw_vmid = vcpu->arch.vpid & vpid_mask;
> +                       kvm_clear_request(KVM_REQ_TLB_FLUSH_GPA, vcpu);
> +               }
Merge Patch#3 and Patch#4, then __kvm_check_vmid() can handle both
cpu_has_guestid and !cpu_has_guestid cases together.


Huacai

>         }
>  }
>
> diff --git a/arch/loongarch/kvm/mmu.c b/arch/loongarch/kvm/mmu.c
> index e104897aa532..714640a2e614 100644
> --- a/arch/loongarch/kvm/mmu.c
> +++ b/arch/loongarch/kvm/mmu.c
> @@ -929,8 +929,10 @@ int kvm_handle_mm_fault(struct kvm_vcpu *vcpu, unsigned long gpa, bool write, in
>                  *
>                  * With SW PTW, invalid TLB is added in TLB refill exception.
>                  */
> -               vcpu->arch.flush_gpa = gpa;
> -               kvm_make_request(KVM_REQ_TLB_FLUSH_GPA, vcpu);
> +               if (!cpu_has_guestid) {
> +                       vcpu->arch.flush_gpa = gpa;
> +                       kvm_make_request(KVM_REQ_TLB_FLUSH_GPA, vcpu);
> +               }
>         }
>
>         return 0;
> diff --git a/arch/loongarch/kvm/vcpu.c b/arch/loongarch/kvm/vcpu.c
> index 20c207d80e31..0b2355aec932 100644
> --- a/arch/loongarch/kvm/vcpu.c
> +++ b/arch/loongarch/kvm/vcpu.c
> @@ -210,7 +210,8 @@ static int kvm_check_requests(struct kvm_vcpu *vcpu)
>                 return RESUME_GUEST;
>
>         if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
> -               vcpu->arch.vpid = 0;  /* Drop vpid for this vCPU */
> +               if (!cpu_has_guestid)
> +                       vcpu->arch.vpid = 0;  /* Drop vpid for this vCPU */
>
>         if (kvm_dirty_ring_check_request(vcpu))
>                 return RESUME_HOST;
> --
> 2.39.3
>

Re: [PATCH v2 5/5] LoongArch: KVM: Enable separate vmid feature

[Huacai Chen]

Hi, Bibo,

On Thu, Aug 6, 2026 at 10:15 AM Bibo Mao <maobibo@loongson.cn> wrote:
>
> With CSR GTLBC shortname for Guest TLB Control Register, separate vmid
> feature will be enabled if bit 14 CSR_GTLBC_USEVMID is set. Enable
> this feature if cpu_has_guestid is true when LVZ is enabled and the LVZ
> version is 2.
>
> Signed-off-by: Bibo Mao <maobibo@loongson.cn>
> ---
>  arch/loongarch/include/asm/loongarch.h | 5 +++++
>  arch/loongarch/kernel/cpu-probe.c      | 6 ++++++
>  arch/loongarch/kvm/main.c              | 4 +++-
>  3 files changed, 14 insertions(+), 1 deletion(-)
>
> diff --git a/arch/loongarch/include/asm/loongarch.h b/arch/loongarch/include/asm/loongarch.h
> index 2a6bc99177d8..a20fb68d8ac4 100644
> --- a/arch/loongarch/include/asm/loongarch.h
> +++ b/arch/loongarch/include/asm/loongarch.h
> @@ -138,6 +138,9 @@
>  #define  CPUCFG6_PMBITS_SHIFT          8
>  #define  CPUCFG6_UPM                   BIT(14)
>
> +#define LOONGARCH_CPUCFG8              0x8
> +#define  CPUCFG8_VMID                  BIT(8)
> +
>  #define LOONGARCH_CPUCFG16             0x10
>  #define  CPUCFG16_L1_IUPRE             BIT(0)
>  #define  CPUCFG16_L1_IUUNIFY           BIT(1)
> @@ -350,6 +353,8 @@
>  #define  CSR_GTLBC_TGID_WIDTH          8
>  #define  CSR_GTLBC_TGID_SHIFT_END      (CSR_GTLBC_TGID_SHIFT + CSR_GTLBC_TGID_WIDTH - 1)
>  #define  CSR_GTLBC_TGID                        (_ULCAST_(0xff) << CSR_GTLBC_TGID_SHIFT)
> +#define  CSR_GTLBC_USEVMID_SHIFT       14
> +#define  CSR_GTLBC_USEVMID             (_ULCAST_(0x1) << CSR_GTLBC_USEVMID_SHIFT)

Other fields in GTLBC is TGID, so it is better to name it
CSR_GTLBC_USETGID, just use vpid/vmid for software purely.



Huacai

>  #define  CSR_GTLBC_TOTI_SHIFT          13
>  #define  CSR_GTLBC_TOTI                        (_ULCAST_(0x1) << CSR_GTLBC_TOTI_SHIFT)
>  #define  CSR_GTLBC_USETGID_SHIFT       12
> diff --git a/arch/loongarch/kernel/cpu-probe.c b/arch/loongarch/kernel/cpu-probe.c
> index 74d31f260dfd..fc68f695d49c 100644
> --- a/arch/loongarch/kernel/cpu-probe.c
> +++ b/arch/loongarch/kernel/cpu-probe.c
> @@ -241,6 +241,12 @@ static void cpu_probe_common(struct cpuinfo_loongarch *c)
>         if (config & CPUCFG6_PMP)
>                 c->options |= LOONGARCH_CPU_PMP;
>
> +       if (c->options & LOONGARCH_CPU_LVZ) {
> +               config = read_cpucfg(LOONGARCH_CPUCFG8);
> +               if (config & CPUCFG8_VMID)
> +                       c->options |= LOONGARCH_CPU_GUESTID;
> +       }
> +
>         config = csr_read32(LOONGARCH_CSR_ASID);
>         config = (config & CSR_ASID_BIT) >> CSR_ASID_BIT_SHIFT;
>         asid_mask = GENMASK(config - 1, 0);
> diff --git a/arch/loongarch/kvm/main.c b/arch/loongarch/kvm/main.c
> index 72c1d23156e5..712b078db0d5 100644
> --- a/arch/loongarch/kvm/main.c
> +++ b/arch/loongarch/kvm/main.c
> @@ -359,7 +359,7 @@ int kvm_arch_enable_virtualization_cpu(void)
>         write_csr_gcfg(0);
>         write_csr_gstat(0);
>         write_csr_gintc(0);
> -       clear_csr_gtlbc(CSR_GTLBC_USETGID | CSR_GTLBC_TOTI);
> +       clear_csr_gtlbc(CSR_GTLBC_USETGID | CSR_GTLBC_TOTI | CSR_GTLBC_USEVMID);
>
>         /*
>          * Enable virtualization features granting guest direct control of
> @@ -382,6 +382,8 @@ int kvm_arch_enable_virtualization_cpu(void)
>
>         /* Enable using TGID  */
>         set_csr_gtlbc(CSR_GTLBC_USETGID);
> +       if (cpu_has_guestid)
> +               set_csr_gtlbc(CSR_GTLBC_USEVMID);
>         kvm_debug("GCFG:%lx GSTAT:%lx GINTC:%lx GTLBC:%lx",
>                   read_csr_gcfg(), read_csr_gstat(), read_csr_gintc(), read_csr_gtlbc());
>
> --
> 2.39.3
>

Re: [PATCH v2 1/5] LoongArch: KVM: Add vmid support for stage2 MMU

[Bibo Mao]

On 2026/8/6 下午8:20, Huacai Chen wrote:
> Hi, Bibo,
> 
> On Thu, Aug 6, 2026 at 10:14 AM Bibo Mao <maobibo@loongson.cn> wrote:
>>
>> LoongArch KVM hypervisor supports two-level MMU, vpid index is used
>> for stage1 MMU and vmid index is used for stage2 MMU.
>>
>> On 3A5000, vmid must be the same with vpid. On 3A6000 platform vmid
>> may separate from vpid. If vCPU migrate to different physical CPUs,
>> vpid need change however vmid can keep unchanged, so that TLB entries
>> for stage2 MMU is valid still. Also vmid index of the whole VM machine
>> is the same on one physical CPU, all vCPUs on the VM can share the
>> same vmid index on one physical CPU.
>>
>> Here hw vmid index is added and it keeps the same with hw vpid still.
> HW VPID means GSTAT.GID, HW VMID means GTLBC.TGID, right? It is useful
> to describe it in the commit message.
yes, it is right.
Will add this description in the commit message.
> 
> 
>>
>> Signed-off-by: Bibo Mao <maobibo@loongson.cn>
>> ---
>>   arch/loongarch/include/asm/kvm_host.h | 3 +++
>>   arch/loongarch/kernel/asm-offsets.c   | 1 +
>>   arch/loongarch/kvm/main.c             | 1 +
>>   arch/loongarch/kvm/switch.S           | 5 ++---
>>   arch/loongarch/kvm/tlb.c              | 5 ++++-
>>   5 files changed, 11 insertions(+), 4 deletions(-)
>>
>> diff --git a/arch/loongarch/include/asm/kvm_host.h b/arch/loongarch/include/asm/kvm_host.h
>> index 23cfbecebbd7..78f97dea124d 100644
>> --- a/arch/loongarch/include/asm/kvm_host.h
>> +++ b/arch/loongarch/include/asm/kvm_host.h
>> @@ -232,6 +232,9 @@ struct kvm_vcpu_arch {
>>          /* Cache for pages needed inside spinlock regions */
>>          struct kvm_mmu_memory_cache mmu_page_cache;
>>
>> +       /* hw vmid info for guest VM */
>> +       unsigned long hw_vmid;
> Since this is only used to write GCNTC.TGID, simply rename it to tgid
> can eliminate confusion.
ok, tgid sounds good to me.
> 
>> +
>>          /* vcpu's vpid */
>>          u64 vpid;
>>          gpa_t flush_gpa;
>> diff --git a/arch/loongarch/kernel/asm-offsets.c b/arch/loongarch/kernel/asm-offsets.c
>> index 1b861cbc5e10..065ced1f3c1f 100644
>> --- a/arch/loongarch/kernel/asm-offsets.c
>> +++ b/arch/loongarch/kernel/asm-offsets.c
>> @@ -300,6 +300,7 @@ static void __used output_kvm_defines(void)
>>          OFFSET(KVM_ARCH_HSP, kvm_vcpu_arch, host_sp);
>>          OFFSET(KVM_ARCH_HTP, kvm_vcpu_arch, host_tp);
>>          OFFSET(KVM_ARCH_HPGD, kvm_vcpu_arch, host_pgd);
>> +       OFFSET(KVM_ARCH_VMID, kvm_vcpu_arch, hw_vmid);
>>          OFFSET(KVM_ARCH_KVMPGD, kvm_vcpu_arch, kvm_pgd);
>>          OFFSET(KVM_ARCH_HANDLE_EXIT, kvm_vcpu_arch, handle_exit);
>>          OFFSET(KVM_ARCH_HEENTRY, kvm_vcpu_arch, host_eentry);
>> diff --git a/arch/loongarch/kvm/main.c b/arch/loongarch/kvm/main.c
>> index 3e1005526f4b..401c84f38e8c 100644
>> --- a/arch/loongarch/kvm/main.c
>> +++ b/arch/loongarch/kvm/main.c
>> @@ -223,6 +223,7 @@ static void kvm_update_vpid(struct kvm_vcpu *vcpu, int cpu)
>>
>>          context->vpid_cache = vpid;
>>          vcpu->arch.vpid = vpid;
>> +       vcpu->arch.hw_vmid = vcpu->arch.vpid & vpid_mask;
> Merge Patch#1 and Patch#2, then we can avoid adding this line and then
> remove it immediately.
will merge Patch#1 and Patch#2 in next version.

Regards
Bibo Mao
> 
> 
>>   }
>>
>>   void kvm_check_vpid(struct kvm_vcpu *vcpu)
>> diff --git a/arch/loongarch/kvm/switch.S b/arch/loongarch/kvm/switch.S
>> index 936e4ae3e408..af972394fd55 100644
>> --- a/arch/loongarch/kvm/switch.S
>> +++ b/arch/loongarch/kvm/switch.S
>> @@ -66,9 +66,8 @@
>>          ld.d    t0, a2, KVM_ARCH_KVMPGD
>>          csrwr   t0, LOONGARCH_CSR_PGDL
>>
>> -       /* Mix GID and RID */
>> -       csrrd           t1, LOONGARCH_CSR_GSTAT
>> -       bstrpick.w      t1, t1, CSR_GSTAT_GID_SHIFT_END, CSR_GSTAT_GID_SHIFT
>> +       /* Set VMID for gpa --> hpa mapping */
>> +       ld.d            t1, a2, KVM_ARCH_VMID
>>          csrrd           t0, LOONGARCH_CSR_GTLBC
>>          bstrins.w       t0, t1, CSR_GTLBC_TGID_SHIFT_END, CSR_GTLBC_TGID_SHIFT
>>          csrwr           t0, LOONGARCH_CSR_GTLBC
>> diff --git a/arch/loongarch/kvm/tlb.c b/arch/loongarch/kvm/tlb.c
>> index ebdbe9264e9c..b25847aab968 100644
>> --- a/arch/loongarch/kvm/tlb.c
>> +++ b/arch/loongarch/kvm/tlb.c
>> @@ -23,7 +23,10 @@ void kvm_flush_tlb_all(void)
>>
>>   void kvm_flush_tlb_gpa(struct kvm_vcpu *vcpu, unsigned long gpa)
>>   {
>> +       unsigned int vmid;
>> +
>>          lockdep_assert_irqs_disabled();
>>          gpa &= (PAGE_MASK << 1);
>> -       invtlb(INVTLB_GID_ADDR, read_csr_gstat() & CSR_GSTAT_GID, gpa);
>> +       vmid = (vcpu->arch.hw_vmid << CSR_GSTAT_GID_SHIFT) & CSR_GSTAT_GID;
>> +       invtlb(INVTLB_GID_ADDR, vmid, gpa);
>>   }
>> --
>> 2.39.3
>>

Re: [PATCH v2 3/5] LoongArch: KVM: Add separate vmid feature support

[Bibo Mao]

On 2026/8/6 下午8:23, Huacai Chen wrote:
> Hi, Bibo,
> 
> On Thu, Aug 6, 2026 at 10:15 AM Bibo Mao <maobibo@loongson.cn> wrote:
>>
>> Feature cpu_has_guestid is used to check whether separate vmid/vpid
>> is supported or not. It is disabled by default, add this feature
>> checking, there is no function change.
>>
>> Signed-off-by: Bibo Mao <maobibo@loongson.cn>
>> ---
>>   arch/loongarch/kvm/main.c | 14 +++++++++-----
>>   arch/loongarch/kvm/mmu.c  |  6 ++++--
>>   arch/loongarch/kvm/vcpu.c |  3 ++-
>>   3 files changed, 15 insertions(+), 8 deletions(-)
>>
>> diff --git a/arch/loongarch/kvm/main.c b/arch/loongarch/kvm/main.c
>> index ac804e77e844..c36e62ab0d91 100644
>> --- a/arch/loongarch/kvm/main.c
>> +++ b/arch/loongarch/kvm/main.c
>> @@ -218,7 +218,8 @@ static void kvm_update_vpid(struct kvm_vcpu *vcpu, int cpu)
>>                  ++vpid; /* vpid 0 reserved for root */
>>
>>                  /* start new vpid cycle */
>> -               kvm_flush_tlb_all();
>> +               if (!cpu_has_guestid)
>> +                       kvm_flush_tlb_all();
>>          }
>>
>>          context->vpid_cache = vpid;
>> @@ -282,10 +283,13 @@ static void __kvm_check_vmid(struct kvm_vcpu *vcpu)
>>   {
>>          unsigned long vmid;
>>
>> -       vmid = vcpu->arch.vpid & vpid_mask;
>> -       if (vcpu->arch.hw_vmid != vmid) {
>> -               vcpu->arch.hw_vmid = vcpu->arch.vpid & vpid_mask;
>> -               kvm_clear_request(KVM_REQ_TLB_FLUSH_GPA, vcpu);
>> +       /* On some machines like 3A5000, vmid needs the same with vpid */
>> +       if (!cpu_has_guestid) {
>> +               vmid = vcpu->arch.vpid & vpid_mask;
>> +               if (vcpu->arch.hw_vmid != vmid) {
>> +                       vcpu->arch.hw_vmid = vcpu->arch.vpid & vpid_mask;
>> +                       kvm_clear_request(KVM_REQ_TLB_FLUSH_GPA, vcpu);
>> +               }
> Merge Patch#3 and Patch#4, then __kvm_check_vmid() can handle both
> cpu_has_guestid and !cpu_has_guestid cases together.
will merge Patch#3 and Patch#4 together in next version.

Regards
Bibo Mao

> 
> 
> Huacai
> 
>>          }
>>   }
>>
>> diff --git a/arch/loongarch/kvm/mmu.c b/arch/loongarch/kvm/mmu.c
>> index e104897aa532..714640a2e614 100644
>> --- a/arch/loongarch/kvm/mmu.c
>> +++ b/arch/loongarch/kvm/mmu.c
>> @@ -929,8 +929,10 @@ int kvm_handle_mm_fault(struct kvm_vcpu *vcpu, unsigned long gpa, bool write, in
>>                   *
>>                   * With SW PTW, invalid TLB is added in TLB refill exception.
>>                   */
>> -               vcpu->arch.flush_gpa = gpa;
>> -               kvm_make_request(KVM_REQ_TLB_FLUSH_GPA, vcpu);
>> +               if (!cpu_has_guestid) {
>> +                       vcpu->arch.flush_gpa = gpa;
>> +                       kvm_make_request(KVM_REQ_TLB_FLUSH_GPA, vcpu);
>> +               }
>>          }
>>
>>          return 0;
>> diff --git a/arch/loongarch/kvm/vcpu.c b/arch/loongarch/kvm/vcpu.c
>> index 20c207d80e31..0b2355aec932 100644
>> --- a/arch/loongarch/kvm/vcpu.c
>> +++ b/arch/loongarch/kvm/vcpu.c
>> @@ -210,7 +210,8 @@ static int kvm_check_requests(struct kvm_vcpu *vcpu)
>>                  return RESUME_GUEST;
>>
>>          if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
>> -               vcpu->arch.vpid = 0;  /* Drop vpid for this vCPU */
>> +               if (!cpu_has_guestid)
>> +                       vcpu->arch.vpid = 0;  /* Drop vpid for this vCPU */
>>
>>          if (kvm_dirty_ring_check_request(vcpu))
>>                  return RESUME_HOST;
>> --
>> 2.39.3
>>

Re: [PATCH v2 5/5] LoongArch: KVM: Enable separate vmid feature

[Bibo Mao]

On 2026/8/6 下午8:39, Huacai Chen wrote:
> Hi, Bibo,
> 
> On Thu, Aug 6, 2026 at 10:15 AM Bibo Mao <maobibo@loongson.cn> wrote:
>>
>> With CSR GTLBC shortname for Guest TLB Control Register, separate vmid
>> feature will be enabled if bit 14 CSR_GTLBC_USEVMID is set. Enable
>> this feature if cpu_has_guestid is true when LVZ is enabled and the LVZ
>> version is 2.
>>
>> Signed-off-by: Bibo Mao <maobibo@loongson.cn>
>> ---
>>   arch/loongarch/include/asm/loongarch.h | 5 +++++
>>   arch/loongarch/kernel/cpu-probe.c      | 6 ++++++
>>   arch/loongarch/kvm/main.c              | 4 +++-
>>   3 files changed, 14 insertions(+), 1 deletion(-)
>>
>> diff --git a/arch/loongarch/include/asm/loongarch.h b/arch/loongarch/include/asm/loongarch.h
>> index 2a6bc99177d8..a20fb68d8ac4 100644
>> --- a/arch/loongarch/include/asm/loongarch.h
>> +++ b/arch/loongarch/include/asm/loongarch.h
>> @@ -138,6 +138,9 @@
>>   #define  CPUCFG6_PMBITS_SHIFT          8
>>   #define  CPUCFG6_UPM                   BIT(14)
>>
>> +#define LOONGARCH_CPUCFG8              0x8
>> +#define  CPUCFG8_VMID                  BIT(8)
>> +
>>   #define LOONGARCH_CPUCFG16             0x10
>>   #define  CPUCFG16_L1_IUPRE             BIT(0)
>>   #define  CPUCFG16_L1_IUUNIFY           BIT(1)
>> @@ -350,6 +353,8 @@
>>   #define  CSR_GTLBC_TGID_WIDTH          8
>>   #define  CSR_GTLBC_TGID_SHIFT_END      (CSR_GTLBC_TGID_SHIFT + CSR_GTLBC_TGID_WIDTH - 1)
>>   #define  CSR_GTLBC_TGID                        (_ULCAST_(0xff) << CSR_GTLBC_TGID_SHIFT)
>> +#define  CSR_GTLBC_USEVMID_SHIFT       14
>> +#define  CSR_GTLBC_USEVMID             (_ULCAST_(0x1) << CSR_GTLBC_USEVMID_SHIFT)
> 
> Other fields in GTLBC is TGID, so it is better to name it
> CSR_GTLBC_USETGID, just use vpid/vmid for software purely.
  - clear_csr_gtlbc(CSR_GTLBC_USETGID | CSR_GTLBC_TOTI);
  + clear_csr_gtlbc(CSR_GTLBC_USETGID | CSR_GTLBC_TOTI | CSR_GTLBC_USEVMID);

There is CSR_GTLBC_USETGID enabled already which it bit 12 :)

> 
> 
> 
> Huacai
> 
>>   #define  CSR_GTLBC_TOTI_SHIFT          13
>>   #define  CSR_GTLBC_TOTI                        (_ULCAST_(0x1) << CSR_GTLBC_TOTI_SHIFT)
>>   #define  CSR_GTLBC_USETGID_SHIFT       12
>> diff --git a/arch/loongarch/kernel/cpu-probe.c b/arch/loongarch/kernel/cpu-probe.c
>> index 74d31f260dfd..fc68f695d49c 100644
>> --- a/arch/loongarch/kernel/cpu-probe.c
>> +++ b/arch/loongarch/kernel/cpu-probe.c
>> @@ -241,6 +241,12 @@ static void cpu_probe_common(struct cpuinfo_loongarch *c)
>>          if (config & CPUCFG6_PMP)
>>                  c->options |= LOONGARCH_CPU_PMP;
>>
>> +       if (c->options & LOONGARCH_CPU_LVZ) {
>> +               config = read_cpucfg(LOONGARCH_CPUCFG8);
>> +               if (config & CPUCFG8_VMID)
>> +                       c->options |= LOONGARCH_CPU_GUESTID;
>> +       }
>> +
>>          config = csr_read32(LOONGARCH_CSR_ASID);
>>          config = (config & CSR_ASID_BIT) >> CSR_ASID_BIT_SHIFT;
>>          asid_mask = GENMASK(config - 1, 0);
>> diff --git a/arch/loongarch/kvm/main.c b/arch/loongarch/kvm/main.c
>> index 72c1d23156e5..712b078db0d5 100644
>> --- a/arch/loongarch/kvm/main.c
>> +++ b/arch/loongarch/kvm/main.c
>> @@ -359,7 +359,7 @@ int kvm_arch_enable_virtualization_cpu(void)
>>          write_csr_gcfg(0);
>>          write_csr_gstat(0);
>>          write_csr_gintc(0);
>> -       clear_csr_gtlbc(CSR_GTLBC_USETGID | CSR_GTLBC_TOTI);
>> +       clear_csr_gtlbc(CSR_GTLBC_USETGID | CSR_GTLBC_TOTI | CSR_GTLBC_USEVMID);
>>
>>          /*
>>           * Enable virtualization features granting guest direct control of
>> @@ -382,6 +382,8 @@ int kvm_arch_enable_virtualization_cpu(void)
>>
>>          /* Enable using TGID  */
>>          set_csr_gtlbc(CSR_GTLBC_USETGID);
>> +       if (cpu_has_guestid)
>> +               set_csr_gtlbc(CSR_GTLBC_USEVMID);
>>          kvm_debug("GCFG:%lx GSTAT:%lx GINTC:%lx GTLBC:%lx",
>>                    read_csr_gcfg(), read_csr_gstat(), read_csr_gintc(), read_csr_gtlbc());
>>
>> --
>> 2.39.3
>>

Re: [PATCH v2 5/5] LoongArch: KVM: Enable separate vmid feature

[Huacai Chen]

On Thu, Aug 6, 2026 at 8:55 PM Bibo Mao <maobibo@loongson.cn> wrote:
>
>
>
> On 2026/8/6 下午8:39, Huacai Chen wrote:
> > Hi, Bibo,
> >
> > On Thu, Aug 6, 2026 at 10:15 AM Bibo Mao <maobibo@loongson.cn> wrote:
> >>
> >> With CSR GTLBC shortname for Guest TLB Control Register, separate vmid
> >> feature will be enabled if bit 14 CSR_GTLBC_USEVMID is set. Enable
> >> this feature if cpu_has_guestid is true when LVZ is enabled and the LVZ
> >> version is 2.
> >>
> >> Signed-off-by: Bibo Mao <maobibo@loongson.cn>
> >> ---
> >>   arch/loongarch/include/asm/loongarch.h | 5 +++++
> >>   arch/loongarch/kernel/cpu-probe.c      | 6 ++++++
> >>   arch/loongarch/kvm/main.c              | 4 +++-
> >>   3 files changed, 14 insertions(+), 1 deletion(-)
> >>
> >> diff --git a/arch/loongarch/include/asm/loongarch.h b/arch/loongarch/include/asm/loongarch.h
> >> index 2a6bc99177d8..a20fb68d8ac4 100644
> >> --- a/arch/loongarch/include/asm/loongarch.h
> >> +++ b/arch/loongarch/include/asm/loongarch.h
> >> @@ -138,6 +138,9 @@
> >>   #define  CPUCFG6_PMBITS_SHIFT          8
> >>   #define  CPUCFG6_UPM                   BIT(14)
> >>
> >> +#define LOONGARCH_CPUCFG8              0x8
> >> +#define  CPUCFG8_VMID                  BIT(8)
> >> +
> >>   #define LOONGARCH_CPUCFG16             0x10
> >>   #define  CPUCFG16_L1_IUPRE             BIT(0)
> >>   #define  CPUCFG16_L1_IUUNIFY           BIT(1)
> >> @@ -350,6 +353,8 @@
> >>   #define  CSR_GTLBC_TGID_WIDTH          8
> >>   #define  CSR_GTLBC_TGID_SHIFT_END      (CSR_GTLBC_TGID_SHIFT + CSR_GTLBC_TGID_WIDTH - 1)
> >>   #define  CSR_GTLBC_TGID                        (_ULCAST_(0xff) << CSR_GTLBC_TGID_SHIFT)
> >> +#define  CSR_GTLBC_USEVMID_SHIFT       14
> >> +#define  CSR_GTLBC_USEVMID             (_ULCAST_(0x1) << CSR_GTLBC_USEVMID_SHIFT)
> >
> > Other fields in GTLBC is TGID, so it is better to name it
> > CSR_GTLBC_USETGID, just use vpid/vmid for software purely.
>   - clear_csr_gtlbc(CSR_GTLBC_USETGID | CSR_GTLBC_TOTI);
>   + clear_csr_gtlbc(CSR_GTLBC_USETGID | CSR_GTLBC_TOTI | CSR_GTLBC_USEVMID);
>
> There is CSR_GTLBC_USETGID enabled already which it bit 12 :)
Emmm, what is the difference between bit 12 and bit 14?

Huacai

>
> >
> >
> >
> > Huacai
> >
> >>   #define  CSR_GTLBC_TOTI_SHIFT          13
> >>   #define  CSR_GTLBC_TOTI                        (_ULCAST_(0x1) << CSR_GTLBC_TOTI_SHIFT)
> >>   #define  CSR_GTLBC_USETGID_SHIFT       12
> >> diff --git a/arch/loongarch/kernel/cpu-probe.c b/arch/loongarch/kernel/cpu-probe.c
> >> index 74d31f260dfd..fc68f695d49c 100644
> >> --- a/arch/loongarch/kernel/cpu-probe.c
> >> +++ b/arch/loongarch/kernel/cpu-probe.c
> >> @@ -241,6 +241,12 @@ static void cpu_probe_common(struct cpuinfo_loongarch *c)
> >>          if (config & CPUCFG6_PMP)
> >>                  c->options |= LOONGARCH_CPU_PMP;
> >>
> >> +       if (c->options & LOONGARCH_CPU_LVZ) {
> >> +               config = read_cpucfg(LOONGARCH_CPUCFG8);
> >> +               if (config & CPUCFG8_VMID)
> >> +                       c->options |= LOONGARCH_CPU_GUESTID;
> >> +       }
> >> +
> >>          config = csr_read32(LOONGARCH_CSR_ASID);
> >>          config = (config & CSR_ASID_BIT) >> CSR_ASID_BIT_SHIFT;
> >>          asid_mask = GENMASK(config - 1, 0);
> >> diff --git a/arch/loongarch/kvm/main.c b/arch/loongarch/kvm/main.c
> >> index 72c1d23156e5..712b078db0d5 100644
> >> --- a/arch/loongarch/kvm/main.c
> >> +++ b/arch/loongarch/kvm/main.c
> >> @@ -359,7 +359,7 @@ int kvm_arch_enable_virtualization_cpu(void)
> >>          write_csr_gcfg(0);
> >>          write_csr_gstat(0);
> >>          write_csr_gintc(0);
> >> -       clear_csr_gtlbc(CSR_GTLBC_USETGID | CSR_GTLBC_TOTI);
> >> +       clear_csr_gtlbc(CSR_GTLBC_USETGID | CSR_GTLBC_TOTI | CSR_GTLBC_USEVMID);
> >>
> >>          /*
> >>           * Enable virtualization features granting guest direct control of
> >> @@ -382,6 +382,8 @@ int kvm_arch_enable_virtualization_cpu(void)
> >>
> >>          /* Enable using TGID  */
> >>          set_csr_gtlbc(CSR_GTLBC_USETGID);
> >> +       if (cpu_has_guestid)
> >> +               set_csr_gtlbc(CSR_GTLBC_USEVMID);
> >>          kvm_debug("GCFG:%lx GSTAT:%lx GINTC:%lx GTLBC:%lx",
> >>                    read_csr_gcfg(), read_csr_gstat(), read_csr_gintc(), read_csr_gtlbc());
> >>
> >> --
> >> 2.39.3
> >>
>

Re: [PATCH v2 5/5] LoongArch: KVM: Enable separate vmid feature

[Bibo Mao]

On 2026/8/6 下午9:03, Huacai Chen wrote:
> On Thu, Aug 6, 2026 at 8:55 PM Bibo Mao <maobibo@loongson.cn> wrote:
>>
>>
>>
>> On 2026/8/6 下午8:39, Huacai Chen wrote:
>>> Hi, Bibo,
>>>
>>> On Thu, Aug 6, 2026 at 10:15 AM Bibo Mao <maobibo@loongson.cn> wrote:
>>>>
>>>> With CSR GTLBC shortname for Guest TLB Control Register, separate vmid
>>>> feature will be enabled if bit 14 CSR_GTLBC_USEVMID is set. Enable
>>>> this feature if cpu_has_guestid is true when LVZ is enabled and the LVZ
>>>> version is 2.
>>>>
>>>> Signed-off-by: Bibo Mao <maobibo@loongson.cn>
>>>> ---
>>>>    arch/loongarch/include/asm/loongarch.h | 5 +++++
>>>>    arch/loongarch/kernel/cpu-probe.c      | 6 ++++++
>>>>    arch/loongarch/kvm/main.c              | 4 +++-
>>>>    3 files changed, 14 insertions(+), 1 deletion(-)
>>>>
>>>> diff --git a/arch/loongarch/include/asm/loongarch.h b/arch/loongarch/include/asm/loongarch.h
>>>> index 2a6bc99177d8..a20fb68d8ac4 100644
>>>> --- a/arch/loongarch/include/asm/loongarch.h
>>>> +++ b/arch/loongarch/include/asm/loongarch.h
>>>> @@ -138,6 +138,9 @@
>>>>    #define  CPUCFG6_PMBITS_SHIFT          8
>>>>    #define  CPUCFG6_UPM                   BIT(14)
>>>>
>>>> +#define LOONGARCH_CPUCFG8              0x8
>>>> +#define  CPUCFG8_VMID                  BIT(8)
>>>> +
>>>>    #define LOONGARCH_CPUCFG16             0x10
>>>>    #define  CPUCFG16_L1_IUPRE             BIT(0)
>>>>    #define  CPUCFG16_L1_IUUNIFY           BIT(1)
>>>> @@ -350,6 +353,8 @@
>>>>    #define  CSR_GTLBC_TGID_WIDTH          8
>>>>    #define  CSR_GTLBC_TGID_SHIFT_END      (CSR_GTLBC_TGID_SHIFT + CSR_GTLBC_TGID_WIDTH - 1)
>>>>    #define  CSR_GTLBC_TGID                        (_ULCAST_(0xff) << CSR_GTLBC_TGID_SHIFT)
>>>> +#define  CSR_GTLBC_USEVMID_SHIFT       14
>>>> +#define  CSR_GTLBC_USEVMID             (_ULCAST_(0x1) << CSR_GTLBC_USEVMID_SHIFT)
>>>
>>> Other fields in GTLBC is TGID, so it is better to name it
>>> CSR_GTLBC_USETGID, just use vpid/vmid for software purely.
>>    - clear_csr_gtlbc(CSR_GTLBC_USETGID | CSR_GTLBC_TOTI);
>>    + clear_csr_gtlbc(CSR_GTLBC_USETGID | CSR_GTLBC_TOTI | CSR_GTLBC_USEVMID);
>>
>> There is CSR_GTLBC_USETGID enabled already which it bit 12 :)
> Emmm, what is the difference between bit 12 and bit 14?
CSR_GTLBC_USETGID is choice to use TGID/GID in host mode, including 
refill exception of stage2 mmu or generic host mode.

I agree that vpid/vmid is purely software, and I will find the latest 
manual and check whether bit 14 is updated or not.

Regards
Bibo Mao
> 
> Huacai
> 
>>
>>>
>>>
>>>
>>> Huacai
>>>
>>>>    #define  CSR_GTLBC_TOTI_SHIFT          13
>>>>    #define  CSR_GTLBC_TOTI                        (_ULCAST_(0x1) << CSR_GTLBC_TOTI_SHIFT)
>>>>    #define  CSR_GTLBC_USETGID_SHIFT       12
>>>> diff --git a/arch/loongarch/kernel/cpu-probe.c b/arch/loongarch/kernel/cpu-probe.c
>>>> index 74d31f260dfd..fc68f695d49c 100644
>>>> --- a/arch/loongarch/kernel/cpu-probe.c
>>>> +++ b/arch/loongarch/kernel/cpu-probe.c
>>>> @@ -241,6 +241,12 @@ static void cpu_probe_common(struct cpuinfo_loongarch *c)
>>>>           if (config & CPUCFG6_PMP)
>>>>                   c->options |= LOONGARCH_CPU_PMP;
>>>>
>>>> +       if (c->options & LOONGARCH_CPU_LVZ) {
>>>> +               config = read_cpucfg(LOONGARCH_CPUCFG8);
>>>> +               if (config & CPUCFG8_VMID)
>>>> +                       c->options |= LOONGARCH_CPU_GUESTID;
>>>> +       }
>>>> +
>>>>           config = csr_read32(LOONGARCH_CSR_ASID);
>>>>           config = (config & CSR_ASID_BIT) >> CSR_ASID_BIT_SHIFT;
>>>>           asid_mask = GENMASK(config - 1, 0);
>>>> diff --git a/arch/loongarch/kvm/main.c b/arch/loongarch/kvm/main.c
>>>> index 72c1d23156e5..712b078db0d5 100644
>>>> --- a/arch/loongarch/kvm/main.c
>>>> +++ b/arch/loongarch/kvm/main.c
>>>> @@ -359,7 +359,7 @@ int kvm_arch_enable_virtualization_cpu(void)
>>>>           write_csr_gcfg(0);
>>>>           write_csr_gstat(0);
>>>>           write_csr_gintc(0);
>>>> -       clear_csr_gtlbc(CSR_GTLBC_USETGID | CSR_GTLBC_TOTI);
>>>> +       clear_csr_gtlbc(CSR_GTLBC_USETGID | CSR_GTLBC_TOTI | CSR_GTLBC_USEVMID);
>>>>
>>>>           /*
>>>>            * Enable virtualization features granting guest direct control of
>>>> @@ -382,6 +382,8 @@ int kvm_arch_enable_virtualization_cpu(void)
>>>>
>>>>           /* Enable using TGID  */
>>>>           set_csr_gtlbc(CSR_GTLBC_USETGID);
>>>> +       if (cpu_has_guestid)
>>>> +               set_csr_gtlbc(CSR_GTLBC_USEVMID);
>>>>           kvm_debug("GCFG:%lx GSTAT:%lx GINTC:%lx GTLBC:%lx",
>>>>                     read_csr_gcfg(), read_csr_gstat(), read_csr_gintc(), read_csr_gtlbc());
>>>>
>>>> --
>>>> 2.39.3
>>>>
>>