Re: [PATCH v5 04/49] KVM: arm64: gic-v5: Define remaining IRS MMIO registers

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] `GICV5_IRS_SETLPIR` is incorrectly defined with an offset of `0x0000`, which aliases the read-only `GICV5_IRS_IDR0` register.
--

--- Patch [4]: [PATCH v5 04/49] KVM: arm64: gic-v5: Define remaining IRS MMIO registers ---
commit 4e5353692b267764abed96c8124c3aebc194d9cf
Author: Sascha Bischoff <Sascha.Bischoff@arm.com>

KVM: arm64: gic-v5: Define remaining IRS MMIO registers

Complete the set of defined IRS MMIO registers in the GICv5 header file.
Up until now, the set of defined IRS MMIO registers has been driven by
code requirements. However, in order to properly emulate the IRS MMIO
interface in KVM, the full set of IRS MMIO registers needs to be added.

> diff --git a/include/linux/irqchip/arm-gic-v5.h b/include/linux/irqchip/arm-gic-v5.h
> index 681c5c51207d6..83cfcd056b250 100644
> --- a/include/linux/irqchip/arm-gic-v5.h
> +++ b/include/linux/irqchip/arm-gic-v5.h
> @@ -62,20 +62,34 @@

[ ... ]

>  /*
>   * IRS registers and tables structures
>   */
>  #define GICV5_IRS_IDR0			0x0000
>  #define GICV5_IRS_IDR1			0x0004
>  #define GICV5_IRS_IDR2			0x0008

[ ... ]

> @@ -166,15 +255,111 @@

[ ... ]

>  #define GICV5_ISTL1E_VALID		BIT_ULL(0)
> +#define GICV5_IRS_ISTL1E_SIZE		8UL
>  
>  #define GICV5_ISTL1E_L2_ADDR_MASK	GENMASK_ULL(55, 12)
>  
> +#define GICV5_IRS_SETLPIR		0x0000

[Severity: High]
Is GICV5_IRS_SETLPIR defined with the correct offset here?

This aliases the read-only GICV5_IRS_IDR0 register defined earlier at 0x0000.

If KVM implements the IRS MMIO emulator expecting guest writes to the SETLPIR
register at offset 0x0000, will guests attempting to use the correct
architectural offset for SETLPIR fail?

Could writes to 0x0000 also interfere with IDR0 emulation, potentially
breaking LPI generation via the IRS in virtual machines?

> +#define GICV5_IRS_SETLPIR_ID		GENMASK(23, 0)
> +
>  /*
>   * ITS registers and tables structures
>   */

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260807111159.429128-1-sascha.bischoff@arm.com?part=4