From: fangyu.yu@linux.alibaba.com
To: andrew.jones@oss.qualcomm.com
Cc: alex@ghiti.fr, anup@brainfault.org, aou@eecs.berkeley.edu,
atish.patra@linux.dev, baolu.lu@linux.intel.com,
fangyu.yu@linux.alibaba.com, guoren@kernel.org,
iommu@lists.linux.dev, jgg@nvidia.com, jgg@ziepe.ca,
joro@8bytes.org, kevin.tian@intel.com,
kvm-riscv@lists.infradead.org, kvm@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org,
palmer@dabbelt.com, pjw@kernel.org, robin.murphy@arm.com,
skhawaja@google.com, tjeznach@rivosinc.com, vasant.hegde@amd.com,
will@kernel.org, zong.li@sifive.com
Subject: Re: [RFC PATCH v2 05/10] iommu/riscv: support GSCID and GVMA invalidation command
Date: Tue, 18 Aug 2026 21:34:47 +0800 [thread overview]
Message-ID: <20260818133447.44426-1-fangyu.yu@linux.alibaba.com> (raw)
In-Reply-To: <4mcwrlk7yc4kozsqbrumf5gbknydquzwdb4g7lv6bgjk7m6ob2@alld2yusipnq>
>> @@ -1212,8 +1225,15 @@ static int riscv_iommu_attach_paging_domain(struct iommu_domain *iommu_domain,
>> if (!riscv_iommu_pt_supported(iommu, pt_info.fsc_iosatp_mode))
>> return -ENODEV;
>
>This needs something like the below diff squashed in.
>
>Thanks,
>drew
>
Thanks, agreed.
I'll split the helper into fsc/iohgatp variants and squash this into
patch 5 for next version.
>>
>> - dc.fsc = FIELD_PREP(RISCV_IOMMU_PC_FSC_MODE, pt_info.fsc_iosatp_mode) |
>> - FIELD_PREP(RISCV_IOMMU_PC_FSC_PPN, pt_info.ppn);
>> + if (domain->gscid) {
>> + dc.iohgatp = FIELD_PREP(RISCV_IOMMU_DC_IOHGATP_MODE, pt_info.iohgatp_mode) |
>> + FIELD_PREP(RISCV_IOMMU_DC_IOHGATP_GSCID, domain->gscid) |
>> + FIELD_PREP(RISCV_IOMMU_DC_IOHGATP_PPN, pt_info.ppn);
>> + } else {
>> + dc.fsc = FIELD_PREP(RISCV_IOMMU_PC_FSC_MODE, pt_info.fsc_iosatp_mode) |
>> + FIELD_PREP(RISCV_IOMMU_PC_FSC_PPN, pt_info.ppn);
>> + }
>> +
>> dc.ta = FIELD_PREP(RISCV_IOMMU_PC_TA_PSCID, domain->pscid) |
>> RISCV_IOMMU_PC_TA_V;
>>
>
>diff --git a/drivers/iommu/riscv/iommu.c b/drivers/iommu/riscv/iommu.c
>index 307baf33c646..434d2d4f26f5 100644
>--- a/drivers/iommu/riscv/iommu.c
>+++ b/drivers/iommu/riscv/iommu.c
>@@ -1262,9 +1262,9 @@ static void riscv_iommu_free_paging_domain(struct iommu_domain *iommu_domain)
> kfree(domain);
> }
>
>-static bool riscv_iommu_pt_supported(struct riscv_iommu_device *iommu, int pgd_mode)
>+static bool riscv_iommu_fsc_supported(struct riscv_iommu_device *iommu, int mode)
> {
>- switch (pgd_mode) {
>+ switch (mode) {
> case RISCV_IOMMU_DC_FSC_IOSATP_MODE_SV39:
> return iommu->caps & RISCV_IOMMU_CAPABILITIES_SV39;
>
>@@ -1277,6 +1277,21 @@ static bool riscv_iommu_pt_supported(struct riscv_iommu_device *iommu, int pgd_m
> return false;
> }
>
>+static bool riscv_iommu_iohgatp_supported(struct riscv_iommu_device *iommu, int mode)
>+{
>+ switch (mode) {
>+ case RISCV_IOMMU_DC_IOHGATP_MODE_SV39X4:
>+ return iommu->caps & RISCV_IOMMU_CAPABILITIES_SV39X4;
>+
>+ case RISCV_IOMMU_DC_IOHGATP_MODE_SV48X4:
>+ return iommu->caps & RISCV_IOMMU_CAPABILITIES_SV48X4;
>+
>+ case RISCV_IOMMU_DC_IOHGATP_MODE_SV57X4:
>+ return iommu->caps & RISCV_IOMMU_CAPABILITIES_SV57X4;
>+ }
>+ return false;
>+}
>+
> static int riscv_iommu_attach_paging_domain(struct iommu_domain *iommu_domain,
> struct device *dev,
> struct iommu_domain *old)
>@@ -1294,14 +1309,17 @@ static int riscv_iommu_attach_paging_domain(struct iommu_domain *iommu_domain,
>
> pt_iommu_riscv_64_hw_info(&domain->riscvpt, &pt_info);
>
>- if (!riscv_iommu_pt_supported(iommu, pt_info.fsc_iosatp_mode))
>- return -ENODEV;
>-
> if (domain->gscid) {
>+ if (!riscv_iommu_iohgatp_supported(iommu, pt_info.iohgatp_mode))
>+ return -ENODEV;
>+
> dc.iohgatp = FIELD_PREP(RISCV_IOMMU_DC_IOHGATP_MODE, pt_info.iohgatp_mode) |
> FIELD_PREP(RISCV_IOMMU_DC_IOHGATP_GSCID, domain->gscid) |
> FIELD_PREP(RISCV_IOMMU_DC_IOHGATP_PPN, pt_info.ppn);
> } else {
>+ if (!riscv_iommu_fsc_supported(iommu, pt_info.fsc_iosatp_mode))
>+ return -ENODEV;
>+
> dc.fsc = FIELD_PREP(RISCV_IOMMU_PC_FSC_MODE, pt_info.fsc_iosatp_mode) |
> FIELD_PREP(RISCV_IOMMU_PC_FSC_PPN, pt_info.ppn);
> }
next prev parent reply other threads:[~2026-08-18 13:34 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-05-07 11:36 [RFC PATCH v2 00/10] iommu/riscv: Add hardware dirty tracking for second-stage domains fangyu.yu
2026-05-07 11:36 ` [RFC PATCH v2 01/10] iommupt: Add RISC-V Second-stage (iohgatp) page table support fangyu.yu
2026-08-18 9:30 ` Andrew Jones
2026-08-18 12:59 ` fangyu.yu
2026-05-07 11:36 ` [RFC PATCH v2 02/10] iommupt: Add RISC-V dirty tracking PTE ops fangyu.yu
2026-05-07 11:36 ` [RFC PATCH v2 03/10] iommu/riscv: report iommu capabilities fangyu.yu
2026-05-07 11:37 ` [RFC PATCH v2 04/10] iommu/riscv: use data structure instead of individual values fangyu.yu
2026-05-07 11:37 ` [RFC PATCH v2 05/10] iommu/riscv: support GSCID and GVMA invalidation command fangyu.yu
2026-08-18 10:59 ` Andrew Jones
2026-08-18 13:34 ` fangyu.yu [this message]
2026-05-07 11:37 ` [RFC PATCH v2 06/10] RISC-V: KVM: Enable KVM_VFIO interfaces on RISC-V arch fangyu.yu
2026-05-07 11:37 ` [RFC PATCH v2 07/10] iommu/riscv: Add domain_alloc_paging_flags for second-stage domain fangyu.yu
2026-08-18 11:05 ` Andrew Jones
2026-08-18 14:03 ` fangyu.yu
2026-05-07 11:37 ` [RFC PATCH v2 08/10] iommu/riscv: Pre-enable GADE for second-stage domains fangyu.yu
2026-05-07 11:37 ` [RFC PATCH v2 09/10] iommu/riscv: Add dirty tracking support " fangyu.yu
2026-05-07 11:37 ` [RFC PATCH v2 10/10] iommu/riscv: Add IOTINVAL.GVMA after updating DDT/PDT entries fangyu.yu
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