From: sashiko-bot@kernel.org
To: "Itaru Kitayama" <itaru.kitayama@fujitsu.com>
Cc: "Oliver Upton" <oupton@kernel.org>,
"Marc Zyngier" <maz@kernel.org>,
kvm@vger.kernel.org, kvmarm@lists.linux.dev
Subject: Re: [PATCH 1/2] KVM: selftest: arm64: Support 5-level paging in stage 1 translation table
Date: Tue, 25 Aug 2026 21:35:33 +0000 [thread overview]
Message-ID: <20260825213534.0D4A41F000E9@smtp.kernel.org> (raw)
In-Reply-To: <20260826-arm64-52bit-va-v1-1-14ec98211363@fujitsu.com>
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Low] The page table dump function `pte_dump()` is missing the 'p4d' string for 5-level paging.
--
commit a04aa92b1663291806024b3dd2c32f253a43baf3
Author: Itaru Kitayama <itaru.kitayama@fujitsu.com>
KVM: selftest: arm64: Support 5-level paging in stage 1 translation table
Add p4d_index() for when 5-level paging required, i.e., V52 guest mode
IDs. With the index helper function, _virt_pg_map() handles 5-level
paging case, and aarch64_vcpu_setup() now is aware of the new V52 guest
mode IDs.
> diff --git a/tools/testing/selftests/kvm/lib/arm64/processor.c b/tools/testing/selftests/kvm/lib/arm64/processor.c
> index 01325bf4d36fc..9108e14a9b5be 100644
> --- a/tools/testing/selftests/kvm/lib/arm64/processor.c
> +++ b/tools/testing/selftests/kvm/lib/arm64/processor.c
[ ... ]
> @@ -182,18 +200,35 @@ void virt_arch_pg_map(struct kvm_vm *vm, gva_t gva, gpa_t gpa)
>
> u64 *virt_get_pte_hva_at_level(struct kvm_vm *vm, gva_t gva, int level)
> {
> + int start_level = 4 - vm->mmu.pgtable_levels;
> u64 *ptep;
>
> + TEST_ASSERT(level >= start_level && level <= 3,
> + "Invalid translation level %d, valid range is %d-3",
> + level, start_level);
> +
> if (!vm->mmu.pgd_created)
> goto unmapped_gva;
>
> ptep = addr_gpa2hva(vm, vm->mmu.pgd) + pgd_index(vm, gva) * 8;
> if (!ptep)
> goto unmapped_gva;
> - if (level == 0)
> + /*
> + * Stage-1 translation starts at level -1 for a five-level page
> + * table, and at levels 0, 1, or 2 for four-, three-, or two-level
> + * page tables, respectively.
> + */
> + if (level == start_level)
> return ptep;
>
> switch (vm->mmu.pgtable_levels) {
> + case 5:
> + ptep = addr_gpa2hva(vm, pte_addr(vm, *ptep)) + p4d_index(vm, gva) * 8;
> + if (!ptep)
> + goto unmapped_gva;
> + if (level == 0)
> + break;
> + /* fall through */
> case 4:
[Severity: Low]
Does pte_dump() also need to be updated to handle the new p4d level?
In tools/testing/selftests/kvm/lib/arm64/processor.c:pte_dump():
static const char * const type[] = { "", "pud", "pmd", "pte" };
With 5-level paging enabled, virt_arch_dump() starts with level 0. The
pte_dump() function will access index 0 and print an empty string instead
of "p4d".
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260826-arm64-52bit-va-v1-0-14ec98211363@fujitsu.com?part=1
next prev parent reply other threads:[~2026-08-25 21:35 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-08-25 21:18 [PATCH 0/2] 52-bit VA guest mode ID support Itaru Kitayama
2026-08-25 21:18 ` [PATCH 1/2] KVM: selftest: arm64: Support 5-level paging in stage 1 translation table Itaru Kitayama
2026-08-25 21:35 ` sashiko-bot [this message]
2026-08-25 21:18 ` [PATCH 2/2] KVM: selftests: arm64: Add 52-bit VA guest modes Itaru Kitayama
2026-08-25 21:32 ` sashiko-bot
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