[PATCH v4 01/21] KVM: SVM: Drop counter MSR checks in amd_is_valid_msr()

[Zide Chen <zide.chen@intel.com>]

amd_msr_idx_to_pmc() accurately validates individual counter MSRs by
checking whether the corresponding counter is supported for the vCPU.
Validating counter MSRs again in amd_is_valid_msr() is redundant.

Furthermore, validating counter MSRs using broad checks like
"pmu->version > 0" or "PERFCTR_CORE" is inaccurate and misleading. It
falsely validates unexposed counters, which then fail in
amd_pmu_{get,set}_msr(), injecting an errant #GP instead of taking
KVM's fallback (read 0, write ignored) and breaking migration for
unadvertised counters.

Finally, the range check in the default case is dead code because AMD
CPUs currently support at most 6 Core Perf counters. Even if future AMD
CPUs support more than 6, counter MSRs would still be sufficiently
validated by amd_msr_idx_to_pmc().

Drop the counter cases and dead range check from amd_is_valid_msr(),
leaving counter validation solely to amd_msr_idx_to_pmc().

Fixes: 4a2771895ca6 ("KVM: x86/svm/pmu: Add AMD PerfMonV2 support")
Reported-by: Jim Mattson <jmattson@google.com>
Signed-off-by: Zide Chen <zide.chen@intel.com>
---
v4:
- New patch. (Jim)
---
 arch/x86/kvm/svm/pmu.c | 9 +--------
 1 file changed, 1 insertion(+), 8 deletions(-)

diff --git a/arch/x86/kvm/svm/pmu.c b/arch/x86/kvm/svm/pmu.c
index c18286545a7a..bf2f23c30afc 100644
--- a/arch/x86/kvm/svm/pmu.c
+++ b/arch/x86/kvm/svm/pmu.c
@@ -106,23 +106,16 @@ static bool amd_is_valid_msr(struct kvm_vcpu *vcpu, u32 msr)
 	struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
 
 	switch (msr) {
-	case MSR_K7_EVNTSEL0 ... MSR_K7_PERFCTR3:
-		return pmu->version > 0;
-	case MSR_F15H_PERF_CTL0 ... MSR_F15H_PERF_CTR5:
-		return guest_cpu_cap_has(vcpu, X86_FEATURE_PERFCTR_CORE);
 	case MSR_AMD64_PERF_CNTR_GLOBAL_STATUS:
 	case MSR_AMD64_PERF_CNTR_GLOBAL_CTL:
 	case MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_CLR:
 	case MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_SET:
 		return pmu->version > 1;
 	default:
-		if (msr > MSR_F15H_PERF_CTR5 &&
-		    msr < MSR_F15H_PERF_CTL0 + 2 * pmu->nr_arch_gp_counters)
-			return pmu->version > 1;
 		break;
 	}
 
-	return amd_msr_idx_to_pmc(vcpu, msr);
+	return false;
 }
 
 static int amd_pmu_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
-- 
2.56.1