Re: [PATCH v3 7/9] perf/x86/intel: KVM: Handle cross-mapped PEBS PMCs entirely within KVM

["Mi, Dapeng" <dapeng1.mi@linux.intel.com>]

On 5/9/2026 7:13 AM, Sean Christopherson wrote:
> Now that perf operates on a KVM-provided snapshot of PMU state, handled
> cross-mapped PEBS counters entirely in KVM by clearing unusable counters
> from the to-be-enabled mask instead of foisting the work on perf.
>
> No functional change intended.
>
> Signed-off-by: Sean Christopherson <seanjc@google.com>
> ---
>  arch/x86/events/intel/core.c      |  8 --------
>  arch/x86/include/asm/perf_event.h |  1 -
>  arch/x86/kvm/vmx/vmx.c            | 10 ++++++++--
>  3 files changed, 8 insertions(+), 11 deletions(-)
>
> diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
> index e9acfc3f3a82..8f6be0cc4c4b 100644
> --- a/arch/x86/events/intel/core.c
> +++ b/arch/x86/events/intel/core.c
> @@ -5053,14 +5053,6 @@ static struct perf_guest_switch_msr *intel_guest_get_msrs(int *nr,
>  			  ~cpuc->intel_ctrl_exclude_guest_mask &
>  			  cpuc->intel_ctrl_exclude_host_mask;
>  
> -	/*
> -	 * Disable counters where the guest PMC is different than the host PMC
> -	 * being used on behalf of the guest, as the PEBS record includes
> -	 * PERF_GLOBAL_STATUS, i.e. the guest will see overflow status for the
> -	 * wrong counter(s).
> -	 */
> -	guest_pebs_mask &= ~guest_pebs->cross_mapped_mask;
> -
>  	/*
>  	 * FIXME: Allow guest and host usage of PEBS events to co-exist instead
>  	 *        of disabling guest PEBS entirely if the host is using PEBS.
> diff --git a/arch/x86/include/asm/perf_event.h b/arch/x86/include/asm/perf_event.h
> index bc7e48f6f4a8..19f874a79ab0 100644
> --- a/arch/x86/include/asm/perf_event.h
> +++ b/arch/x86/include/asm/perf_event.h
> @@ -790,7 +790,6 @@ struct x86_guest_pebs {
>  	u64	enable;
>  	u64	ds_area;
>  	u64	data_cfg;
> -	u64	cross_mapped_mask;
>  };
>  #if defined(CONFIG_PERF_EVENTS) && defined(CONFIG_CPU_SUP_INTEL)
>  extern struct perf_guest_switch_msr *perf_guest_get_msrs(int *nr,
> diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c
> index 9f0a028cf10b..fbe3ce5f5a51 100644
> --- a/arch/x86/kvm/vmx/vmx.c
> +++ b/arch/x86/kvm/vmx/vmx.c
> @@ -7319,8 +7319,14 @@ static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
>  		.data_cfg = pmu->pebs_data_cfg,
>  	};
>  
> -	if (pmu->pebs_enable & pmu->global_ctrl)
> -		guest_pebs.cross_mapped_mask = intel_pmu_get_cross_mapped_mask(pmu);
> +	/*
> +	 * Disable counters where the guest PMC is different than the host PMC
> +	 * being used on behalf of the guest, as the PEBS record includes
> +	 * PERF_GLOBAL_STATUS, i.e. the guest will see overflow status for the
> +	 * wrong counter(s).
> +	 */
> +	if (guest_pebs.enable & pmu->global_ctrl)
> +		guest_pebs.enable &= ~intel_pmu_get_cross_mapped_mask(pmu);
>  
>  	/* Note, nr_msrs may be garbage if perf_guest_get_msrs() returns NULL. */
>  	msrs = perf_guest_get_msrs(&nr_msrs, &guest_pebs);

LGTM.

Reviewed-by: Dapeng Mi <dapeng1.mi@linux.intel.com>