From: Paolo Bonzini <pbonzini@redhat.com>
To: Luwei Kang <luwei.kang@intel.com>, kvm@vger.kernel.org
Cc: rkrcmar@redhat.com, tglx@linutronix.de, mingo@redhat.com,
hpa@zytor.com, x86@kernel.org, linux-kernel@vger.kernel.org,
Chao Peng <chao.p.peng@linux.intel.com>
Subject: Re: [patch v2 6/8] KVM: x86: Implement Intel processor trace context switch
Date: Mon, 13 Nov 2017 17:01:36 +0100 [thread overview]
Message-ID: <77e7451c-1e1a-7332-08c2-a5fe8ab930e3@redhat.com> (raw)
In-Reply-To: <1509401117-15521-7-git-send-email-luwei.kang@intel.com>
On 30/10/2017 23:05, Luwei Kang wrote:
> +static void pt_guest_enter(struct vcpu_vmx *vmx)
> +{
> + u64 ctl;
> +
> + if (pt_mode == PT_MODE_HOST || pt_mode == PT_MODE_HOST_GUEST) {
> + rdmsrl(MSR_IA32_RTIT_CTL, ctl);
> + vmx->pt_desc.host.ctl = ctl;
> + if (ctl & RTIT_CTL_TRACEEN) {
> + ctl &= ~RTIT_CTL_TRACEEN;
> + wrmsrl(MSR_IA32_RTIT_CTL, ctl);
> + }
This "if" is only needed for PT_MODE_HOST_GUEST, I believe.
PT_MODE_HOST can just use the "load RTIT_CTL" vmentry control to disable
tracing.
> + }
> +
> + if (pt_mode == PT_MODE_HOST_GUEST) {
> + pt_save_msr(&vmx->pt_desc.host, vmx->pt_desc.addr_num);
> + pt_load_msr(&vmx->pt_desc.guest, vmx->pt_desc.addr_num);
> + }
> +}
> +
> +static void pt_guest_exit(struct vcpu_vmx *vmx)
> +{
> + if (pt_mode == PT_MODE_HOST_GUEST) {
> + pt_save_msr(&vmx->pt_desc.guest, vmx->pt_desc.addr_num);
> + pt_load_msr(&vmx->pt_desc.host, vmx->pt_desc.addr_num);
> + wrmsrl(MSR_IA32_RTIT_CTL, vmx->pt_desc.host.ctl);
> + }
> +
> + if (pt_mode == PT_MODE_HOST)
> + wrmsrl(MSR_IA32_RTIT_CTL, vmx->pt_desc.host.ctl);
> +}
Please use an
if (pt_mode == PT_MODE_HOST || pt_mode == PT_MODE_HOST_GUEST)
for the write to RTIT_CTL, so that pt_guest_exit mirrors pt_guest_entry.
Also, we don't actually need to write the MSR if RTIT_CTL_TRACEEN is
false. With these changes, the cost of the "host-only" mode is
acceptable, but for host-guest mode it is very expensive to read and
write the MSRs on all vmentries and vmexits is very expensive.
It would be much better to avoid writing the guest state if the guest
RTIT_CTL has TRACEEN=0. This would require keeping the intercepts until
TRACEEN=1, but a lot of the work would be needed anyway---see my review
of patch 7.
Thanks,
Paolo
next prev parent reply other threads:[~2017-11-13 16:01 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-10-30 22:05 [patch v2 0/8] Intel Processor Trace virtulization enabling Luwei Kang
2017-10-30 22:05 ` [patch v2 1/8] perf/x86/intel/pt: Move Intel-PT MSR bit definitions to a public header Luwei Kang
2017-10-30 22:05 ` [patch v2 2/8] perf/x86/intel/pt: change pt_cap_get() to a public function Luwei Kang
2017-10-30 22:05 ` [patch v2 3/8] KVM: x86: add Intel processor trace virtualization mode Luwei Kang
2017-11-13 16:29 ` Paolo Bonzini
2017-11-14 7:11 ` Kang, Luwei
2017-11-13 16:32 ` Paolo Bonzini
2017-11-14 7:31 ` Kang, Luwei
2017-11-14 10:47 ` Paolo Bonzini
2017-10-30 22:05 ` [patch v2 4/8] KVM: x86: add Intel processor trace cpuid emulataion Luwei Kang
2017-11-13 15:36 ` Paolo Bonzini
2017-11-14 2:56 ` Kang, Luwei
2017-10-30 22:05 ` [patch v2 5/8] KVM: x86: add Intel processor trace context for each vcpu Luwei Kang
2017-10-30 22:05 ` [patch v2 6/8] KVM: x86: Implement Intel processor trace context switch Luwei Kang
2017-11-13 16:01 ` Paolo Bonzini [this message]
2017-10-30 22:05 ` [patch v2 7/8] KVM: x86: add Intel PT msr RTIT_CTL read/write Luwei Kang
2017-11-13 16:22 ` Paolo Bonzini
2017-11-14 6:59 ` Kang, Luwei
2017-11-14 10:34 ` Paolo Bonzini
2017-10-30 22:05 ` [patch v2 8/8] KVM: x86: Disable intercept for Intel processor trace MSRs Luwei Kang
2017-11-13 16:24 ` Paolo Bonzini
2017-11-14 7:01 ` Kang, Luwei
2017-11-02 14:57 ` [patch v2 0/8] Intel Processor Trace virtulization enabling Paolo Bonzini
2017-11-03 6:09 ` Kang, Luwei
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