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From: Paolo Bonzini <pbonzini@redhat.com>
To: Andy Lutomirski <luto@amacapital.net>
Cc: kvm list <kvm@vger.kernel.org>,
	linux-kernel@vger.kernel.org, X86 ML <x86@kernel.org>,
	"H. Peter Anvin" <hpa@zytor.com>,
	Borislav Petkov <bpetkov@suse.de>
Subject: Re: RFC: Getting rid of LTR in VMX
Date: Mon, 20 Feb 2017 17:02:53 -0500 (EST)	[thread overview]
Message-ID: <890292613.23897064.1487628173163.JavaMail.zimbra@redhat.com> (raw)
In-Reply-To: <CALCETrW6sVVQN1DfMvKMpU9u=bpOeS7WZVfwNPYqPqEiysXjFg@mail.gmail.com>


> > Yes.  But 150-200 clock cycles are nothing compared to the cache misses
> > you get from preemption, so I'd ignore that.  Saving 300 clock cycles on
> > userspace exits from TR+GSBASE would be about 5% on my Haswell.
> 
> That's still 5% :)

Yes, 5% on userspace exits is good (though they're rare).

OTOH, 300 clock cycles on preemption are nothing to write home about.

Paolo

  reply	other threads:[~2017-02-20 22:02 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-02-18  3:29 RFC: Getting rid of LTR in VMX Andy Lutomirski
2017-02-18 15:19 ` Paolo Bonzini
2017-02-20 11:05 ` Paolo Bonzini
2017-02-20 16:46   ` Andy Lutomirski
2017-02-20 16:51     ` Paolo Bonzini
2017-02-20 16:55       ` Andy Lutomirski
2017-02-20 22:02         ` Paolo Bonzini [this message]
2017-02-20 22:23           ` hpa

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