From: "Chen, Zide" <zide.chen@intel.com>
To: Jim Mattson <jmattson@google.com>
Cc: Sean Christopherson <seanjc@google.com>,
Paolo Bonzini <pbonzini@redhat.com>,
Peter Zijlstra <peterz@infradead.org>,
kvm@vger.kernel.org, linux-kernel@vger.kernel.org,
Mingwei Zhang <mizhang@google.com>,
Das Sandipan <Sandipan.Das@amd.com>,
Shukla Manali <Manali.Shukla@amd.com>,
Dapeng Mi <dapeng1.mi@linux.intel.com>,
Falcon Thomas <thomas.falcon@intel.com>,
Xudong Hao <xudong.hao@intel.com>
Subject: Re: [PATCH 14/15] KVM: x86/pmu: Advertise PerfMon version 5 on Intel hosts
Date: Fri, 24 Jul 2026 09:19:19 -0500 [thread overview]
Message-ID: <a852a4ef-719f-4a4e-aae7-83d365189494@intel.com> (raw)
In-Reply-To: <CALMp9eSd2TBixRrRTqfam8LFVG4__fy_H6XVa9Q_-kEdXoxe6w@mail.gmail.com>
On 7/23/2026 10:20 PM, Jim Mattson wrote:
> On Thu, Jul 23, 2026 at 4:25 PM Chen, Zide <zide.chen@intel.com> wrote:
>>
>> Currently KVM always injects #GP when the AnyThread bit is set.
>>
>> kvm_pmu_refresh(): pmu->reserved_bits = 0xffffffff00200000ull;
>>
>> I understand the concern, but I'm not aware of a better solution for
>> PMUv3/4. Silently ignoring AnyThread would deviate from the
>> architectural behavior and, more importantly, may give the guest the
>> false impression that AnyThread is supported. Supporting AnyThread, on
>> the other hand, has cross-VM information leakage concerns.
>
> Don't support versions 3 or 4; they aren't virtualizable. Hosts with
> PMU versions 3 or 4 just get vPMU version 2.
Yes, that sounds reasonable.
PMUv3/v4 platforms (Nehalem, Westmere, Sandy Bridge, and Ivy Bridge) are
quite old. In addition, the impact of exposing PMUv2 instead of PMUv3/v4
should be minimal.
next prev parent reply other threads:[~2026-07-24 14:19 UTC|newest]
Thread overview: 31+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-07-07 18:33 [PATCH 00/15] KVM: x86/pmu: Add mediated vPMU PerfMon v5 support Zide Chen
2026-07-07 18:33 ` [PATCH 01/15] KVM: x86/pmu: Remove redundant Perf Global Status MSR bit definitions Zide Chen
2026-07-07 18:33 ` [PATCH 02/15] KVM: x86/pmu: Rename all_valid_pmc_idx to all_valid_pmc_mask Zide Chen
2026-07-28 19:11 ` Sean Christopherson
2026-07-28 19:51 ` Chen, Zide
2026-07-07 18:33 ` [PATCH 03/15] KVM: x86/pmu: Rename reserved_bits to eventsel_rsvd in kvm_pmu Zide Chen
2026-07-07 18:33 ` [PATCH 04/15] KVM: x86/pmu: Add PMC bitmap accessor helpers Zide Chen
2026-07-28 19:28 ` Sean Christopherson
2026-07-28 20:42 ` Chen, Zide
2026-07-28 23:35 ` Sean Christopherson
2026-07-07 18:33 ` [PATCH 05/15] KVM: x86/pmu: Drop nr_arch_{gp,fixed}_counters from kvm_pmu Zide Chen
2026-07-07 18:33 ` [PATCH 06/15] KVM: x86/pmu: Expose kvm_host_pmu to vendor modules Zide Chen
2026-07-07 18:33 ` [PATCH 07/15] perf/x86: Plumb counter bitmap from x86_pmu to x86_pmu_cap Zide Chen
2026-07-07 18:33 ` [PATCH 08/15] KVM: x86/pmu: Switch to bitmask-based KVM PMU capabilities Zide Chen
2026-07-23 21:47 ` Jim Mattson
2026-07-24 15:15 ` Chen, Zide
2026-07-07 18:33 ` [PATCH 09/15] perf/x86: Remove num_counters_{gp,fixed} from x86_pmu_capability Zide Chen
2026-07-23 21:49 ` Jim Mattson
2026-07-24 15:52 ` Chen, Zide
2026-07-07 18:34 ` [PATCH 10/15] KVM: x86/pmu: Emulate the GLOBAL_STATUS_SET and GLOBAL_INUSE MSRs Zide Chen
2026-07-07 18:34 ` [PATCH 11/15] KVM: x86/pmu: Emulate streamlined Freeze-LBR-on-PMI Zide Chen
2026-07-28 19:33 ` Sean Christopherson
2026-07-28 19:48 ` Chen, Zide
2026-07-07 18:34 ` [PATCH 12/15] KVM: x86/pmu: Populate CPUID.0AH:ECX fixed-counter bitmap Zide Chen
2026-07-07 18:34 ` [PATCH 13/15] KVM: x86/pmu: Ignore AnyThread bit if CPUID.0AH:EDX[15] is not set Zide Chen
2026-07-07 18:34 ` [PATCH 14/15] KVM: x86/pmu: Advertise PerfMon version 5 on Intel hosts Zide Chen
2026-07-23 21:53 ` Jim Mattson
2026-07-23 23:25 ` Chen, Zide
2026-07-24 3:20 ` Jim Mattson
2026-07-24 14:19 ` Chen, Zide [this message]
2026-07-07 18:34 ` [PATCH 15/15] KVM: selftests: Support fixed counters bitmap in pmu_counters_test Zide Chen
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