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From: Marc Zyngier <maz@kernel.org>
To: kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org,
	kvm@vger.kernel.org
Cc: Joey Gouly <joey.gouly@arm.com>,
	Suzuki K Poulose <suzuki.poulose@arm.com>,
	Oliver Upton <oliver.upton@linux.dev>,
	Zenghui Yu <yuzenghui@huawei.com>,
	Andre Przywara <andre.przywara@arm.com>,
	Eric Auger <eric.auger@redhat.com>
Subject: [PATCH v2 05/17] KVM: arm64: nv: Load timer before the GIC
Date: Sun, 12 Jan 2025 17:08:33 +0000	[thread overview]
Message-ID: <20250112170845.1181891-6-maz@kernel.org> (raw)
In-Reply-To: <20250112170845.1181891-1-maz@kernel.org>

In order for vgic_v3_load_nested to be able to observe which timer
interrupts have the HW bit set for the current context, the timers
must have been loaded in the new mode and the right timer mapped
to their corresponding HW IRQs.

At the moment, we load the GIC first, meaning that timer interrupts
injected to an L2 guest will never have the HW bit set (we see the
old configuration).

Swapping the two loads solves this particular problem.

Signed-off-by: Marc Zyngier <maz@kernel.org>
---
 arch/arm64/kvm/arm.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm64/kvm/arm.c b/arch/arm64/kvm/arm.c
index a102c3aebdbc4..3115c44ed4042 100644
--- a/arch/arm64/kvm/arm.c
+++ b/arch/arm64/kvm/arm.c
@@ -596,8 +596,8 @@ void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
 
 	vcpu->cpu = cpu;
 
-	kvm_vgic_load(vcpu);
 	kvm_timer_vcpu_load(vcpu);
+	kvm_vgic_load(vcpu);
 	if (has_vhe())
 		kvm_vcpu_load_vhe(vcpu);
 	kvm_arch_vcpu_load_fp(vcpu);
-- 
2.39.2


  parent reply	other threads:[~2025-01-12 17:08 UTC|newest]

Thread overview: 21+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-01-12 17:08 [PATCH v2 00/17] KVM: arm64: Add NV GICv3 support Marc Zyngier
2025-01-12 17:08 ` [PATCH v2 01/17] arm64: sysreg: Add layout for ICH_HCR_EL2 Marc Zyngier
2025-01-15 18:39   ` Andre Przywara
2025-01-12 17:08 ` [PATCH v2 02/17] arm64: sysreg: Add layout for ICH_VTR_EL2 Marc Zyngier
2025-01-15 18:40   ` Andre Przywara
2025-01-12 17:08 ` [PATCH v2 03/17] arm64: sysreg: Add layout for ICH_MISR_EL2 Marc Zyngier
2025-01-15 18:41   ` Andre Przywara
2025-01-12 17:08 ` [PATCH v2 04/17] KVM: arm64: Move host SVE/SME state flags out of vCPU Marc Zyngier
2025-01-12 17:08 ` Marc Zyngier [this message]
2025-01-12 17:08 ` [PATCH v2 06/17] KVM: arm64: nv: Add ICH_*_EL2 registers to vpcu_sysreg Marc Zyngier
2025-01-12 17:08 ` [PATCH v2 07/17] KVM: arm64: nv: Plumb handling of GICv3 EL2 accesses Marc Zyngier
2025-01-12 17:08 ` [PATCH v2 08/17] KVM: arm64: nv: Sanitise ICH_HCR_EL2 accesses Marc Zyngier
2025-01-12 17:08 ` [PATCH v2 09/17] KVM: arm64: nv: Nested GICv3 emulation Marc Zyngier
2025-01-12 17:08 ` [PATCH v2 10/17] KVM: arm64: nv: Handle L2->L1 transition on interrupt injection Marc Zyngier
2025-01-12 17:08 ` [PATCH v2 11/17] KVM: arm64: nv: Add Maintenance Interrupt emulation Marc Zyngier
2025-01-12 17:08 ` [PATCH v2 12/17] KVM: arm64: nv: Respect virtual HCR_EL2.TWx setting Marc Zyngier
2025-01-12 17:08 ` [PATCH v2 13/17] KVM: arm64: nv: Request vPE doorbell upon nested ERET to L2 Marc Zyngier
2025-01-12 17:08 ` [PATCH v2 14/17] KVM: arm64: nv: Propagate used_lrs between L1 and L0 contexts Marc Zyngier
2025-01-12 17:08 ` [PATCH v2 15/17] KVM: arm64: nv: Fold GICv3 host trapping requirements into guest setup Marc Zyngier
2025-01-12 17:08 ` [PATCH v2 16/17] KVM: arm64: nv: Allow userland to set VGIC maintenance IRQ Marc Zyngier
2025-01-12 17:08 ` [PATCH v2 17/17] KVM: arm64: nv: Fail KVM init if asking for NV without GICv3 Marc Zyngier

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