From: Oliver Upton <oliver.upton@linux.dev>
To: kvmarm@lists.linux.dev
Cc: Marc Zyngier <maz@kernel.org>, Joey Gouly <joey.gouly@arm.com>,
Suzuki K Poulose <suzuki.poulose@arm.com>,
Sebastian Ott <sebott@redhat.com>,
Oliver Upton <oliver.upton@linux.dev>
Subject: [PATCH v4 2/5] KVM: arm64: Maintain per-VM copy of implementation ID regs
Date: Mon, 24 Feb 2025 16:53:58 -0800 [thread overview]
Message-ID: <20250225005401.679536-3-oliver.upton@linux.dev> (raw)
In-Reply-To: <20250225005401.679536-1-oliver.upton@linux.dev>
From: Sebastian Ott <sebott@redhat.com>
Get ready to allow changes to the implementation ID registers by
tracking the VM-wide values.
Signed-off-by: Sebastian Ott <sebott@redhat.com>
Signed-off-by: Oliver Upton <oliver.upton@linux.dev>
---
arch/arm64/include/asm/kvm_host.h | 9 +++++++
arch/arm64/kvm/sys_regs.c | 43 ++++++++++++++++---------------
2 files changed, 31 insertions(+), 21 deletions(-)
diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm_host.h
index 7cfa024de4e3..bc5e8a5620ac 100644
--- a/arch/arm64/include/asm/kvm_host.h
+++ b/arch/arm64/include/asm/kvm_host.h
@@ -373,6 +373,9 @@ struct kvm_arch {
#define KVM_ARM_ID_REG_NUM (IDREG_IDX(sys_reg(3, 0, 0, 7, 7)) + 1)
u64 id_regs[KVM_ARM_ID_REG_NUM];
+ u64 midr_el1;
+ u64 revidr_el1;
+ u64 aidr_el1;
u64 ctr_el0;
/* Masks for VNCR-backed and general EL2 sysregs */
@@ -1471,6 +1474,12 @@ static inline u64 *__vm_id_reg(struct kvm_arch *ka, u32 reg)
return &ka->id_regs[IDREG_IDX(reg)];
case SYS_CTR_EL0:
return &ka->ctr_el0;
+ case SYS_MIDR_EL1:
+ return &ka->midr_el1;
+ case SYS_REVIDR_EL1:
+ return &ka->revidr_el1;
+ case SYS_AIDR_EL1:
+ return &ka->aidr_el1;
default:
WARN_ON_ONCE(1);
return NULL;
diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
index f25a157622e3..de66ffab3a2b 100644
--- a/arch/arm64/kvm/sys_regs.c
+++ b/arch/arm64/kvm/sys_regs.c
@@ -1653,15 +1653,24 @@ static bool is_feature_id_reg(u32 encoding)
* Return true if the register's (Op0, Op1, CRn, CRm, Op2) is
* (3, 0, 0, crm, op2), where 1<=crm<8, 0<=op2<8, which is the range of ID
* registers KVM maintains on a per-VM basis.
+ *
+ * Additionally, the implementation ID registers and CTR_EL0 are handled as
+ * per-VM registers.
*/
static inline bool is_vm_ftr_id_reg(u32 id)
{
- if (id == SYS_CTR_EL0)
+ switch (id) {
+ case SYS_CTR_EL0:
+ case SYS_MIDR_EL1:
+ case SYS_REVIDR_EL1:
+ case SYS_AIDR_EL1:
return true;
+ default:
+ return (sys_reg_Op0(id) == 3 && sys_reg_Op1(id) == 0 &&
+ sys_reg_CRn(id) == 0 && sys_reg_CRm(id) >= 1 &&
+ sys_reg_CRm(id) < 8);
- return (sys_reg_Op0(id) == 3 && sys_reg_Op1(id) == 0 &&
- sys_reg_CRn(id) == 0 && sys_reg_CRm(id) >= 1 &&
- sys_reg_CRm(id) < 8);
+ }
}
static inline bool is_vcpu_ftr_id_reg(u32 id)
@@ -2530,36 +2539,27 @@ static void init_imp_id_regs(void)
boot_cpu_aidr_val = read_sysreg(aidr_el1);
}
-static int get_imp_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r,
- u64 *val)
+static u64 reset_imp_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
{
switch (reg_to_encoding(r)) {
case SYS_MIDR_EL1:
- *val = boot_cpu_midr_val;
- break;
+ return boot_cpu_midr_val;
case SYS_REVIDR_EL1:
- *val = boot_cpu_revidr_val;
- break;
+ return boot_cpu_revidr_val;
case SYS_AIDR_EL1:
- *val = boot_cpu_aidr_val;
- break;
+ return boot_cpu_aidr_val;
default:
- WARN_ON_ONCE(1);
- return -EINVAL;
+ KVM_BUG_ON(1, vcpu->kvm);
+ return 0;
}
-
- return 0;
}
static int set_imp_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r,
u64 val)
{
u64 expected;
- int ret;
- ret = get_imp_id_reg(vcpu, r, &expected);
- if (ret)
- return ret;
+ expected = read_id_reg(vcpu, r);
return (expected == val) ? 0 : -EINVAL;
}
@@ -2567,8 +2567,9 @@ static int set_imp_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r,
#define IMPLEMENTATION_ID(reg) { \
SYS_DESC(SYS_##reg), \
.access = access_imp_id_reg, \
- .get_user = get_imp_id_reg, \
+ .get_user = get_id_reg, \
.set_user = set_imp_id_reg, \
+ .reset = reset_imp_id_reg, \
}
/*
--
2.39.5
next prev parent reply other threads:[~2025-02-25 0:54 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-02-25 0:53 [PATCH v4 0/5] KVM: arm64: Writable MIDR/REVIDR (and associated baggage) Oliver Upton
2025-02-25 0:53 ` [PATCH v4 1/5] KVM: arm64: Set HCR_EL2.TID1 unconditionally Oliver Upton
2025-02-25 11:09 ` Marc Zyngier
2025-02-25 0:53 ` Oliver Upton [this message]
2025-02-25 0:53 ` [PATCH v4 3/5] KVM: arm64: Load VPIDR_EL2 with the VM's MIDR_EL1 value Oliver Upton
2025-02-25 0:54 ` [PATCH v4 4/5] KVM: arm64: Allow userspace to change the implementation ID registers Oliver Upton
2025-02-25 11:19 ` Marc Zyngier
2025-02-25 0:54 ` [PATCH v4 5/5] KVM: selftests: arm64: Test writes to MIDR,REVIDR,AIDR Oliver Upton
2025-02-27 20:39 ` Mark Brown
2025-02-28 9:47 ` Sebastian Ott
2025-02-28 13:21 ` Sebastian Ott
2025-02-25 13:54 ` [PATCH v4 0/5] KVM: arm64: Writable MIDR/REVIDR (and associated baggage) Marc Zyngier
2025-02-26 9:49 ` Oliver Upton
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