From: Marc Zyngier <maz@kernel.org>
To: Oliver Upton <oliver.upton@linux.dev>
Cc: kvmarm@lists.linux.dev, Joey Gouly <joey.gouly@arm.com>,
Suzuki K Poulose <suzuki.poulose@arm.com>,
Sebastian Ott <sebott@redhat.com>
Subject: Re: [PATCH v4 0/5] KVM: arm64: Writable MIDR/REVIDR (and associated baggage)
Date: Tue, 25 Feb 2025 13:54:12 +0000 [thread overview]
Message-ID: <86eczmqge3.wl-maz@kernel.org> (raw)
In-Reply-To: <20250225005401.679536-1-oliver.upton@linux.dev>
On Tue, 25 Feb 2025 00:53:56 +0000,
Oliver Upton <oliver.upton@linux.dev> wrote:
>
> This is hopefully the last take on the writable MIDR/REVIDR/AIDR series.
>
> I've restructured things in order to work around the existing
> shortcomings, have a stable-worthy backport for SMIDR_EL1, and avoid
> breaking ABI.
>
> I personally hate using a capability for this, but given the subtlety of
> the issue (and our habit of breaking save/restore) it is probably best
> to put userspace in the driver's seat.
>
> v3: https://lore.kernel.org/kvmarm/20250218163443.32836-1-sebott@redhat.com/
>
> v3 -> v4:
> - Trap SMIDR_EL1 accesses so they actually UNDEF
> - Snapshot MIDR, REVIDR, and AIDR from the boot CPU
> - Require buy-in from userspace to make ID registers writable
Here's what I added to the series in order to handle AIDR/REVIDR. Not
exactly pretty, but it does the job (tested on my Synquacker running a
hand-crafted guest).
Feel free to squash it into patch #1.
Thanks,
M.
From: Marc Zyngier <maz@kernel.org>
Date: Tue, 25 Feb 2025 13:46:55 +0000
Subject: [PATCH] KVM: arm64: Map AArch32 AIDR/REVIDR to their AArch64
counterpart
In order to handle AIDR/REVIDR traps from an AArch32 guest, add
some ugly handling to kvm_handle_cp15_32().
Signed-off-by: Marc Zyngier <maz@kernel.org>
---
arch/arm64/kvm/sys_regs.c | 8 ++++++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
index c1727fe6c8cb0..1ceaec61796c9 100644
--- a/arch/arm64/kvm/sys_regs.c
+++ b/arch/arm64/kvm/sys_regs.c
@@ -4398,9 +4398,13 @@ int kvm_handle_cp15_32(struct kvm_vcpu *vcpu)
* Certain AArch32 ID registers are handled by rerouting to the AArch64
* system register table. Registers in the ID range where CRm=0 are
* excluded from this scheme as they do not trivially map into AArch64
- * system register encodings.
+ * system register encodings, except for AIDR/REVIDR.
*/
- if (params.Op1 == 0 && params.CRn == 0 && params.CRm)
+ if (params.Op1 == 0 && params.CRn == 0 &&
+ (params.CRm || params.Op2 == 6 /* REVIDR */))
+ return kvm_emulate_cp15_id_reg(vcpu, ¶ms);
+ if (params.Op1 == 1 && params.CRn == 0 &&
+ params.CRm == 0 && params.Op2 == 7 /* AIDR */)
return kvm_emulate_cp15_id_reg(vcpu, ¶ms);
return kvm_handle_cp_32(vcpu, ¶ms, cp15_regs, ARRAY_SIZE(cp15_regs));
--
2.39.2
--
Without deviation from the norm, progress is not possible.
next prev parent reply other threads:[~2025-02-25 13:54 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-02-25 0:53 [PATCH v4 0/5] KVM: arm64: Writable MIDR/REVIDR (and associated baggage) Oliver Upton
2025-02-25 0:53 ` [PATCH v4 1/5] KVM: arm64: Set HCR_EL2.TID1 unconditionally Oliver Upton
2025-02-25 11:09 ` Marc Zyngier
2025-02-25 0:53 ` [PATCH v4 2/5] KVM: arm64: Maintain per-VM copy of implementation ID regs Oliver Upton
2025-02-25 0:53 ` [PATCH v4 3/5] KVM: arm64: Load VPIDR_EL2 with the VM's MIDR_EL1 value Oliver Upton
2025-02-25 0:54 ` [PATCH v4 4/5] KVM: arm64: Allow userspace to change the implementation ID registers Oliver Upton
2025-02-25 11:19 ` Marc Zyngier
2025-02-25 0:54 ` [PATCH v4 5/5] KVM: selftests: arm64: Test writes to MIDR,REVIDR,AIDR Oliver Upton
2025-02-27 20:39 ` Mark Brown
2025-02-28 9:47 ` Sebastian Ott
2025-02-28 13:21 ` Sebastian Ott
2025-02-25 13:54 ` Marc Zyngier [this message]
2025-02-26 9:49 ` [PATCH v4 0/5] KVM: arm64: Writable MIDR/REVIDR (and associated baggage) Oliver Upton
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