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From: Oliver Upton <oupton@kernel.org>
To: kvmarm@lists.linux.dev
Cc: Marc Zyngier <maz@kernel.org>, Joey Gouly <joey.gouly@arm.com>,
	Suzuki K Poulose <suzuki.poulose@arm.com>,
	Zenghui Yu <yuzenghui@huawei.com>,
	Oliver Upton <oupton@kernel.org>
Subject: [PATCH v2 12/14] KVM: arm64: nv: Implement HW access flag management in stage-2 SW PTW
Date: Mon, 17 Nov 2025 14:43:23 -0800	[thread overview]
Message-ID: <20251117224325.2431848-13-oupton@kernel.org> (raw)
In-Reply-To: <20251117224325.2431848-1-oupton@kernel.org>

Give the stage-2 walk similar treatment to stage-1: update the access
flag during the table walk and do so for any walk context.

Signed-off-by: Oliver Upton <oupton@kernel.org>
---
 arch/arm64/kvm/mmu.c    |  3 +++
 arch/arm64/kvm/nested.c | 48 ++++++++++++++++++++++++++++++++++-------
 2 files changed, 43 insertions(+), 8 deletions(-)

diff --git a/arch/arm64/kvm/mmu.c b/arch/arm64/kvm/mmu.c
index 96f1786c72fe..b23d3dc8865e 100644
--- a/arch/arm64/kvm/mmu.c
+++ b/arch/arm64/kvm/mmu.c
@@ -2012,6 +2012,9 @@ int kvm_handle_guest_abort(struct kvm_vcpu *vcpu)
 		u32 esr;
 
 		ret = kvm_walk_nested_s2(vcpu, fault_ipa, &nested_trans);
+		if (ret == -EAGAIN)
+			return 1;
+
 		if (ret) {
 			esr = kvm_s2_trans_esr(&nested_trans);
 			kvm_inject_s2_fault(vcpu, esr);
diff --git a/arch/arm64/kvm/nested.c b/arch/arm64/kvm/nested.c
index b2fb3d7c9c19..5921b66279b8 100644
--- a/arch/arm64/kvm/nested.c
+++ b/arch/arm64/kvm/nested.c
@@ -124,13 +124,14 @@ int kvm_vcpu_init_nested(struct kvm_vcpu *vcpu)
 }
 
 struct s2_walk_info {
-	void	     *data;
-	u64	     baddr;
-	unsigned int max_oa_bits;
-	unsigned int pgshift;
-	unsigned int sl;
-	unsigned int t0sz;
-	bool	     be;
+	void		*data;
+	u64		baddr;
+	unsigned int	max_oa_bits;
+	unsigned int	pgshift;
+	unsigned int	sl;
+	unsigned int	t0sz;
+	bool		be;
+	bool		ha;
 };
 
 static u32 compute_fsc(int level, u32 fsc)
@@ -220,6 +221,22 @@ static int read_guest_s2_desc(phys_addr_t pa, u64 *desc, struct s2_walk_info *wi
 	return 0;
 }
 
+static int swap_guest_s2_desc(phys_addr_t pa, u64 old, u64 new,
+			      struct s2_walk_info *wi)
+{
+	struct kvm_vcpu *vcpu = wi->data;
+
+	if (wi->be) {
+		old = cpu_to_be64(old);
+		new = cpu_to_be64(new);
+	} else {
+		old = cpu_to_le64(old);
+		new = cpu_to_le64(new);
+	}
+
+	return __kvm_at_swap_desc(vcpu->kvm, pa, old, new);
+}
+
 /*
  * This is essentially a C-version of the pseudo code from the ARM ARM
  * AArch64.TranslationTableWalk  function.  I strongly recommend looking at
@@ -233,7 +250,7 @@ static int walk_nested_s2_pgd(phys_addr_t ipa,
 	int first_block_level, level, stride, input_size, base_lower_bound;
 	phys_addr_t base_addr;
 	unsigned int addr_top, addr_bottom;
-	u64 desc;  /* page table entry */
+	u64 desc, new_desc;  /* page table entry */
 	int ret;
 	phys_addr_t paddr;
 
@@ -282,6 +299,8 @@ static int walk_nested_s2_pgd(phys_addr_t ipa,
 		if (ret < 0)
 			return ret;
 
+		new_desc = desc;
+
 		/* Check for valid descriptor at this point */
 		if (!(desc & KVM_PTE_VALID)) {
 			out->esr = compute_fsc(level, ESR_ELx_FSC_FAULT);
@@ -326,6 +345,17 @@ static int walk_nested_s2_pgd(phys_addr_t ipa,
 		return 1;
 	}
 
+	if (wi->ha)
+		new_desc |= KVM_PTE_LEAF_ATTR_LO_S2_AF;
+
+	if (new_desc != desc) {
+		ret = swap_guest_s2_desc(paddr, desc, new_desc, wi);
+		if (ret)
+			return ret;
+
+		desc = new_desc;
+	}
+
 	if (!(desc & KVM_PTE_LEAF_ATTR_LO_S2_AF)) {
 		out->esr = compute_fsc(level, ESR_ELx_FSC_ACCESS);
 		out->desc = desc;
@@ -364,6 +394,8 @@ static void vtcr_to_walk_info(u64 vtcr, struct s2_walk_info *wi)
 	/* Global limit for now, should eventually be per-VM */
 	wi->max_oa_bits = min(get_kvm_ipa_limit(),
 			      ps_to_output_size(FIELD_GET(VTCR_EL2_PS_MASK, vtcr), false));
+
+	wi->ha = vtcr & VTCR_EL2_HA;
 }
 
 int kvm_walk_nested_s2(struct kvm_vcpu *vcpu, phys_addr_t gipa,
-- 
2.47.3


  parent reply	other threads:[~2025-11-17 22:43 UTC|newest]

Thread overview: 21+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-11-17 22:43 [PATCH v2 00/14] KVM: arm64: nv: Implement FEAT_XNX and FEAT_HAF Oliver Upton
2025-11-17 22:43 ` [PATCH v2 01/14] arm64: Detect FEAT_XNX Oliver Upton
2025-11-17 22:43 ` [PATCH v2 02/14] KVM: arm64: Add support for FEAT_XNX stage-2 permissions Oliver Upton
2025-11-21 12:24   ` Marc Zyngier
2025-11-17 22:43 ` [PATCH v2 03/14] KVM: arm64: nv: Forward FEAT_XNX permissions to the shadow stage-2 Oliver Upton
2025-11-17 22:43 ` [PATCH v2 04/14] KVM: arm64: Teach ptdump about FEAT_XNX permissions Oliver Upton
2025-11-17 22:43 ` [PATCH v2 05/14] KVM: arm64: nv: Advertise support for FEAT_XNX Oliver Upton
2025-11-17 22:43 ` [PATCH v2 06/14] KVM: arm64: Call helper for reading descriptors directly Oliver Upton
2025-11-21 17:10   ` Marc Zyngier
2025-11-17 22:43 ` [PATCH v2 07/14] KVM: arm64: Handle endianness in read helper for emulated PTW Oliver Upton
2025-11-21 17:40   ` Marc Zyngier
2025-11-17 22:43 ` [PATCH v2 08/14] KVM: arm64: nv: Use pgtable definitions in stage-2 walk Oliver Upton
2025-11-17 22:43 ` [PATCH v2 09/14] KVM: arm64: Add helper for swapping guest descriptor Oliver Upton
2025-11-21 18:25   ` Marc Zyngier
2025-11-17 22:43 ` [PATCH v2 10/14] KVM: arm64: Propagate PTW errors up to AT emulation Oliver Upton
2025-11-17 22:43 ` [PATCH v2 11/14] KVM: arm64: Implement HW access flag management in stage-1 SW PTW Oliver Upton
2025-11-17 22:43 ` Oliver Upton [this message]
2025-11-21 18:37   ` [PATCH v2 12/14] KVM: arm64: nv: Implement HW access flag management in stage-2 " Marc Zyngier
2025-11-17 22:43 ` [PATCH v2 13/14] KVM: arm64: nv: Expose hardware access flag management to NV guests Oliver Upton
2025-11-17 22:43 ` [PATCH v2 14/14] KVM: arm64: selftests: Add test for AT emulation Oliver Upton
2025-11-21 18:43 ` [PATCH v2 00/14] KVM: arm64: nv: Implement FEAT_XNX and FEAT_HAF Marc Zyngier

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