Re: [PATCH v20 13/14] tools: Synchronise the kernel esr.h

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] The tools version of `esr.h` is synchronized incorrectly, introducing an invalid value for the level -1 address size fault status code, which causes `esr_fsc_is_addr_sz_fault()` in userspace tools to misclassify actual level -1 address size faults.
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commit 2c5fc93c8578044cae22aadc2c4df4b978889699
Author: Mark Brown <broonie@kernel.org>
Subject: tools: Synchronise the kernel esr.h

This commit updates the tools version of esr.h to match the kernel version,
picking up new definitions for GCS.

> diff --git a/tools/arch/arm64/include/asm/esr.h b/tools/arch/arm64/include/asm/esr.h
> index f3c6403e5ef2b..24c6ebe3fd416 100644
> --- a/tools/arch/arm64/include/asm/esr.h
> +++ b/tools/arch/arm64/include/asm/esr.h

[ ... ]

> @@ -119,6 +123,16 @@
>  #define ESR_ELx_FSC_SEA_TTW(n)	(0x14 + (n))
>  #define ESR_ELx_FSC_SECC	(0x18)
>  #define ESR_ELx_FSC_SECC_TTW(n)	(0x1c + (n))
> +#define ESR_ELx_FSC_EXCL_ATOMIC	(0x35)
> +#define ESR_ELx_FSC_ADDRSZ	(0x00)
> +
> +/*
> + * Annoyingly, the negative levels for Address size faults aren't laid out
> + * contiguously (or in the desired order)
> + */
> +#define ESR_ELx_FSC_ADDRSZ_nL(n)	((n) == -1 ? 0x25 : 0x2C)

[Severity: Medium]
Does this synchronization introduce an invalid value for the level -1 address
size fault status code?

The main kernel's esr.h defines the level -1 address size fault as 0x29, but
this macro evaluates to 0x25 when n == -1. If hardware generates a level -1
address size fault, the resulting syndrome value is 0x29. Userspace tools or
KVM selftests checking the fault with esr_fsc_is_addr_sz_fault() will test
against 0x25 instead and incorrectly return false.

> +#define ESR_ELx_FSC_ADDRSZ_L(n)		((n) < 0 ? ESR_ELx_FSC_ADDRSZ_nL(n) : \
> +						   (ESR_ELx_FSC_ADDRSZ + (n)))

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Sashiko AI review · https://sashiko.dev/#/patchset/20260901-arm64-gcs-v20-0-f31750bdfadb@kernel.org?part=13