HCPTR cp15 writes need isb?

[Vikram Sethi <vikrams@codeaurora.org>]

Hi Marc, Christoffer, Catalin, Will,

I'm seeing an issue with KVM HCPTR (cp15) writes on guest entry/exit on one of Qualcomm's CPU cores in AArch32 host and AArch32 guest mode. Our CPU architects believe that HCPTR cp15 writes are context changing and require an isb.
With an isb in set_hcptr macro in arch/arm/kvm/interrupts_head.S I am able to boot the Aarch32 guest, but without it, I see strange crashes to hyp_undef or hyp_pabt.

What is your opinion on HCPTR cp15 writes being context changing and needing isb? I can submit a one line patch that adds the isb at the end of set_hcptr macro.

I did find some examples in ARMv7 ARM with an isb after cp15 write and an ARM blog [1] that states ISB "is used to ensure any previously executed context changing operations (including cp15 operations) will have completed by the time the ISB completed."

I also found this text from an older lkml thread [2] which seems to quote from an ARM document (although I cannot find the same text in ARMv7 ARM) "Any change to CP15 registers is guaranteed to be visible to subsequent
instructions only after one of isb, exception, return from exception"

1 http://community.arm.com/groups/processors/blog/2011/10/19/memory-access-ordering-part-3--memory-access-ordering-in-the-arm-architecture
2 http://lkml.iu.edu/hypermail/linux/kernel/1105.1/00475.html

Thanks,
Vikram

-- 
Vikram Sethi
Qualcomm Technologies Inc, on behalf of Qualcomm Innovation Center, Inc.
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project