Re: [PATCH v3 12/17] KVM: arm64: nv: Adjust range of accessible PMCs according to HPMN

[Marc Zyngier <maz@kernel.org>]

On Mon, 07 Oct 2024 18:45:54 +0100,
Oliver Upton <oliver.upton@linux.dev> wrote:
> 
> The value of MDCR_EL2.HPMN controls the number of event counters made
> visible to EL0 and EL1. This means it is possible for the guest
> hypervisor to allow direct access to event counters to the L2.
> 
> Rework KVM's PMU register emulation to take the effects of HPMN into
> account when handling a trap. For bitmask-style registers, writes only
> affect accessible registers.
> 
> Signed-off-by: Oliver Upton <oliver.upton@linux.dev>
> ---
>  arch/arm64/kvm/pmu-emul.c | 14 +++++++++++++-
>  arch/arm64/kvm/sys_regs.c | 12 ++++++------
>  include/kvm/arm_pmu.h     |  5 +++++
>  3 files changed, 24 insertions(+), 7 deletions(-)
> 
> diff --git a/arch/arm64/kvm/pmu-emul.c b/arch/arm64/kvm/pmu-emul.c
> index ca5da1da477d..746ff1ceb998 100644
> --- a/arch/arm64/kvm/pmu-emul.c
> +++ b/arch/arm64/kvm/pmu-emul.c
> @@ -276,6 +276,18 @@ bool kvm_pmu_counter_is_hyp(struct kvm_vcpu *vcpu, unsigned int idx)
>  	return idx >= hpmn;
>  }
>  
> +u64 kvm_pmu_accessible_counter_mask(struct kvm_vcpu *vcpu)
> +{
> +	u64 mask = kvm_pmu_implemented_counter_mask(vcpu);
> +	u64 hpmn;
> +
> +	if (!vcpu_has_nv(vcpu) || vcpu_is_el2(vcpu))
> +		return mask;
> +
> +	hpmn = SYS_FIELD_GET(MDCR_EL2, HPMN, __vcpu_sys_reg(vcpu, MDCR_EL2));
> +	return mask & GENMASK(hpmn - 1, 0);

Doesn't this break the cycle counter (bit 31)? Also, this is not going
to play very well with FEAT_ICNTR, where the instruction counter is
bit 32 in the mask.

Could we instead clear the bits from (PMCR_EL0.N - 1) down to HPMN?

Thanks,

	M.

-- 
Without deviation from the norm, progress is not possible.