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From: Marc Zyngier <maz@kernel.org>
To: Oliver Upton <oliver.upton@linux.dev>
Cc: kvmarm@lists.linux.dev, Joey Gouly <joey.gouly@arm.com>,
	Suzuki K Poulose <suzuki.poulose@arm.com>,
	Zenghui Yu <yuzenghui@huawei.com>,
	Mingwei Zhang <mizhang@google.com>,
	Colton Lewis <coltonlewis@google.com>,
	Raghavendra Rao Ananta <rananta@google.com>
Subject: Re: [PATCH v2 2/2] KVM: arm64: Use MDCR_EL2.HPME to evaluate overflow of hyp counters
Date: Wed, 20 Nov 2024 09:55:40 +0000	[thread overview]
Message-ID: <86sermut43.wl-maz@kernel.org> (raw)
In-Reply-To: <Zz2j1SEnH8OSrl5t@linux.dev>

On Wed, 20 Nov 2024 08:54:45 +0000,
Oliver Upton <oliver.upton@linux.dev> wrote:
> 
> On Wed, Nov 20, 2024 at 08:38:22AM +0000, Marc Zyngier wrote:
> > On Wed, 20 Nov 2024 00:52:30 +0000, Oliver Upton <oliver.upton@linux.dev> wrote:
> > > +/*
> > > + * Returns the PMU overflow state, which is true if there exists an event
> > > + * counter where the values of the global enable control, PMOVSSET_EL0[n], and
> > > + * PMINTENSET_EL1[n] are all 1.
> > > + */
> > > +static bool kvm_pmu_overflow_status(struct kvm_vcpu *vcpu)
> > >  {
> > > -	u64 reg = 0;
> > > +	u64 reg = __vcpu_sys_reg(vcpu, PMOVSSET_EL0);
> > >  
> > > -	if ((kvm_vcpu_read_pmcr(vcpu) & ARMV8_PMU_PMCR_E)) {
> > > -		reg = __vcpu_sys_reg(vcpu, PMOVSSET_EL0);
> > > -		reg &= __vcpu_sys_reg(vcpu, PMINTENSET_EL1);
> > > -	}
> > > +	reg &= __vcpu_sys_reg(vcpu, PMINTENSET_EL1);
> > > +
> > > +	/*
> > > +	 * PMCR_EL0.E is the global enable control for event counters available
> > > +	 * to EL0 and EL1.
> > > +	 */
> > > +	if (!(kvm_vcpu_read_pmcr(vcpu) & ARMV8_PMU_PMCR_E))
> > > +		reg &= kvm_pmu_hyp_counter_mask(vcpu);
> > 
> > So if the PMU is disabled at EL1, we remove the cycle counter from the
> > list of counters that are considered for an overflow.
> > 
> > I don't think that's what you really want.
> 
> That's how it is written though, no? My understanding is that the fixed
> counters are never reserved by EL2:
> 
> """
> The PE signals a request for:
> 
> [...]
> 
>  - The cycle counter, when the values of PMCR_EL0.E, PMOVSSET[31] and
>    PMINTENSET[31] are all 1
> """

Ah, fair enough. I had the misguided impression that there would be
another control for that, but this is actually called out in D13.11.2
("The PMU does not provide any control that a hypervisor can use to
reserve the cycle counter for its own use.").

I stand corrected.

> 
> PMUOverflowCondition() and PMUCounterIsHyp() seem to match this too.
> Unless I can't read, which happens a lot.

Nah, that's definitely me.

FWIW, and with the follow-up fixes:

Reviewed-by: Marc Zyngier <maz@kernel.org>

	M.

-- 
Without deviation from the norm, progress is not possible.

  reply	other threads:[~2024-11-20  9:55 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-11-20  0:52 [PATCH v2 0/2] KVM: arm64: Fixes for PMU overflow state Oliver Upton
2024-11-20  0:52 ` [PATCH v2 1/2] KVM: arm64: Ignore PMCNTENSET_EL0 while checking for overflow status Oliver Upton
2024-11-20  8:18   ` Marc Zyngier
2024-11-20  0:52 ` [PATCH v2 2/2] KVM: arm64: Use MDCR_EL2.HPME to evaluate overflow of hyp counters Oliver Upton
2024-11-20  1:00   ` Oliver Upton
2024-11-20  8:38   ` Marc Zyngier
2024-11-20  8:54     ` Oliver Upton
2024-11-20  9:55       ` Marc Zyngier [this message]
2024-11-21  8:18 ` [PATCH v2 0/2] KVM: arm64: Fixes for PMU overflow state Oliver Upton

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