From: "H. Peter Anvin" <hpa@zytor.com>
To: dan.j.williams@intel.com, Peter Zijlstra <peterz@infradead.org>
Cc: Jonathan Cameron <Jonathan.Cameron@huawei.com>,
Catalin Marinas <catalin.marinas@arm.com>,
james.morse@arm.com, linux-cxl@vger.kernel.org,
linux-arm-kernel@lists.infradead.org, linux-acpi@vger.kernel.org,
linux-arch@vger.kernel.org, linux-mm@kvack.org,
gregkh@linuxfoundation.org, Will Deacon <will@kernel.org>,
Davidlohr Bueso <dave@stgolabs.net>,
Yicong Yang <yangyicong@huawei.com>,
linuxarm@huawei.com, Yushan Wang <wangyushan12@huawei.com>,
Lorenzo Pieralisi <lpieralisi@kernel.org>,
Mark Rutland <mark.rutland@arm.com>,
Dave Hansen <dave.hansen@linux.intel.com>,
Thomas Gleixner <tglx@linutronix.de>,
Ingo Molnar <mingo@redhat.com>, Borislav Petkov <bp@alien8.de>,
x86@kernel.org, Andy Lutomirski <luto@kernel.org>
Subject: Re: [PATCH v2 0/8] Cache coherency management subsystem
Date: Thu, 10 Jul 2025 12:16:33 -0700 [thread overview]
Message-ID: <4CA4EB2A-8F45-4596-ADB9-B0C2307316B1@zytor.com> (raw)
In-Reply-To: <68701051ec185_1d3d1001d@dwillia2-xfh.jf.intel.com.notmuch>
On July 10, 2025 12:11:13 PM PDT, dan.j.williams@intel.com wrote:
>H. Peter Anvin wrote:
>[..]
>> >> > In the near term though, current CXL platforms that do not support
>> >> > device-initiated-invalidate still need coarse cache management for that
>> >> > original infrequent provisioning events. Folks that want to go further
>> >> > and attempt frequent DCD events with WBINVD get to keep all the pieces.
>> >>
>> >> I would strongly prefer those pieces to include WARNs and or worse.
>> >
>> >That is fair. It is not productive for the CXL subsystem to sit back and
>> >hope that people notice the destructive side-effects of wbinvd and hope
>> >that leads to device changes.
>> >
>> >This discussion has me reconsidering that yes, it would indeed be better
>> >to clflushopt loop over potentially terabytes on all CPUs. That should
>> >only be suffered rarely for the provisioning case, and for the DCD case
>> >the potential add/remove events should be more manageable.
>> >
>> >drm already has drm_clflush_pages() for bulk cache management, CXL
>> >should just align on that approach.
>>
>> Let's not be flippant; looping over terabytes could take *hours*. But those are hours during which the system is alive, and only one CPU needs to be looping.
>
>Do not all CPUs need to perform the invalidation for L1 copies of the
>line?
>
>Not trying to be flippant, but if wbinvd is only a one-shot per Peter's
>proposed policy and the system experiences another CXL reconfiguration
>event, then looping is the only option or fail the memory plug event.
>
>> The other question is: what happens if memory is unplugged and then a
>> cache line evicted? I'm guessing that existing memory hotplug
>> solutions simply drop the writeback, since the OS knows there is no
>> valid memory there, and so any cached data is inherently worthless.
>
>Right, the expectation is that unplug is always coordinated and that
>surprise unplug is unsupported / might lead to system instability.
>
>
CLFLUSH goes through the cache coherency protocol and is therefore system wide, which WBINVD is not.
next prev parent reply other threads:[~2025-07-10 19:17 UTC|newest]
Thread overview: 38+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-06-24 15:47 [PATCH v2 0/8] Cache coherency management subsystem Jonathan Cameron
2025-06-24 15:47 ` [PATCH v2 1/8] memregion: Support fine grained invalidate by cpu_cache_invalidate_memregion() Jonathan Cameron
2025-07-09 19:46 ` Davidlohr Bueso
2025-07-09 22:31 ` dan.j.williams
2025-07-11 11:54 ` Jonathan Cameron
2025-06-24 15:47 ` [PATCH v2 2/8] generic: Support ARCH_HAS_CPU_CACHE_INVALIDATE_MEMREGION Jonathan Cameron
2025-06-24 16:16 ` Greg KH
2025-06-25 16:46 ` Jonathan Cameron
2025-07-10 5:57 ` dan.j.williams
2025-07-10 6:01 ` H. Peter Anvin
2025-07-11 11:53 ` Jonathan Cameron
2025-07-11 11:52 ` Jonathan Cameron
2025-08-07 16:07 ` Jonathan Cameron
2025-06-24 15:47 ` [PATCH v2 3/8] cache: coherency core registration and instance handling Jonathan Cameron
2025-06-24 15:48 ` [PATCH v2 4/8] MAINTAINERS: Add Jonathan Cameron to drivers/cache Jonathan Cameron
2025-06-24 15:48 ` [PATCH v2 5/8] arm64: Select GENERIC_CPU_CACHE_INVALIDATE_MEMREGION Jonathan Cameron
2025-06-25 16:21 ` kernel test robot
2025-06-28 7:10 ` kernel test robot
2025-06-24 15:48 ` [PATCH v2 6/8] cache: Support cache maintenance for HiSilicon SoC Hydra Home Agent Jonathan Cameron
2025-06-24 17:18 ` Randy Dunlap
2025-06-24 15:48 ` [RFC v2 7/8] acpi: PoC of Cache control via ACPI0019 and _DSM Jonathan Cameron
2025-06-24 15:48 ` [PATCH v2 8/8] Hack: Pretend we have PSCI 1.2 Jonathan Cameron
2025-06-25 8:52 ` [PATCH v2 0/8] Cache coherency management subsystem Peter Zijlstra
2025-06-25 9:12 ` H. Peter Anvin
2025-06-25 9:31 ` Peter Zijlstra
2025-06-25 17:03 ` Jonathan Cameron
2025-06-26 9:55 ` Jonathan Cameron
2025-07-10 5:32 ` dan.j.williams
2025-07-10 10:59 ` Peter Zijlstra
2025-07-10 18:36 ` dan.j.williams
2025-07-10 5:22 ` dan.j.williams
2025-07-10 5:31 ` H. Peter Anvin
2025-07-10 10:56 ` Peter Zijlstra
2025-07-10 18:45 ` dan.j.williams
2025-07-10 18:55 ` H. Peter Anvin
2025-07-10 19:11 ` dan.j.williams
2025-07-10 19:16 ` H. Peter Anvin [this message]
2025-07-09 19:53 ` Davidlohr Bueso
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