Re: [PATCH v4 2/4] acpi/hmat / cxl: Add extended linear cache support for CXL

[Alison Schofield <alison.schofield@intel.com>]

On Mon, Feb 24, 2025 at 11:21:00AM -0700, Dave Jiang wrote:

snip to a dev_dbg message of interest -
> diff --git a/drivers/cxl/core/region.c b/drivers/cxl/core/region.c
> index e8d11a988fd9..cd7b0c31ebf7 100644
> --- a/drivers/cxl/core/region.c
> +++ b/drivers/cxl/core/region.c

snip
> @@ -1951,7 +1965,7 @@ static int cxl_region_attach(struct cxl_region *cxlr,
>  		return -ENXIO;
>  	}
>  
> -	if (resource_size(cxled->dpa_res) * p->interleave_ways !=
> +	if (resource_size(cxled->dpa_res) * p->interleave_ways + p->cache_size !=
>  	    resource_size(p->res)) {
>  		dev_dbg(&cxlr->dev,
>  			"%s:%s: decoder-size-%#llx * ways-%d != region-size-%#llx\n",

Add cache to this message since used in calculation above.
Took the liberty of trimming 'decoder-size' to '-size' since the decoder name
already precedes '-size'.



 		dev_dbg(&cxlr->dev,
-			"%s:%s: decoder-size-%#llx * ways-%d != region-size-%#llx\n",
+			"%s:%s-size-%#llx * ways-%d + cache-%#llx != region-size-%#llx\n",
 			dev_name(&cxlmd->dev), dev_name(&cxled->cxld.dev),
 			(u64)resource_size(cxled->dpa_res), p->interleave_ways,
-			(u64)resource_size(p->res));
+			(u64)p->cache_size, (u64)resource_size(p->res));
 		return -EINVAL;
 	}
 

snip