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From: Alison Schofield <alison.schofield@intel.com>
To: Dave Jiang <dave.jiang@intel.com>
Cc: linux-cxl@vger.kernel.org, linux-acpi@vger.kernel.org,
	rafael@kernel.org, bp@alien8.de, dan.j.williams@intel.com,
	tony.luck@intel.com, dave@stgolabs.net,
	jonathan.cameron@huawei.com, ira.weiny@intel.com,
	ming.li@zohomail.com
Subject: Re: [PATCH v4 3/4] cxl: Add extended linear cache address alias emission for cxl events
Date: Tue, 25 Feb 2025 12:34:03 -0800	[thread overview]
Message-ID: <Z74pO6m10psBdJns@aschofie-mobl2.lan> (raw)
In-Reply-To: <20250224182202.1683380-4-dave.jiang@intel.com>

On Mon, Feb 24, 2025 at 11:21:01AM -0700, Dave Jiang wrote:
> Add the aliased address of extended linear cache when emitting event
> trace for DRAM and general media of CXL events.

What about cxl_poison trace events?

When cxl device poison lists are read, or poison is injected
or cleared, an HPA is included in the trace event. Seems the
hpa_alias0 belong there too. 


> 
> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> Signed-off-by: Dave Jiang <dave.jiang@intel.com>
> ---
> v4:
> - Make error using ULLONG_MAX consistently. (Alison)
> - Make hpa_alias0 naming consistent. (Alison)
> - Swap incorrect position of hpa and hpa_alias0. (Alison)
> ---
>  drivers/cxl/core/mbox.c  | 28 ++++++++++++++++++++++++----
>  drivers/cxl/core/trace.h | 22 ++++++++++++++--------
>  2 files changed, 38 insertions(+), 12 deletions(-)
> 
> diff --git a/drivers/cxl/core/mbox.c b/drivers/cxl/core/mbox.c
> index 548564c770c0..808b6a3c577b 100644
> --- a/drivers/cxl/core/mbox.c
> +++ b/drivers/cxl/core/mbox.c
> @@ -856,6 +856,23 @@ int cxl_enumerate_cmds(struct cxl_memdev_state *mds)
>  }
>  EXPORT_SYMBOL_NS_GPL(cxl_enumerate_cmds, "CXL");
>  
> +static u64 cxlr_hpa_cache_alias(struct cxl_region *cxlr, u64 hpa)
> +{
> +	struct cxl_region_params *p;
> +
> +	if (!cxlr)
> +		return ULLONG_MAX;

checked cxlr in caller

> +
> +	p = &cxlr->params;
> +	if (!p->cache_size)
> +		return ULLONG_MAX;
> +
> +	if (hpa >= p->res->start + p->cache_size)
> +		return hpa - p->cache_size;
> +
> +	return hpa + p->cache_size;

Since a DPA can only be in the cxl resource half of the p->res, not in
the extended cache, is alias always hpa - cache.


>  void cxl_event_trace_record(const struct cxl_memdev *cxlmd,
>  			    enum cxl_event_log_type type,
>  			    enum cxl_event_type event_type,
> @@ -871,7 +888,7 @@ void cxl_event_trace_record(const struct cxl_memdev *cxlmd,
>  	}
>  
>  	if (trace_cxl_general_media_enabled() || trace_cxl_dram_enabled()) {
> -		u64 dpa, hpa = ULLONG_MAX;
> +		u64 dpa, hpa = ULLONG_MAX, hpa_alias = ULLONG_MAX;
>  		struct cxl_region *cxlr;
>  
>  		/*
> @@ -884,14 +901,17 @@ void cxl_event_trace_record(const struct cxl_memdev *cxlmd,
>  
>  		dpa = le64_to_cpu(evt->media_hdr.phys_addr) & CXL_DPA_MASK;
>  		cxlr = cxl_dpa_to_region(cxlmd, dpa);
> -		if (cxlr)
> +		if (cxlr) {
>  			hpa = cxl_dpa_to_hpa(cxlr, cxlmd, dpa);
> +			hpa_alias = cxlr_hpa_cache_alias(cxlr, hpa);
> +		}
>  

How about something like this to eliminate cxlr_hpa_cache_alias():
 
 	if (trace_cxl_general_media_enabled() || trace_cxl_dram_enabled()) {
-		u64 dpa, hpa = ULLONG_MAX, hpa_alias = ULLONG_MAX;
+		u64 dpa, cache_size, hpa = ULLONG_MAX, hpa_alias = ULLONG_MAX;
 		struct cxl_region *cxlr;
 
 		/*
@@ -904,7 +887,9 @@ void cxl_event_trace_record(const struct cxl_memdev *cxlmd,
 		cxlr = cxl_dpa_to_region(cxlmd, dpa);
 		if (cxlr) {
 			hpa = cxl_dpa_to_hpa(cxlr, cxlmd, dpa);
-			hpa_alias = cxlr_hpa_cache_alias(cxlr, hpa);
+			cache_size = cxlr->params.cache_size;
+			if (cache_size)
+				hpa_alias = hpa - cache_size;
 		}


snip


  parent reply	other threads:[~2025-02-25 20:34 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-02-24 18:20 [PATCH v4 0/4] acpi/hmat / cxl: Add exclusive caching enumeration and RAS support Dave Jiang
2025-02-24 18:20 ` [PATCH v4 1/4] acpi: numa: Add support to enumerate and store extended linear address mode Dave Jiang
2025-02-25 14:09   ` Li Ming
2025-02-24 18:21 ` [PATCH v4 2/4] acpi/hmat / cxl: Add extended linear cache support for CXL Dave Jiang
2025-02-25 14:10   ` Li Ming
2025-02-25 20:00   ` Alison Schofield
2025-02-25 20:35     ` Dave Jiang
2025-02-25 20:11   ` Alison Schofield
2025-02-24 18:21 ` [PATCH v4 3/4] cxl: Add extended linear cache address alias emission for cxl events Dave Jiang
2025-02-25 14:10   ` Li Ming
2025-02-25 20:34   ` Alison Schofield [this message]
2025-02-24 18:21 ` [PATCH v4 4/4] cxl: Add mce notifier to emit aliased address for extended linear cache Dave Jiang
2025-02-25 14:11   ` Li Ming

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