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From: Sunil V L <sunilvl@ventanamicro.com>
To: Andrew Jones <ajones@ventanamicro.com>
Cc: linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org,
	linux-acpi@vger.kernel.org, iommu@lists.linux.dev,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	Alexandre Ghiti <alex@ghiti.fr>,
	"Rafael J . Wysocki" <rafael@kernel.org>,
	Len Brown <lenb@kernel.org>,
	Tomasz Jeznach <tjeznach@rivosinc.com>,
	Joerg Roedel <joro@8bytes.org>, Will Deacon <will@kernel.org>,
	Robin Murphy <robin.murphy@arm.com>,
	Anup Patel <apatel@ventanamicro.com>,
	Atish Patra <atishp@rivosinc.com>,
	"Rafael J . Wysocki" <rafael.j.wysocki@intel.com>
Subject: Re: [PATCH v3 2/3] ACPI: scan: Add support for RISC-V in acpi_iommu_configure_id()
Date: Tue, 1 Jul 2025 09:03:55 +0530	[thread overview]
Message-ID: <aGNXIzi8vYL4AOj4@sunil-laptop> (raw)
In-Reply-To: <20250630-c479c6607cf8c1430f11336f@orel>

On Mon, Jun 30, 2025 at 10:02:53AM +0200, Andrew Jones wrote:
> On Mon, Jun 30, 2025 at 09:18:02AM +0530, Sunil V L wrote:
> > acpi_iommu_configure_id() currently supports only IORT (ARM) and VIOT.
> > Add support for RISC-V as well.
> > 
> > Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
> > Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
> > ---
> >  drivers/acpi/scan.c | 9 +++++++--
> >  1 file changed, 7 insertions(+), 2 deletions(-)
> > 
> > diff --git a/drivers/acpi/scan.c b/drivers/acpi/scan.c
> > index fb1fe9f3b1a3..70f57d58fd61 100644
> > --- a/drivers/acpi/scan.c
> > +++ b/drivers/acpi/scan.c
> > @@ -11,6 +11,7 @@
> >  #include <linux/kernel.h>
> >  #include <linux/acpi.h>
> >  #include <linux/acpi_iort.h>
> > +#include <linux/acpi_rimt.h>
> >  #include <linux/acpi_viot.h>
> >  #include <linux/iommu.h>
> >  #include <linux/signal.h>
> > @@ -1628,8 +1629,12 @@ static int acpi_iommu_configure_id(struct device *dev, const u32 *id_in)
> >  	}
> >  
> >  	err = iort_iommu_configure_id(dev, id_in);
> > -	if (err && err != -EPROBE_DEFER)
> > -		err = viot_iommu_configure(dev);
> > +	if (err && err != -EPROBE_DEFER) {
> > +		err = rimt_iommu_configure_id(dev, id_in);
> > +		if (err && err != -EPROBE_DEFER)
> > +			err = viot_iommu_configure(dev);
> > +	}
> 
> This can just be
> 
>   err = iort_iommu_configure_id(dev, id_in);
>   if (err...
>      err = rimt_iommu_configure_id(dev, id_in);
>   if (err...
>      err = viot_iommu_configure(dev);
> 
> Thanks,
> drew
> 
Sure. Let me update in the next version.

Thanks!
Sunil

  reply	other threads:[~2025-07-01  3:34 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-06-30  3:48 [PATCH v3 0/3] RISC-V: Add ACPI support for IOMMU Sunil V L
2025-06-30  3:48 ` [PATCH v3 1/3] ACPI: RISC-V: Add support for RIMT Sunil V L
2025-06-30  7:55   ` Andrew Jones
2025-07-01  3:47     ` Sunil V L
2025-06-30  3:48 ` [PATCH v3 2/3] ACPI: scan: Add support for RISC-V in acpi_iommu_configure_id() Sunil V L
2025-06-30  8:02   ` Andrew Jones
2025-07-01  3:33     ` Sunil V L [this message]
2025-06-30  3:48 ` [PATCH v3 3/3] iommu/riscv: Add ACPI support Sunil V L
2025-06-30  8:48   ` Andrew Jones
2025-07-13 11:47   ` Will Deacon
2025-06-30  3:51 ` [PATCH v3 0/3] RISC-V: Add ACPI support for IOMMU Sunil V L

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