Re: [PATCH v4 5/8] ACPI: CPPC: add APIs and sysfs interface for perf_limited register

[Sumit Gupta <sumitg@nvidia.com>]

On 27/11/25 20:24, Pierre Gondois wrote:
> External email: Use caution opening links or attachments
>
>
> On 11/5/25 12:38, Sumit Gupta wrote:
>> Add sysfs interface to read/write the Performance Limited register.
>>
>> The Performance Limited register indicates to the OS that an
>> unpredictable event (like thermal throttling) has limited processor
>> performance. This register is sticky and remains set until reset or
>> OS clears it by writing 0.
>>
>> The interface is exposed as:
>>   /sys/devices/system/cpu/cpuX/cpufreq/perf_limited
>>
>> Signed-off-by: Sumit Gupta<sumitg@nvidia.com>
>> ---
>>   drivers/acpi/cppc_acpi.c       | 26 ++++++++++++++++++++++++++
>>   drivers/cpufreq/cppc_cpufreq.c | 12 ++++++++++++
>>   include/acpi/cppc_acpi.h       | 10 ++++++++++
>>   3 files changed, 48 insertions(+)
>>
>> diff --git a/drivers/acpi/cppc_acpi.c b/drivers/acpi/cppc_acpi.c
>> index ef53eb8a1feb..9b8da3ef06db 100644
>> --- a/drivers/acpi/cppc_acpi.c
>> +++ b/drivers/acpi/cppc_acpi.c
>> @@ -1810,6 +1810,32 @@ int cppc_set_max_perf(int cpu, u64 max_perf)
>>   }
>>   EXPORT_SYMBOL_GPL(cppc_set_max_perf);
>>
>> +/**
>> + * cppc_get_perf_limited - Get the Performance Limited register value.
>> + * @cpu: CPU from which to get Performance Limited register.
>> + * @perf_limited: Pointer to store the Performance Limited value.
>> + *
>> + * Return: 0 for success, -EIO on register access failure, 
>> -EOPNOTSUPP if not supported.
>> + */
>> +int cppc_get_perf_limited(int cpu, u64 *perf_limited)
>> +{
>> +     return cppc_get_reg_val(cpu, PERF_LIMITED, perf_limited);
>> +}
>> +EXPORT_SYMBOL_GPL(cppc_get_perf_limited);
>> +
>> +/**
>> + * cppc_set_perf_limited() - Write the Performance Limited register.
>> + * @cpu: CPU on which to write register.
>> + * @perf_limited: Value to write to the perf_limited register.
>> + *
>> + * Return: 0 for success, -EIO on register access failure, 
>> -EOPNOTSUPP if not supported.
>> + */
>> +int cppc_set_perf_limited(int cpu, u64 perf_limited)
>> +{
>> +     return cppc_set_reg_val(cpu, PERF_LIMITED, perf_limited);
>> +}
>
> There are currently only 2 bits used:
> - 0 Desired_Excursion
> - 1 Minimum_Excursion
> It might be worth defining these bits and mask the values when trying to
> set the register.
>

Will do the change to allow only the clearing of these two bits and not 
setting.


> ------
>
> Also NIT:
>
> The spec. says:
> " All accesses to the Performance Limited Register must be made using
> interlocked operations, by both accessing entities."
>
> I am not sure I understand which synchronization issues are faced.
> It's just to report the comment from the spec.
>

cpc_write() already has locking. So, two writes will complete without 
interference.
As you suggested above, only the required register bit will be cleared 
by an operation.

Thank you,
Sumit Gupta


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