From: "Paul E. McKenney" <paulmck@linux.vnet.ibm.com>
To: will.deacon@arm.com, ralf@linux-mips.org, tony.luck@intel.com,
fenghua.yu@intel.com
Cc: linux-arch@vger.kernel.org
Subject: Fw: Getting an early start on C++ standards issues...
Date: Fri, 26 Feb 2016 06:50:57 -0800 [thread overview]
Message-ID: <20160226145057.GA6734@linux.vnet.ibm.com> (raw)
Hello!
Do ARM, MIPS, and IA64 data/address/control dependencies apply to loads
and stores from vector instructions? The use case appears to be that the
dependency chain is headed by a normal load instruction, and a dependency
to a later vector load/store is desired.
Any other weakly ordered architectures with vector instructions?
Thanx, Paul
Original query from Torvald Riegel and Richard Biener:
> > I'm not sure I understand you correctly. Do you have a brief example,
> > perhaps? For mo_consume and its data dependencies, if there might be a
> > dependence, the compiler would have to preserve it; but I guess that
> > both a vectorized loop an one that accessses each element separately
> > would preserve dependences because it's doing those accesses, and they
> > depend on the input data.
> > OTOH, peraps HW vector instructions don't get the ordering guarantees
> > from data dependences -- Paul, do you know of any such cases?
>
> A brief example would be for
>
> void foo (int *a, int *b, int n)
> {
> for (int i = 0; i < n; ++i)
> a[i] = b[i];
> }
>
> which we can vectorize like
>
> if (a + n < b || b + n < a)
> {
> vectorized loop
> }
> else
> {
> not vectorized loop
> }
>
> note how we're not establishing equivalences between pointers but
> non-dependence vs. possible dependence.
next reply other threads:[~2016-02-26 14:51 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-02-26 14:50 Paul E. McKenney [this message]
2016-02-26 15:22 ` Fw: Getting an early start on C++ standards issues Will Deacon
2016-02-26 21:33 ` Paul E. McKenney
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