Fw: Getting an early start on C++ standards issues...

Fw: Getting an early start on C++ standards issues...

[Paul E. McKenney]

Hello!

Do ARM, MIPS, and IA64 data/address/control dependencies apply to loads
and stores from vector instructions?  The use case appears to be that the
dependency chain is headed by a normal load instruction, and a dependency
to a later vector load/store is desired.

Any other weakly ordered architectures with vector instructions?

							Thanx, Paul

Original query from Torvald Riegel and Richard Biener:

> > I'm not sure I understand you correctly.  Do you have a brief example,
> > perhaps?  For mo_consume and its data dependencies, if there might be a
> > dependence, the compiler would have to preserve it; but I guess that
> > both a vectorized loop an one that accessses each element separately
> > would preserve dependences because it's doing those accesses, and they
> > depend on the input data.
> > OTOH, peraps HW vector instructions don't get the ordering guarantees
> > from data dependences -- Paul, do you know of any such cases?
> 
> A brief example would be for
> 
>  void foo (int *a, int *b, int n)
> {
>   for (int i = 0; i < n; ++i)
>    a[i] = b[i];
> }
> 
> which we can vectorize like
> 
>   if (a + n < b || b + n < a)
>    {
>       vectorized loop
>    }
>   else
>     {
>        not vectorized loop
>     }
> 
> note how we're not establishing equivalences between pointers but
> non-dependence vs. possible dependence.

Re: Fw: Getting an early start on C++ standards issues...

[Will Deacon]

On Fri, Feb 26, 2016 at 06:50:57AM -0800, Paul E. McKenney wrote:
> Hello!

Hi Paul,

> Do ARM, MIPS, and IA64 data/address/control dependencies apply to loads
> and stores from vector instructions?  The use case appears to be that the
> dependency chain is headed by a normal load instruction, and a dependency
> to a later vector load/store is desired.
> 
> Any other weakly ordered architectures with vector instructions?

We certainly have instructions that don't honour address dependencies,
for example LDNP (load non-temporal pair), and these could be used by
variants of memcpy. x86 has something similar with MOVNTDQA[1].

It's highly likely that we'd consider similar relaxations for extensions
to our vector instructions in future revisions of the ARM architecture,
so I don't think we should generally rely on address dependencies
providing order for vectorised code.

Will

[1] http://www.felixcloutier.com/x86/MOVNTDQA.html

Re: Fw: Getting an early start on C++ standards issues...

[Paul E. McKenney]

On Fri, Feb 26, 2016 at 03:22:38PM +0000, Will Deacon wrote:
> On Fri, Feb 26, 2016 at 06:50:57AM -0800, Paul E. McKenney wrote:
> > Hello!
> 
> Hi Paul,
> 
> > Do ARM, MIPS, and IA64 data/address/control dependencies apply to loads
> > and stores from vector instructions?  The use case appears to be that the
> > dependency chain is headed by a normal load instruction, and a dependency
> > to a later vector load/store is desired.
> > 
> > Any other weakly ordered architectures with vector instructions?
> 
> We certainly have instructions that don't honour address dependencies,
> for example LDNP (load non-temporal pair), and these could be used by
> variants of memcpy. x86 has something similar with MOVNTDQA[1].
> 
> It's highly likely that we'd consider similar relaxations for extensions
> to our vector instructions in future revisions of the ARM architecture,
> so I don't think we should generally rely on address dependencies
> providing order for vectorised code.

Thank you for the information, Will!

							Thanx, Paul

> Will
> 
> [1] http://www.felixcloutier.com/x86/MOVNTDQA.html
>