From: Tangnianyao <tangnianyao@huawei.com>
To: Oliver Upton <oupton@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>,
Marc Zyngier <maz@kernel.org>,
Wei-Lin Chang <weilin.chang@arm.com>, <joey.gouly@arm.com>,
<seiden@linux.ibm.com>, <suzuki.poulose@arm.com>,
<yuzenghui@huawei.com>, <catalin.marinas@arm.com>,
<will@kernel.org>, <linux-arm-kernel@lists.infradead.org>,
<kvmarm@lists.linux.dev>, <linux-kernel@vger.kernel.org>,
"guoyang (C)" <guoyang2@huawei.com>,
"huanglingyan (A)" <huanglingyan2@huawei.com>,
"Wangzhou (B)" <wangzhou1@hisilicon.com>
Subject: Re: Question about the "TLBs and I-cache are private to each vCPU" guarantee with VTTBR_EL2.CnP
Date: Wed, 8 Jul 2026 16:10:18 +0800 [thread overview]
Message-ID: <007d69fe-9554-b9c1-dd89-23856d78571b@huawei.com> (raw)
In-Reply-To: <akyeWPzrMDuAGRXP@kernel.org>
On 7/7/2026 14:36, Oliver Upton wrote:
> On Tue, Jul 07, 2026 at 10:41:35AM +0800, Tangnianyao wrote:
>> On 7/6/2026 23:33, Mark Rutland wrote:
>>> If *both* of the vCPUs set TTBRn_EL1.CnP, then surely that is
>>> indistinguishable from physical CPUs:
>>>
>>> PE0(core0,smt0) PE1(core0,smt1)
>>> cpu0 va->pa0
>>> cpu1 flush local tlb
>>> cpu1 modify desc to va->pa1
>>> cpu0 hit *va->pa1*
>>>
>>> Mark.
>>>
>>> .
>>>
>> Thanks for the clarification.
>> Stage-1 CnP determines whether Stage-1 translation entries may be shared
>> across vCPUs, and the hardware is responsible for enforcing the
>> architectural semantics.
>>
>> Given that, why does KVM still need to guarantee that TLBs are private to
>> each vCPU?
>>
>> Assuming VTTBR_EL2.CnP == 1:
>> If TTBRx_EL1.CnP == 1, the guest is responsible for ensuring that the
>> translations referenced by TTBRx_EL1 are shareable, as required by the
>> architecture.
>> If TTBRx_EL1.CnP == 0, the hardware must ensure that Stage-1 translations
>> are not shared, again according to the architectural definition.
>>
>> The reason I'm asking is the potential performance impact. In a scenario
>> where multiple vCPUs of the same VM are scheduled onto a single PE, this
>> TLB flush may prevent a vCPU from reusing its previously populated
>> translation entries, potentially increasing TLB misses.
> The problem is you can't infer the state of the TLB based on the current
> value of CnP at stage-1. CnP only applies to the current TTBR;
> nothing stops the guest from using a mix of CnP=0/1 for different TTBRs.
>
> KVM still needs to invalidate in the case that the PE retained a CnP=0
> TLB entry for a different stage-1 context than the one configured at
> the time of vcpu_load().
>
> Thanks,
> Oliver
> .
>
Thanks for the explanation. When the guest uses `Stage-1 CnP = 0`, kvm
does need the flush to maintain the "private to each vCPU" guarantee.
Thanks,
Nianyao Tang
prev parent reply other threads:[~2026-07-08 8:12 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-07-04 7:45 Question about the "TLBs and I-cache are private to each vCPU" guarantee with VTTBR_EL2.CnP Tangnianyao
2026-07-05 17:28 ` Wei-Lin Chang
2026-07-06 3:30 ` Tangnianyao
2026-07-06 7:25 ` Marc Zyngier
2026-07-06 8:25 ` Tangnianyao
2026-07-06 8:44 ` Marc Zyngier
2026-07-06 14:15 ` Tangnianyao
2026-07-06 15:18 ` Will Deacon
2026-07-06 15:33 ` Mark Rutland
2026-07-07 2:41 ` Tangnianyao
2026-07-07 6:36 ` Oliver Upton
2026-07-08 8:10 ` Tangnianyao [this message]
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