ARM1176 goes wild when MMU on line

ARM1176 goes wild when MMU on line

[胡杨树]

Hi, guys:)
      I'm porting Linux-2.6.30 to a ARM1176 core based SOC from scratch.
When i turned MMU off in arch/arm/boot/compressed/Head.S , kernel can decompress easily, and boot onto start_kernel, while it's a little bit slow for decompressing.
But when MMU is on line, functions call in decompress_kernel go wild!
      I checked the page tables, it's definitely OK with my memory space and ARM1176 has ARMv7 VMSA.  Am I?missing something obvious?

      DDR2 space 0x00000000 ~ 0x0fffffff ,256M
       I load zImage at 0x0
      zreladdr-y    := 0x00608000
      params_phys-y    := 0x00600100
 
 
The page table looks like this:
|0x0000_0C1E | address:0x604000  DDR bufferable/cachable
|0x0010_0C1E | address:0x604004  DDR bufferable/cachable
|0x0020_0C1E | address:0x604008  DDR bufferable/cachable
         X
         X       
|0x0FF0_0C1E | address:0x6043FC DDR bufferable/cachable
|0x0100_0C12 | address:0x604400 Peripheral unbufferable/uncachable
         X
         X
|0xFFD0_0C12 | address:0x607FF4 Peripheral unbufferable/uncachable
|0xFFE0_0C12 | address:0x607FF8 Peripheral unbufferable/uncachable
|0xFFF0_0C12 | address:0x607FFC Peripheral unbufferable/uncachable

ARM1176 goes wild when MMU on line

[Laurent Desnogues]

2009/10/20 ??? <914059751@qq.com>:
> ARM1176 has ARMv7 VMSA. ?Am I?missing something obvious?

Is that a typo? ARM1176 is an ARMv6 chip, not an ARMv7 one.


Laurent

答复: ARM1176 goes wild when MMU on line

[rocky]

ARM1176 is definitely an ARMv7 VMSA! Its CPUID is:0x410FB764, check the
following code to see how does kernel code decide which architecture
operation procedure to use.

BTW: S3C6410 is also based on ARM1176 core, it uses ARMv7 cache calls as
well.

--------------- Arch/arm/boot/compressed/head.S -------------------
/*
 * Here follow the relocatable cache support functions for the
 * various processors.  This is a generic hook for locating an
 * entry and jumping to an instruction at the specified offset
 * from the start of the block.  Please note this is all position
 * independent code.
 *
 *  r1  = corrupted
 *  r2  = corrupted
 *  r3  = block offset
 *  r6  = corrupted
 *  r12 = corrupted
 */

call_cache_fn:	adr	r12, proc_types
#ifdef CONFIG_CPU_CP15
		mrc	p15, 0, r6, c0, c0	@ get processor ID
#else
		ldr	r6, =CONFIG_PROCESSOR_ID
#endif
1:		ldr	r1, [r12, #0]		@ get value
		ldr	r2, [r12, #4]		@ get mask
		eor	r1, r1, r6		@ (real ^ match)
		tst	r1, r2			@       & mask
		addeq	pc, r12, r3		@ call cache function
		add	r12, r12, #4*5
		b	1b
proc_types
		.word	0x000f0000		@ new CPU Id
		.word	0x000f0000
		b	__armv7_mmu_cache_on
		b	__armv7_mmu_cache_off
		b	__armv7_mmu_cache_flush

-----????-----
???: Laurent Desnogues [mailto:laurent.desnogues at gmail.com] 
????: 2009?10?20? 18:00
???: ???
??: linux-arm-kernel
??: Re: ARM1176 goes wild when MMU on line

2009/10/20 ??? <914059751@qq.com>:
> ARM1176 has ARMv7 VMSA. ?Am I?missing something obvious?

Is that a typo? ARM1176 is an ARMv6 chip, not an ARMv7 one.


Laurent

Re: 答复: ARM1176 goes wild when MMU on line

[Laurent Desnogues]

2009/10/20 rocky <914059751@qq.com>:
> ARM1176 is definitely an ARMv7 VMSA! Its CPUID is:0x410FB764, check the
> following code to see how does kernel code decide which architecture
> operation procedure to use.

If you don't trust me, read these pages:

http://www.arm.com/products/CPUs/ARM1176.html
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0333g/I1000175.html


Laurent

答复: ARM1176 goes wild when MMU on line

[rocky]

Hi,Peter:)
	Thanks for you tips! 
	It appears that ARM1176 implementing an revised ARMv7 CPU ID, though
it's based on an ARMv6 core. I changed ARMv6 cpu mask of cache function in
arch/arm/boot/compressed/head.S, kernel still pops in decompress_kernel. I
really don't know how to debug this, any advise would be really appreciated.


--rocky




-----????-----
???: Peter Pearse [mailto:peter.pearse at arm.com] 
????: 2009?10?26? 16:28
???: 'rocky'
??: RE: ARM1176 goes wild when MMU on line

http://www.arm.com/products/CPUs/ARM1176.html 

> -----Original Message-----
> From: linux-arm-kernel-bounces at lists.infradead.org 
> [mailto:linux-arm-kernel-bounces at lists.infradead.org] On 
> Behalf Of rocky
> Sent: 20 October 2009 11:19
> To: 'Laurent Desnogues'
> Cc: 'linux-arm-kernel'
> Subject: ??: ARM1176 goes wild when MMU on line
> 
> ARM1176 is definitely an ARMv7 VMSA! Its CPUID is:0x410FB764, 
> check the following code to see how does kernel code decide 
> which architecture operation procedure to use.
> 
> BTW: S3C6410 is also based on ARM1176 core, it uses ARMv7 
> cache calls as well.
> 
> --------------- Arch/arm/boot/compressed/head.S -------------------
> /*
>  * Here follow the relocatable cache support functions for the
>  * various processors.  This is a generic hook for locating an
>  * entry and jumping to an instruction at the specified offset
>  * from the start of the block.  Please note this is all position
>  * independent code.
>  *
>  *  r1  = corrupted
>  *  r2  = corrupted
>  *  r3  = block offset
>  *  r6  = corrupted
>  *  r12 = corrupted
>  */
> 
> call_cache_fn:	adr	r12, proc_types
> #ifdef CONFIG_CPU_CP15
> 		mrc	p15, 0, r6, c0, c0	@ get processor ID
> #else
> 		ldr	r6, =CONFIG_PROCESSOR_ID
> #endif
> 1:		ldr	r1, [r12, #0]		@ get value
> 		ldr	r2, [r12, #4]		@ get mask
> 		eor	r1, r1, r6		@ (real ^ match)
> 		tst	r1, r2			@       & mask
> 		addeq	pc, r12, r3		@ call cache function
> 		add	r12, r12, #4*5
> 		b	1b
> proc_types
> 		.word	0x000f0000		@ new CPU Id
> 		.word	0x000f0000
> 		b	__armv7_mmu_cache_on
> 		b	__armv7_mmu_cache_off
> 		b	__armv7_mmu_cache_flush
> 
> -----????-----
> ???: Laurent Desnogues [mailto:laurent.desnogues at gmail.com]
> ????: 2009?10?20? 18:00
> ???: ???
> ??: linux-arm-kernel
> ??: Re: ARM1176 goes wild when MMU on line
> 
> 2009/10/20 ??? <914059751@qq.com>:
> > ARM1176 has ARMv7 VMSA. ?Am I?missing something obvious?
> 
> Is that a typo? ARM1176 is an ARMv6 chip, not an ARMv7 one.
> 
> 
> Laurent
> 
> 
> 
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