[PATCH net-next v23 0/9] net: dsa: Add Airoha AN8855 support

[PATCH net-next v23 0/9] net: dsa: Add Airoha AN8855 support

[Christian Marangi]

This series add the initial support for the Airoha AN8855 Switch.

It's a 5 port Gigabit Switch with SGMII/HSGMII upstream port.

This is starting to get in the wild and there are already some router
having this switch chip.

MT7530 is generalized with reg fields to a shared library to
reduce code duplication and reuse all the logic for AN8855.

There is this special thing where PHY needs to be calibrated with values
from the switch efuse. (the thing have a whole cpu timer and MCU)

Given the double usage of PHY and Switch accessor, a special handling
is used with registering a mdio-regmap bus for each internal PHY.

From v8 Driver is now evaluated with Kernel selftest scripts for DSA:

Additional info about the test bridge_vlan_aware.sh.

It was discovered that the Airoha Switch (and probably the Mediatek one
that produce the same test results) hardcode checking for 802.1ad when
the port is configured in VLAN-Aware mode (aka Security mode).

In such mode, both 802.1q and 802.1ad TPID are checked, hence the
bridge_vlan_aware.sh test fails as packets with 802.1ad TPID are rejected
(in the case where a wrong VLAN ID is forwarded)

This was confirmed by Airoha and multiple try were done to try to
workaround this problem. No solution were found to this as ACL mechanism
can't work on receiving packets and the Switch doesn't support turning off
this.

The current driver is in use from 4 month on OpenWrt with all kind of
scenario confirming working in VLAN bridge. By tweaking the
bridge_vlan_aware.sh test with setting the TPID to 0x9100, the test
correctly pass as packets gets classified as untagged and the default PVID
applied. It's also confirmed that switch correctly parse the 802.1ad tag
and make the packet pass only when allowed by VLAN table rules.

Output local_termination.sh
TEST: lan2: Unicast IPv4 to primary MAC address                     [ OK ]
TEST: lan2: Unicast IPv4 to macvlan MAC address                     [ OK ]
TEST: lan2: Unicast IPv4 to unknown MAC address                     [ OK ]
TEST: lan2: Unicast IPv4 to unknown MAC address, promisc            [ OK ]
TEST: lan2: Unicast IPv4 to unknown MAC address, allmulti           [ OK ]
TEST: lan2: Multicast IPv4 to joined group                          [ OK ]
TEST: lan2: Multicast IPv4 to unknown group                         [XFAIL]
        reception succeeded, but should have failed
TEST: lan2: Multicast IPv4 to unknown group, promisc                [ OK ]
TEST: lan2: Multicast IPv4 to unknown group, allmulti               [ OK ]
TEST: lan2: Multicast IPv6 to joined group                          [ OK ]
TEST: lan2: Multicast IPv6 to unknown group                         [XFAIL]
        reception succeeded, but should have failed
TEST: lan2: Multicast IPv6 to unknown group, promisc                [ OK ]
TEST: lan2: Multicast IPv6 to unknown group, allmulti               [ OK ]
TEST: lan2: 1588v2 over L2 transport, Sync                          [ OK ]
TEST: lan2: 1588v2 over L2 transport, Follow-Up                     [ OK ]
TEST: lan2: 1588v2 over L2 transport, Peer Delay Request            [ OK ]
TEST: lan2: 1588v2 over IPv4, Sync                                  [FAIL]
        reception failed
TEST: lan2: 1588v2 over IPv4, Follow-Up                             [FAIL]
        reception failed
TEST: lan2: 1588v2 over IPv4, Peer Delay Request                    [FAIL]
        reception failed
TEST: lan2: 1588v2 over IPv6, Sync                                  [FAIL]
        reception failed
TEST: lan2: 1588v2 over IPv6, Follow-Up                             [FAIL]
        reception failed
TEST: lan2: 1588v2 over IPv6, Peer Delay Request                    [FAIL]
        reception failed
TEST: vlan_filtering=0 bridge: Unicast IPv4 to primary MAC address   [ OK ]
TEST: vlan_filtering=0 bridge: Unicast IPv4 to macvlan MAC address   [ OK ]
TEST: vlan_filtering=0 bridge: Unicast IPv4 to unknown MAC address   [ OK ]
TEST: vlan_filtering=0 bridge: Unicast IPv4 to unknown MAC address, promisc   [ OK ]
TEST: vlan_filtering=0 bridge: Unicast IPv4 to unknown MAC address, allmulti   [ OK ]
TEST: vlan_filtering=0 bridge: Multicast IPv4 to joined group       [ OK ]
TEST: vlan_filtering=0 bridge: Multicast IPv4 to unknown group      [XFAIL]
        reception succeeded, but should have failed
TEST: vlan_filtering=0 bridge: Multicast IPv4 to unknown group, promisc   [ OK ]
TEST: vlan_filtering=0 bridge: Multicast IPv4 to unknown group, allmulti   [ OK ]
TEST: vlan_filtering=0 bridge: Multicast IPv6 to joined group       [ OK ]
TEST: vlan_filtering=0 bridge: Multicast IPv6 to unknown group      [XFAIL]
        reception succeeded, but should have failed
TEST: vlan_filtering=0 bridge: Multicast IPv6 to unknown group, promisc   [ OK ]
TEST: vlan_filtering=0 bridge: Multicast IPv6 to unknown group, allmulti   [ OK ]
TEST: vlan_filtering=1 bridge: Unicast IPv4 to primary MAC address   [ OK ]
TEST: vlan_filtering=1 bridge: Unicast IPv4 to macvlan MAC address   [ OK ]
TEST: vlan_filtering=1 bridge: Unicast IPv4 to unknown MAC address   [ OK ]
TEST: vlan_filtering=1 bridge: Unicast IPv4 to unknown MAC address, promisc   [ OK ]
TEST: vlan_filtering=1 bridge: Unicast IPv4 to unknown MAC address, allmulti   [ OK ]
TEST: vlan_filtering=1 bridge: Multicast IPv4 to joined group       [ OK ]
TEST: vlan_filtering=1 bridge: Multicast IPv4 to unknown group      [XFAIL]
        reception succeeded, but should have failed
TEST: vlan_filtering=1 bridge: Multicast IPv4 to unknown group, promisc   [ OK ]
TEST: vlan_filtering=1 bridge: Multicast IPv4 to unknown group, allmulti   [ OK ]
TEST: vlan_filtering=1 bridge: Multicast IPv6 to joined group       [ OK ]
TEST: vlan_filtering=1 bridge: Multicast IPv6 to unknown group      [XFAIL]
        reception succeeded, but should have failed
TEST: vlan_filtering=1 bridge: Multicast IPv6 to unknown group, promisc   [ OK ]
TEST: vlan_filtering=1 bridge: Multicast IPv6 to unknown group, allmulti   [ OK ]
TEST: VLAN upper: Unicast IPv4 to primary MAC address               [ OK ]
TEST: VLAN upper: Unicast IPv4 to macvlan MAC address               [ OK ]
TEST: VLAN upper: Unicast IPv4 to unknown MAC address               [ OK ]
TEST: VLAN upper: Unicast IPv4 to unknown MAC address, promisc      [ OK ]
TEST: VLAN upper: Unicast IPv4 to unknown MAC address, allmulti     [ OK ]
TEST: VLAN upper: Multicast IPv4 to joined group                    [ OK ]
TEST: VLAN upper: Multicast IPv4 to unknown group                   [XFAIL]
        reception succeeded, but should have failed
TEST: VLAN upper: Multicast IPv4 to unknown group, promisc          [ OK ]
TEST: VLAN upper: Multicast IPv4 to unknown group, allmulti         [ OK ]
TEST: VLAN upper: Multicast IPv6 to joined group                    [ OK ]
TEST: VLAN upper: Multicast IPv6 to unknown group                   [XFAIL]
        reception succeeded, but should have failed
TEST: VLAN upper: Multicast IPv6 to unknown group, promisc          [ OK ]
TEST: VLAN upper: Multicast IPv6 to unknown group, allmulti         [ OK ]
TEST: VLAN upper: 1588v2 over L2 transport, Sync                    [ OK ]
TEST: VLAN upper: 1588v2 over L2 transport, Follow-Up               [FAIL]
        reception failed
TEST: VLAN upper: 1588v2 over L2 transport, Peer Delay Request      [ OK ]
TEST: VLAN upper: 1588v2 over IPv4, Sync                            [FAIL]
        reception failed
;TEST: VLAN upper: 1588v2 over IPv4, Follow-Up                       [FAIL]
        reception failed
TEST: VLAN upper: 1588v2 over IPv4, Peer Delay Request              [FAIL]
        reception failed
TEST: VLAN upper: 1588v2 over IPv6, Sync                            [FAIL]
        reception failed
TEST: VLAN upper: 1588v2 over IPv6, Follow-Up                       [FAIL]
        reception failed
TEST: VLAN upper: 1588v2 over IPv6, Peer Delay Request              [FAIL]
        reception failed
TEST: VLAN over vlan_filtering=0 bridged port: Unicast IPv4 to primary MAC address   [ OK ]
TEST: VLAN over vlan_filtering=0 bridged port: Unicast IPv4 to macvlan MAC address   [ OK ]
TEST: VLAN over vlan_filtering=0 bridged port: Unicast IPv4 to unknown MAC address   [ OK ]
TEST: VLAN over vlan_filtering=0 bridged port: Unicast IPv4 to unknown MAC address, promisc   [ OK ]
TEST: VLAN over vlan_filtering=0 bridged port: Unicast IPv4 to unknown MAC address, allmulti   [ OK ]
TEST: VLAN over vlan_filtering=0 bridged port: Multicast IPv4 to joined group   [ OK ]
TEST: VLAN over vlan_filtering=0 bridged port: Multicast IPv4 to unknown group   [XFAIL]
        reception succeeded, but should have failed
TEST: VLAN over vlan_filtering=0 bridged port: Multicast IPv4 to unknown group, promisc   [ OK ]
TEST: VLAN over vlan_filtering=0 bridged port: Multicast IPv4 to unknown group, allmulti   [ OK ]
TEST: VLAN over vlan_filtering=0 bridged port: Multicast IPv6 to joined group   [ OK ]
TEST: VLAN over vlan_filtering=0 bridged port: Multicast IPv6 to unknown group   [XFAIL]
        reception succeeded, but should have failed
TEST: VLAN over vlan_filtering=0 bridged port: Multicast IPv6 to unknown group, promisc   [ OK ]
TEST: VLAN over vlan_filtering=0 bridged port: Multicast IPv6 to unknown group, allmulti   [ OK ]
TEST: VLAN over vlan_filtering=0 bridged port: 1588v2 over L2 transport, Sync   [ OK ]
TEST: VLAN over vlan_filtering=0 bridged port: 1588v2 over L2 transport, Follow-Up   [ OK ]
TEST: VLAN over vlan_filtering=0 bridged port: 1588v2 over L2 transport, Peer Delay Request   [ OK ]
TEST: VLAN over vlan_filtering=0 bridged port: 1588v2 over IPv4, Sync   [FAIL]
        reception failed
TEST: VLAN over vlan_filtering=0 bridged port: 1588v2 over IPv4, Follow-Up   [FAIL]
        reception failed
TEST: VLAN over vlan_filtering=0 bridged port: 1588v2 over IPv4, Peer Delay Request   [FAIL]
        reception failed
TEST: VLAN over vlan_filtering=0 bridged port: 1588v2 over IPv6, Sync   [FAIL]
        reception failed
TEST: VLAN over vlan_filtering=0 bridged port: 1588v2 over IPv6, Follow-Up   [FAIL]
        reception failed
TEST: VLAN over vlan_filtering=0 bridged port: 1588v2 over IPv6, Peer Delay Request   [FAIL]
        reception failed
TEST: VLAN over vlan_filtering=1 bridged port: Unicast IPv4 to primary MAC address   [ OK ]
TEST: VLAN over vlan_filtering=1 bridged port: Unicast IPv4 to macvlan MAC address   [ OK ]
TEST: VLAN over vlan_filtering=1 bridged port: Unicast IPv4 to unknown MAC address   [FAIL]
        reception succeeded, but should have failed
TEST: VLAN over vlan_filtering=1 bridged port: Unicast IPv4 to unknown MAC address, promisc   [ OK ]
TEST: VLAN over vlan_filtering=1 bridged port: Unicast IPv4 to unknown MAC address, allmulti   [FAIL]
        reception succeeded, but should have failed
TEST: VLAN over vlan_filtering=1 bridged port: Multicast IPv4 to joined group   [ OK ]
TEST: VLAN over vlan_filtering=1 bridged port: Multicast IPv4 to unknown group   [XFAIL]
        reception succeeded, but should have failed
TEST: VLAN over vlan_filtering=1 bridged port: Multicast IPv4 to unknown group, promisc   [ OK ]
TEST: VLAN over vlan_filtering=1 bridged port: Multicast IPv4 to unknown group, allmulti   [ OK ]
TEST: VLAN over vlan_filtering=1 bridged port: Multicast IPv6 to joined group   [ OK ]
TEST: VLAN over vlan_filtering=1 bridged port: Multicast IPv6 to unknown group   [XFAIL]
        reception succeeded, but should have failed
TEST: VLAN over vlan_filtering=1 bridged port: Multicast IPv6 to unknown group, promisc   [ OK ]
TEST: VLAN over vlan_filtering=1 bridged port: Multicast IPv6 to unknown group, allmulti   [ OK ]
TEST: VLAN over vlan_filtering=1 bridged port: 1588v2 over L2 transport, Sync   [ OK ]
TEST: VLAN over vlan_filtering=1 bridged port: 1588v2 over L2 transport, Follow-Up   [ OK ]
TEST: VLAN over vlan_filtering=1 bridged port: 1588v2 over L2 transport, Peer Delay Request   [ OK ]
TEST: VLAN over vlan_filtering=1 bridged port: 1588v2 over IPv4, Sync   [FAIL]
        reception failed
TEST: VLAN over vlan_filtering=1 bridged port: 1588v2 over IPv4, Follow-Up   [FAIL]
        reception failed
TEST: VLAN over vlan_filtering=1 bridged port: 1588v2 over IPv4, Peer Delay Request   [FAIL]
        reception failed
TEST: VLAN over vlan_filtering=1 bridged port: 1588v2 over IPv6, Sync   [FAIL]
        reception failed
TEST: VLAN over vlan_filtering=1 bridged port: 1588v2 over IPv6, Follow-Up   [FAIL]
        reception failed
TEST: VLAN over vlan_filtering=1 bridged port: 1588v2 over IPv6, Peer Delay Request   [FAIL]
        reception failed
TEST: VLAN over vlan_filtering=0 bridge: Unicast IPv4 to primary MAC address   [ OK ]
TEST: VLAN over vlan_filtering=0 bridge: Unicast IPv4 to macvlan MAC address   [ OK ]
TEST: VLAN over vlan_filtering=0 bridge: Unicast IPv4 to unknown MAC address   [ OK ]
TEST: VLAN over vlan_filtering=0 bridge: Unicast IPv4 to unknown MAC address, promisc   [ OK ]
TEST: VLAN over vlan_filtering=0 bridge: Unicast IPv4 to unknown MAC address, allmulti   [ OK ]
TEST: VLAN over vlan_filtering=0 bridge: Multicast IPv4 to joined group   [ OK ]
TEST: VLAN over vlan_filtering=0 bridge: Multicast IPv4 to unknown group   [XFAIL]
        reception succeeded, but should have failed
TEST: VLAN over vlan_filtering=0 bridge: Multicast IPv4 to unknown group, promisc   [ OK ]
TEST: VLAN over vlan_filtering=0 bridge: Multicast IPv4 to unknown group, allmulti   [ OK ]
TEST: VLAN over vlan_filtering=0 bridge: Multicast IPv6 to joined group   [ OK ]
TEST: VLAN over vlan_filtering=0 bridge: Multicast IPv6 to unknown group   [XFAIL]
        reception succeeded, but should have failed
TEST: VLAN over vlan_filtering=0 bridge: Multicast IPv6 to unknown group, promisc   [ OK ]
TEST: VLAN over vlan_filtering=0 bridge: Multicast IPv6 to unknown group, allmulti   [ OK ]
TEST: VLAN over vlan_filtering=1 bridge: Unicast IPv4 to primary MAC address   [ OK ]
TEST: VLAN over vlan_filtering=1 bridge: Unicast IPv4 to macvlan MAC address   [ OK ]
TEST: VLAN over vlan_filtering=1 bridge: Unicast IPv4 to unknown MAC address   [ OK ]
TEST: VLAN over vlan_filtering=1 bridge: Unicast IPv4 to unknown MAC address, promisc   [ OK ]
TEST: VLAN over vlan_filtering=1 bridge: Unicast IPv4 to unknown MAC address, allmulti   [ OK ]
TEST: VLAN over vlan_filtering=1 bridge: Multicast IPv4 to joined group   [ OK ]
TEST: VLAN over vlan_filtering=1 bridge: Multicast IPv4 to unknown group   [XFAIL]
        reception succeeded, but should have failed
TEST: VLAN over vlan_filtering=1 bridge: Multicast IPv4 to unknown group, promisc   [ OK ]
TEST: VLAN over vlan_filtering=1 bridge: Multicast IPv4 to unknown group, allmulti   [ OK ]
TEST: VLAN over vlan_filtering=1 bridge: Multicast IPv6 to joined group   [ OK ]
TEST: VLAN over vlan_filtering=1 bridge: Multicast IPv6 to unknown group   [XFAIL]
        reception succeeded, but should have failed
TEST: VLAN over vlan_filtering=1 bridge: Multicast IPv6 to unknown group, promisc   [ OK ]
TEST: VLAN over vlan_filtering=1 bridge: Multicast IPv6 to unknown group, allmulti   [ OK ]

Output bridge_vlan_unaware.sh
TEST: ping                                                          [ OK ]
TEST: ping6                                                         [ OK ]
TEST: FDB learning                                                  [ OK ]
TEST: Unknown unicast flood                                         [ OK ]
TEST: Unregistered multicast flood                                  [ OK ]

Output bridge_vlan_aware.sh
TEST: ping                                                          [ OK ]
TEST: ping6                                                         [ OK ]
TEST: FDB learning                                                  [ OK ]
TEST: Unknown unicast flood                                         [ OK ]
TEST: Unregistered multicast flood                                  [ OK ]
INFO: Add and delete a VLAN on bridge port lan2
TEST: ping                                                          [ OK ]
TEST: ping6                                                         [ OK ]
TEST: Externally learned FDB entry - ageing & roaming               [ OK ]
TEST: FDB entry in PVID for VLAN-tagged with other TPID             [FAIL]
        FDB entry was not learned when it should
TEST: Reception of VLAN with other TPID as untagged                 [FAIL]
        Packet was not forwarded when it should
TEST: Reception of VLAN with other TPID as untagged (no PVID)       [FAIL]
        Packet was forwarded when should not

Changes v23:
- Add review by tag for DT patch
- Fix MFD fwnode handle release
- Better handle LPI handling for AN8855
- Add additional kconfig for AN8855
- Use shorter name for virtual phy bus

Changes v22:
- Improve MFD lock handling for phy bus
- Prevent devm crash on removal for MFD driver
- Address VAWD bug reported by bot
- Fix wrong msb for MIB for AN8855 driver
- Better handle kconfig dependency
- Read tx_lpi under lock

Changes v21:
- Rebase on top of net-next
- Drop megred patch from Daniel
- Address suggestion reported by bot for MFD driver
- Drop reset for MFD driver
- Reset FDB and VLAN data on writing
- Fix not correct PCR matrix in port enable
- Add ID_EN7528 fields
- Fix MAC address learning SA_DIS
- Fix MAC address FDB read swapped
- Fix mib reset logic
- Fix AN8855 missing regfiled
- Fix AN8855 ethtool stats access
- Improve tx lpi timer for AN8855
- Improve MFD Documentation patch
Changes v20:
- Address all the typo pointed out by bot
- Make documentation schema more consistent
- Address some concern for the mfd driver from bot
- Fix some conversion problem for the generalization patch
Changes v19:
- Rebase on top of net-next
- Rework with shared function from mt7530 driver
- Add dependency for mt7530 lock
- Fix some define typo for AN8855
Changes v18:
- Fix configurting typo
- Init ret in MFD driver
Changes v17:
- Drop nvmem patch (subset merged and present in linux-next)
- Fix wrong Documentation patch for MFD
- Address reviews for MFD driver
- Rework MTK tag to slipt for Airoha name
Changes v16:
- Rebase on top of net-next
- Drop PBUS implementation (Airoha said that it's not OK to use it)
- Convert to simple mdio-regmap and split regmap
- Fix typo for some define (AND8855 -> AN8855)
Changes v15:
- Rebase on top of net-next
- Drop regmap MDIO patch (in favor of PBUS)
- Implement MDIO PBUS and rework MDIO driver/MFD
- Reimplement EEE support
- Add some check for regmap from MFD
- Move to single regmap and add comments with all findings
Changes v14:
- Move MAITAINERS entry to dedicated commit (make it easier for cross
  subsystem merge)
- Pack variables in trap function
- Add additional patch for reported difference from MTK tag
Changes v13:
- Reimplement tx_lpi OPs
- Rework mdio-regmap to internally encode/decode address
- Fix error in Documentation
- Drop ext-surge property (assume calibration with declared nvmem cell)
- Fix comments from Lee on MFD driver
- Improve print error and drop extra space in DSA driver
Changes v12:
- Update on top of net-next
- Add additional info on conver-letter about slefttests and HW limitation
- Introduce mdio-regmap generalization for multiple address
- Drop dev flags and define PHY calibration in PHY node directly
Changes v11:
- Address reviews from Christophe (spell mistake + dev_err_probe)
- Fix kconfig dependency for MFD driver (depends on MDIO_DEVICE instead of MDIO)
  (indirectly fix link error for mdio APIs)
- Fix copy-paste error for MFD driver of_table
- Fix compilation error for PHY (move NVMEM to .config)
- Drop unneeded NVMEM node from MDIO example schema (from Andrew)
- Adapt MFD example schema to MDIO reg property restrictions
Changes v10:
- Entire rework to MFD + split to MDIO, EFUSE, SWITCH separate drivers
- Drop EEE OPs (while Russell finish RFC for EEE changes)
- Use new pcs_inpand OPs
- Drop AN restart function and move to pcs_config
- Enable assisted_learning and disable CPU learn (preparation for fdb_isolation)
- Move EFUSE read in Internal PHY driver to .config to handle EPROBE_DEFER
  (needed now that NVMEM driver is register externally instead of internally to switch
   node)
Changes v9:
- Error out on using 5G speed as currently not supported
- Add missing MAC_2500FD in phylink mac_capabilities
- Add comment and improve if condition for an8855_phylink_mac_config
Changes v8:
- Add port Fast Age support
- Add support for Port Isolation
- Use correct register for Learning Disable
- Add support for Ageing Time OP
- Set default PVID to 0 by default
- Add mdb OPs
- Add port change MTU
- Fix support for Upper VLAN
Changes v7:
- Fix devm_dsa_register_switch wrong export symbol
Changes v6:
- Drop standard MIB and handle with ethtool OPs (as requested by Jakub)
- Cosmetic: use bool instead of 0 or 1
Changes v5:
- Add devm_dsa_register_switch() patch
- Add Reviewed-by tag for DT patch
Changes v4:
- Set regmap readable_table static (mute compilation warning)
- Add support for port_bridge flags (LEARNING, FLOOD)
- Reset fdb struct in fdb_dump
- Drop support_asym_pause in port_enable
- Add define for get_phy_flags
- Fix bug for port not inititially part of a bridge
  (in an8855_setup the port matrix was always cleared but
   the CPU port was never initially added)
- Disable learning and flood for user port by default
- Set CPU port to flood and learning by default
- Correctly AND force duplex and flow control in an8855_phylink_mac_link_up
- Drop RGMII from pcs_config
- Check ret in "Disable AN if not in autoneg"
- Use devm_mutex_init
- Fix typo for AN8855_PORT_CHECK_MODE
- Better define AN8855_STP_LISTENING = AN8855_STP_BLOCKING
- Fix typo in AN8855_PHY_EN_DOWN_SHIFT
- Use paged helper for PHY
- Skip calibration in config_init if priv not defined
Changes v3:
- Out of RFC
- Switch PHY code to select_page API
- Better describe masks and bits in PHY driver for ADC register
- Drop raw values and use define for mii read/write
- Switch to absolute PHY address
- Replace raw values with mask and bits for pcs_config
- Fix typo for ext-surge property name
- Drop support for relocating Switch base PHY address on the bus
Changes v2:
- Drop mutex guard patch
- Drop guard usage in DSA driver
- Use __mdiobus_write/read
- Check return condition and return errors for mii read/write
- Fix wrong logic for EEE
- Fix link_down (don't force link down with autoneg)
- Fix forcing speed on sgmii autoneg
- Better document link speed for sgmii reg
- Use standard define for sgmii reg
- Imlement nvmem support to expose switch EFUSE
- Rework PHY calibration with the use of NVMEM producer/consumer
- Update DT with new NVMEM property
- Move aneg validation for 2500-basex in pcs_config
- Move r50Ohm table and function to PHY driver

Christian Marangi (9):
  dt-bindings: net: dsa: Document support for Airoha AN8855 DSA Switch
  dt-bindings: net: Document support for AN8855 Switch Internal PHY
  dt-bindings: mfd: Document support for Airoha AN8855 Switch SoC
  mfd: an8855: Add support for Airoha AN8855 Switch
  net: phy: Add Airoha AN8855 Internal Switch Gigabit PHY
  net: dsa: tag_mtk: add Airoha variant usage of this TAG
  MAINTAINERS: add myself as maintainer for Airoha AN8855 Switch
  net: dsa: mt7530: generalize and move common function to lib module
  net: dsa: Add Airoha AN8855 5-Port Gigabit DSA Switch driver

 .../bindings/mfd/airoha,an8855.yaml           |  176 ++
 .../bindings/net/airoha,an8855-phy.yaml       |   83 +
 .../net/dsa/airoha,an8855-switch.yaml         |   86 +
 MAINTAINERS                                   |   16 +
 drivers/mfd/Kconfig                           |   14 +
 drivers/mfd/Makefile                          |    1 +
 drivers/mfd/airoha-an8855.c                   |  580 ++++++
 drivers/net/dsa/Kconfig                       |   14 +
 drivers/net/dsa/Makefile                      |    2 +
 drivers/net/dsa/an8855.c                      | 1740 +++++++++++++++++
 drivers/net/dsa/an8855.h                      |  755 +++++++
 drivers/net/dsa/mt7530-lib.c                  | 1156 +++++++++++
 drivers/net/dsa/mt7530-lib.h                  |  413 ++++
 drivers/net/dsa/mt7530-mdio.c                 |    4 +
 drivers/net/dsa/mt7530-mmio.c                 |    4 +
 drivers/net/dsa/mt7530.c                      | 1368 +++----------
 drivers/net/dsa/mt7530.h                      |  256 +--
 drivers/net/phy/Kconfig                       |    6 +
 drivers/net/phy/Makefile                      |    1 +
 drivers/net/phy/air_an8855.c                  |  275 +++
 include/net/dsa.h                             |    2 +
 net/dsa/Kconfig                               |   11 +
 net/dsa/Makefile                              |    2 +-
 net/dsa/tag_mtk.c                             |   36 +-
 24 files changed, 5754 insertions(+), 1247 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/mfd/airoha,an8855.yaml
 create mode 100644 Documentation/devicetree/bindings/net/airoha,an8855-phy.yaml
 create mode 100644 Documentation/devicetree/bindings/net/dsa/airoha,an8855-switch.yaml
 create mode 100644 drivers/mfd/airoha-an8855.c
 create mode 100644 drivers/net/dsa/an8855.c
 create mode 100644 drivers/net/dsa/an8855.h
 create mode 100644 drivers/net/dsa/mt7530-lib.c
 create mode 100644 drivers/net/dsa/mt7530-lib.h
 create mode 100644 drivers/net/phy/air_an8855.c

-- 
2.55.0

[PATCH net-next v23 1/9] dt-bindings: net: dsa: Document support for Airoha AN8855 DSA Switch

[Christian Marangi]

Document support for Airoha AN8855 5-port Gigabit Switch.

It does expose the 5 Internal PHYs on the MDIO bus and each port
can access the Switch register space by configuring the PHY page.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
---
 .../net/dsa/airoha,an8855-switch.yaml         | 86 +++++++++++++++++++
 1 file changed, 86 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/net/dsa/airoha,an8855-switch.yaml

diff --git a/Documentation/devicetree/bindings/net/dsa/airoha,an8855-switch.yaml b/Documentation/devicetree/bindings/net/dsa/airoha,an8855-switch.yaml
new file mode 100644
index 000000000000..5ad9b9e13983
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/dsa/airoha,an8855-switch.yaml
@@ -0,0 +1,86 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/net/dsa/airoha,an8855-switch.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Airoha AN8855 Gigabit Switch
+
+maintainers:
+  - Christian Marangi <ansuelsmth@gmail.com>
+
+description: >
+  Airoha AN8855 is a 5-port Gigabit Switch.
+
+  It does expose the 5 Internal PHYs on the MDIO bus and each port
+  can access the Switch register space by configuring the PHY page.
+
+$ref: dsa.yaml#/$defs/ethernet-ports
+
+properties:
+  compatible:
+    const: airoha,an8855-switch
+
+required:
+  - compatible
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    ethernet-switch {
+        compatible = "airoha,an8855-switch";
+
+        ports {
+            #address-cells = <1>;
+            #size-cells = <0>;
+
+            port@0 {
+                reg = <0>;
+                label = "lan1";
+                phy-mode = "internal";
+                phy-handle = <&internal_phy1>;
+            };
+
+            port@1 {
+                reg = <1>;
+                label = "lan2";
+                phy-mode = "internal";
+                phy-handle = <&internal_phy2>;
+            };
+
+            port@2 {
+                reg = <2>;
+                label = "lan3";
+                phy-mode = "internal";
+                phy-handle = <&internal_phy3>;
+            };
+
+            port@3 {
+                reg = <3>;
+                label = "lan4";
+                phy-mode = "internal";
+                phy-handle = <&internal_phy4>;
+            };
+
+            port@4 {
+                reg = <4>;
+                label = "wan";
+                phy-mode = "internal";
+                phy-handle = <&internal_phy5>;
+            };
+
+            port@5 {
+                reg = <5>;
+                label = "cpu";
+                ethernet = <&gmac0>;
+                phy-mode = "2500base-x";
+
+                fixed-link {
+                    speed = <2500>;
+                    full-duplex;
+                    pause;
+                };
+            };
+        };
+    };
-- 
2.55.0

[PATCH net-next v23 2/9] dt-bindings: net: Document support for AN8855 Switch Internal PHY

[Christian Marangi]

Document support for AN8855 Switch Internal PHY.

Airoha AN8855 is a 5-port Gigabit Switch that expose the Internal
PHYs on the MDIO bus.

Each PHY might need to be calibrated to correctly work with the
use of the eFUSE provided by the Switch SoC. This can be enabled by
defining in the PHY node the NVMEM cell properties.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
---
 .../bindings/net/airoha,an8855-phy.yaml       | 83 +++++++++++++++++++
 1 file changed, 83 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/net/airoha,an8855-phy.yaml

diff --git a/Documentation/devicetree/bindings/net/airoha,an8855-phy.yaml b/Documentation/devicetree/bindings/net/airoha,an8855-phy.yaml
new file mode 100644
index 000000000000..d2f86116badf
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/airoha,an8855-phy.yaml
@@ -0,0 +1,83 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/net/airoha,an8855-phy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Airoha AN8855 Switch Internal PHY
+
+maintainers:
+  - Christian Marangi <ansuelsmth@gmail.com>
+
+description: >
+  Airoha AN8855 is a 5-port Gigabit Switch that expose the Internal
+  PHYs on the MDIO bus.
+
+  Each PHY might need to be calibrated to correctly work with the
+  use of the eFUSE provided by the Switch SoC.
+
+allOf:
+  - $ref: ethernet-phy.yaml#
+
+select:
+  properties:
+    compatible:
+      contains:
+        enum:
+          - ethernet-phy-idc0ff.0410
+  required:
+    - compatible
+
+properties:
+  reg:
+    maxItems: 1
+
+  nvmem-cells:
+    items:
+      - description: phandle to SoC eFUSE tx_a
+      - description: phandle to SoC eFUSE tx_b
+      - description: phandle to SoC eFUSE tx_c
+      - description: phandle to SoC eFUSE tx_d
+
+  nvmem-cell-names:
+    items:
+      - const: tx_a
+      - const: tx_b
+      - const: tx_c
+      - const: tx_d
+
+required:
+  - compatible
+  - reg
+
+dependentRequired:
+  nvmem-cells: [ nvmem-cell-names ]
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    mdio {
+        #address-cells = <1>;
+        #size-cells = <0>;
+
+        ethernet-phy@1 {
+            compatible = "ethernet-phy-idc0ff.0410",
+                         "ethernet-phy-ieee802.3-c45";
+
+            reg = <1>;
+        };
+
+        ethernet-phy@2 {
+            compatible = "ethernet-phy-idc0ff.0410",
+                         "ethernet-phy-ieee802.3-c45";
+
+            reg = <2>;
+
+            nvmem-cells = <&shift_sel_port0_tx_a>,
+                          <&shift_sel_port0_tx_b>,
+                          <&shift_sel_port0_tx_c>,
+                          <&shift_sel_port0_tx_d>;
+            nvmem-cell-names = "tx_a", "tx_b", "tx_c", "tx_d";
+        };
+    };
-- 
2.55.0

Re: [PATCH net-next v23 2/9] dt-bindings: net: Document support for AN8855 Switch Internal PHY

[netdev-bot+sashiko]

Thank you for your contribution! Sashiko AI review found 2 potential
issue(s) to consider.

Critical: 0 · High: 0 · Medium: 1 · Low: 1

If you believe none of the issues are legitimate, please reply to each
issue of Medium severity or higher and explain why the AI is wrong.
If any of them are legitimate and you plan to respin, please let patchwork
know by including "pw-bot: cr" as a separate line at the end of your reply
(one such reply per series is enough).

- [Medium] Both PHY nodes in the example of the new binding
  Documentation/devicetree/bindings/net/airoha,an8855-phy.yaml…
- [Low] In the example of
  Documentation/devicetree/bindings/net/airoha,an8855-phy.yaml, the PHY…

--

dt-bindings: net: Document support for AN8855 Switch Internal PHY

This adds a binding for the internal PHYs of the Airoha AN8855 5-port
Gigabit switch, which are exposed on the MDIO bus. It also documents
optional nvmem-cells, which point at eFUSE cells used to calibrate each
PHY.

> diff --git a/Documentation/devicetree/bindings/net/airoha,an8855-phy.yaml b/Documentation/devicetree/bindings/net/airoha,an8855-phy.yaml
> new file mode 100644
> index 0000000000000..d2f86116badf4
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/net/airoha,an8855-phy.yaml

[ ... ]

> +examples:
> +  - |
> +    mdio {
> +        #address-cells = <1>;
> +        #size-cells = <0>;
> +
> +        ethernet-phy@1 {
> +            compatible = "ethernet-phy-idc0ff.0410",
> +                         "ethernet-phy-ieee802.3-c45";

[Severity: Medium]
Should this be "ethernet-phy-ieee802.3-c22"? The same pair is used for
ethernet-phy@2 below.

The rest of the series treats these PHYs as Clause 22 only. The MFD
binding in mfd/airoha,an8855.yaml uses "ethernet-phy-ieee802.3-c22" for
the same PHYs. The PHY driver in drivers/net/phy/air_an8855.c relies on
Clause 22 register 0x1f paging and has no Clause 45 callbacks.

When the c45 compatible is present, fwnode_mdiobus_register_phy()
ignores the fixed PHY ID:

drivers/net/mdio/fwnode_mdio.c:fwnode_mdiobus_register_phy() {
    ...
	is_c45 = fwnode_device_is_compatible(child, "ethernet-phy-ieee802.3-c45");
	if (is_c45 || fwnode_get_phy_id(child, &phy_id))
		phy = get_phy_device(bus, addr, is_c45);
    ...
}

The per-PHY buses that an8855_core_probe() creates come from
devm_mdio_regmap_register(). That function only sets Clause 22
accessors:

drivers/net/mdio/mdio-regmap.c:devm_mdio_regmap_register() {
    ...
	mii->read = mdio_regmap_read_c22;
	mii->write = mdio_regmap_write_c22;
    ...
}

Since read_c45 is never set, this chain fails:

get_phy_device(bus, addr, true)
  get_phy_c45_ids()
    mdiobus_c45_read() -> -EOPNOTSUPP
  -> -EIO

After that, fwnode_mdiobus_register_phy() fails and an8855_core_probe()
jumps to err_put_fwnodes. The whole AN8855 MFD then fails to probe,
including the switch and the efuse.

The schema accepts either compatible, so dt_binding_check won't catch
a board DT that copies this example.

> +
> +            reg = <1>;
> +        };
> +
> +        ethernet-phy@2 {
> +            compatible = "ethernet-phy-idc0ff.0410",
> +                         "ethernet-phy-ieee802.3-c45";
> +
> +            reg = <2>;
> +
> +            nvmem-cells = <&shift_sel_port0_tx_a>,
> +                          <&shift_sel_port0_tx_b>,
> +                          <&shift_sel_port0_tx_c>,
> +                          <&shift_sel_port0_tx_d>;

[Severity: Low]
Is ethernet-phy@2 meant to get the port 0 calibration cells here?

Later in the series, an8855_phy_bus_register() maps a PHY to a switch
port with phy_offset = addr - priv->switch_addr. This example also has
a PHY at address 1, so ethernet-phy@2 can't be port 0.

The sibling bindings agree:

- dsa/airoha,an8855-switch.yaml maps port@0 to internal_phy1 and port@1
  to internal_phy2.
- mfd/airoha,an8855.yaml puts the shift_sel_port0_* cells on
  ethernet-phy@1 and the shift_sel_port1_* cells on ethernet-phy@2.

an8855_config_init() writes whatever cells it gets into
AN8855_PHY_R50OHM_RSEL_TX_AB/CD. If a board DT copies this example, the
port 1 PHY would silently get the port 0 TX calibration.

Should the cells either move to ethernet-phy@1, or be renamed to
shift_sel_port1_*?

> +            nvmem-cell-names = "tx_a", "tx_b", "tx_c", "tx_d";
> +        };
> +    };

-- 
Sashiko AI review · https://netdev-ai.bots.linux.dev/sashiko/#/patchset/20260925182435.21207-1-ansuelsmth%40gmail.com

[PATCH net-next v23 3/9] dt-bindings: mfd: Document support for Airoha AN8855 Switch SoC

[Christian Marangi]

Document support for Airoha AN8855 Switch SoC. This SoC expose various
peripherals like an Ethernet Switch, a NVMEM provider and Ethernet PHYs.

It does also support i2c and timers but those are not currently
supported/used.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
---
 .../bindings/mfd/airoha,an8855.yaml           | 176 ++++++++++++++++++
 1 file changed, 176 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/mfd/airoha,an8855.yaml

diff --git a/Documentation/devicetree/bindings/mfd/airoha,an8855.yaml b/Documentation/devicetree/bindings/mfd/airoha,an8855.yaml
new file mode 100644
index 000000000000..48127e956c96
--- /dev/null
+++ b/Documentation/devicetree/bindings/mfd/airoha,an8855.yaml
@@ -0,0 +1,176 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mfd/airoha,an8855.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Airoha AN8855 Switch SoC
+
+maintainers:
+  - Christian Marangi <ansuelsmth@gmail.com>
+
+description: >
+  Airoha AN8855 Switch is a SoC that expose various peripherals like an
+  Ethernet Switch, a NVMEM provider and Ethernet PHYs.
+
+  It does also support i2c and timers but those are not currently
+  supported/used.
+
+properties:
+  compatible:
+    const: airoha,an8855
+
+  reg:
+    maxItems: 1
+
+  reset-gpios:
+    maxItems: 1
+
+  efuse:
+    type: object
+    $ref: /schemas/nvmem/airoha,an8855-efuse.yaml
+    description: EFUSE exposed by the Airoha AN8855 SoC
+
+  ethernet-switch:
+    type: object
+    $ref: /schemas/net/dsa/airoha,an8855-switch.yaml
+    description: Switch exposed by the Airoha AN8855 SoC
+
+  mdio:
+    type: object
+    $ref: /schemas/net/mdio.yaml#
+    description: MDIO exposed by the Airoha AN8855 SoC
+    unevaluatedProperties: false
+
+required:
+  - compatible
+  - reg
+  - mdio
+  - ethernet-switch
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/gpio/gpio.h>
+
+    mdio {
+        #address-cells = <1>;
+        #size-cells = <0>;
+
+        soc@1 {
+            compatible = "airoha,an8855";
+            reg = <1>;
+
+            reset-gpios = <&pio 39 GPIO_ACTIVE_HIGH>;
+
+            efuse {
+                compatible = "airoha,an8855-efuse";
+
+                #nvmem-cell-cells = <0>;
+
+                nvmem-layout {
+                    compatible = "fixed-layout";
+                    #address-cells = <1>;
+                    #size-cells = <1>;
+
+                    shift_sel_port0_tx_a: shift-sel-port0-tx-a@c {
+                       reg = <0xc 0x4>;
+                    };
+
+                    shift_sel_port0_tx_b: shift-sel-port0-tx-b@10 {
+                        reg = <0x10 0x4>;
+                    };
+
+                    shift_sel_port0_tx_c: shift-sel-port0-tx-c@14 {
+                        reg = <0x14 0x4>;
+                    };
+
+                    shift_sel_port0_tx_d: shift-sel-port0-tx-d@18 {
+                       reg = <0x18 0x4>;
+                    };
+
+                    shift_sel_port1_tx_a: shift-sel-port1-tx-a@1c {
+                        reg = <0x1c 0x4>;
+                    };
+
+                    shift_sel_port1_tx_b: shift-sel-port1-tx-b@20 {
+                        reg = <0x20 0x4>;
+                    };
+
+                    shift_sel_port1_tx_c: shift-sel-port1-tx-c@24 {
+                       reg = <0x24 0x4>;
+                    };
+
+                    shift_sel_port1_tx_d: shift-sel-port1-tx-d@28 {
+                        reg = <0x28 0x4>;
+                    };
+                };
+            };
+
+            ethernet-switch {
+                compatible = "airoha,an8855-switch";
+
+                ports {
+                    #address-cells = <1>;
+                    #size-cells = <0>;
+
+                    port@0 {
+                        reg = <0>;
+                        label = "lan1";
+                        phy-mode = "internal";
+                        phy-handle = <&internal_phy1>;
+                    };
+
+                    port@1 {
+                        reg = <1>;
+                        label = "lan2";
+                        phy-mode = "internal";
+                        phy-handle = <&internal_phy2>;
+                    };
+
+                    port@5 {
+                        reg = <5>;
+                        label = "cpu";
+                        ethernet = <&gmac0>;
+                        phy-mode = "2500base-x";
+
+                        fixed-link {
+                            speed = <2500>;
+                            full-duplex;
+                            pause;
+                        };
+                    };
+                };
+            };
+
+            mdio {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                internal_phy1: ethernet-phy@1 {
+                  compatible = "ethernet-phy-idc0ff.0410",
+                               "ethernet-phy-ieee802.3-c22";
+                  reg = <1>;
+
+                  nvmem-cells = <&shift_sel_port0_tx_a>,
+                      <&shift_sel_port0_tx_b>,
+                      <&shift_sel_port0_tx_c>,
+                      <&shift_sel_port0_tx_d>;
+                  nvmem-cell-names = "tx_a", "tx_b", "tx_c", "tx_d";
+                };
+
+                internal_phy2: ethernet-phy@2 {
+                  compatible = "ethernet-phy-idc0ff.0410",
+                               "ethernet-phy-ieee802.3-c22";
+                  reg = <2>;
+
+                  nvmem-cells = <&shift_sel_port1_tx_a>,
+                      <&shift_sel_port1_tx_b>,
+                      <&shift_sel_port1_tx_c>,
+                      <&shift_sel_port1_tx_d>;
+                  nvmem-cell-names = "tx_a", "tx_b", "tx_c", "tx_d";
+                };
+            };
+        };
+    };
-- 
2.55.0

Re: [PATCH net-next v23 3/9] dt-bindings: mfd: Document support for Airoha AN8855 Switch SoC

[netdev-bot+sashiko]

Thank you for your contribution! Sashiko AI review found 1 potential
issue(s) to consider.

Critical: 0 · High: 0 · Medium: 1 · Low: 0

If you believe none of the issues are legitimate, please reply to each
issue of Medium severity or higher and explain why the AI is wrong.
If any of them are legitimate and you plan to respin, please let patchwork
know by including "pw-bot: cr" as a separate line at the end of your reply
(one such reply per series is enough).

- [Medium] Two bindings added in this series disagree on which MDIO
  clause the same AN8855 internal PHY (ethernet-phy-idc0ff.0410) uses.

--

dt-bindings: mfd: Document support for Airoha AN8855 Switch SoC

This commit adds a DT binding for the Airoha AN8855 Switch SoC. The SoC
exposes an Ethernet switch, an efuse NVMEM provider and internal Ethernet
PHYs on an mdio subnode. The example shows the full layout, including the
nvmem cells the internal PHYs use.

> diff --git a/Documentation/devicetree/bindings/mfd/airoha,an8855.yaml b/Documentation/devicetree/bindings/mfd/airoha,an8855.yaml
> new file mode 100644
> index 0000000000000..48127e956c965
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/mfd/airoha,an8855.yaml

[ ... ]

> +            mdio {
> +                #address-cells = <1>;
> +                #size-cells = <0>;
> +
> +                internal_phy1: ethernet-phy@1 {
> +                  compatible = "ethernet-phy-idc0ff.0410",
> +                               "ethernet-phy-ieee802.3-c22";

[Severity: Medium]
This example describes the internal PHY (ethernet-phy-idc0ff.0410) as
ethernet-phy-ieee802.3-c22. The PHY binding added later in this series,
Documentation/devicetree/bindings/net/airoha,an8855-phy.yaml, describes
the same PHY as ethernet-phy-ieee802.3-c45 in its ethernet-phy@1 and
ethernet-phy@2 examples. Which one is intended?

The drivers later in the series suggest c22 is correct. The MFD core
registers each PHY on an mdio-regmap bus, and devm_mdio_regmap_register()
sets up only the C22 ops:

drivers/net/mdio/mdio-regmap.c:devm_mdio_regmap_register() {
    ...
    mii->read = mdio_regmap_read_c22;
    mii->write = mdio_regmap_write_c22;
    ...
}

bus->read_c45 is never set.

Now take a board DT that copies the c45 example from the PHY binding.
an8855_core_probe() would register each PHY like this:

an8855_core_probe()
  fwnode_mdiobus_register_phy()      /* is_c45 = true */
    get_phy_device(bus, addr, true)
      get_phy_c45_ids()
        get_phy_c45_devs_in_pkg()
          mdiobus_c45_read()         /* -EOPNOTSUPP, no read_c45 */

get_phy_c45_devs_in_pkg() turns that error into -EIO. The failure then
goes through err_put_fwnodes in an8855_core_probe().

Wouldn't that fail the whole AN8855 core probe, and with it the switch
and efuse children? The schema can't catch this because both compatibles
are valid under ethernet-phy.yaml.

This example looks correct. Should the c45 examples in
airoha,an8855-phy.yaml be changed to c22 so the two bindings match?

> +                  reg = <1>;
> +
> +                  nvmem-cells = <&shift_sel_port0_tx_a>,
> +                      <&shift_sel_port0_tx_b>,
> +                      <&shift_sel_port0_tx_c>,
> +                      <&shift_sel_port0_tx_d>;
> +                  nvmem-cell-names = "tx_a", "tx_b", "tx_c", "tx_d";
> +                };
> +
> +                internal_phy2: ethernet-phy@2 {
> +                  compatible = "ethernet-phy-idc0ff.0410",
> +                               "ethernet-phy-ieee802.3-c22";

[ ... ]

-- 
Sashiko AI review · https://netdev-ai.bots.linux.dev/sashiko/#/patchset/20260925182435.21207-1-ansuelsmth%40gmail.com

[PATCH net-next v23 4/9] mfd: an8855: Add support for Airoha AN8855 Switch

[Christian Marangi]

Add support for Airoha AN8855 Switch that provide support for a DSA
switch and a NVMEM provider.

Also make use of the mdio-regmap driver and register a regmap for each
internal PHY of the switch.
This is needed to handle the double usage of the PHYs as both PHY and
Switch accessor.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
---
 drivers/mfd/Kconfig         |  14 +
 drivers/mfd/Makefile        |   1 +
 drivers/mfd/airoha-an8855.c | 580 ++++++++++++++++++++++++++++++++++++
 3 files changed, 595 insertions(+)
 create mode 100644 drivers/mfd/airoha-an8855.c

diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
index e4fd4572472f..afbdcec0fce8 100644
--- a/drivers/mfd/Kconfig
+++ b/drivers/mfd/Kconfig
@@ -54,6 +54,20 @@ config MFD_ALTERA_SYSMGR
 	  using regmap_mmio accesses for ARM32 parts and SMC calls to
 	  EL3 for ARM64 parts.
 
+config MFD_AIROHA_AN8855
+	tristate "Airoha AN8855 Switch Core"
+	select MFD_CORE
+	select REGMAP
+	select PHYLIB
+	select MDIO_REGMAP
+	depends on NETDEVICES && OF
+	help
+	  Support for the Airoha AN8855 Switch Core. This is an SoC
+	  that provides various peripherals, to count, i2c, an Ethrnet
+	  Switch, a CPU timer, GPIO, eFUSE.
+
+	  Currently it provides a DSA switch and a NVMEM provider.
+
 config MFD_ACT8945A
 	tristate "Active-semi ACT8945A"
 	select MFD_CORE
diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
index 72d3944b0ad8..484127dba2ad 100644
--- a/drivers/mfd/Makefile
+++ b/drivers/mfd/Makefile
@@ -8,6 +8,7 @@ obj-$(CONFIG_MFD_88PM860X)	+= 88pm860x.o
 obj-$(CONFIG_MFD_88PM800)	+= 88pm800.o 88pm80x.o
 obj-$(CONFIG_MFD_88PM805)	+= 88pm805.o 88pm80x.o
 obj-$(CONFIG_MFD_88PM886_PMIC)	+= 88pm886.o
+obj-$(CONFIG_MFD_AIROHA_AN8855)	+= airoha-an8855.o
 obj-$(CONFIG_MFD_ACT8945A)	+= act8945a.o
 obj-$(CONFIG_MFD_SM501)		+= sm501.o
 obj-$(CONFIG_ARCH_BCM2835)	+= bcm2835-pm.o
diff --git a/drivers/mfd/airoha-an8855.c b/drivers/mfd/airoha-an8855.c
new file mode 100644
index 000000000000..a2a36704a9fc
--- /dev/null
+++ b/drivers/mfd/airoha-an8855.c
@@ -0,0 +1,580 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Core driver for Airoha AN8855 Switch
+ *
+ * Copyright (C) 2024 Christian Marangi <ansuelsmth@gmail.com>
+ */
+
+#include <linux/bitfield.h>
+#include <linux/fwnode_mdio.h>
+#include <linux/gpio/consumer.h>
+#include <linux/mfd/core.h>
+#include <linux/mdio.h>
+#include <linux/mdio/mdio-regmap.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/phy.h>
+#include <linux/regmap.h>
+
+/* Register for HW trap status */
+#define AN8855_HWTRAP			0x1000009c
+
+/*
+ * Register of the Switch ID
+ * (called Project ID in Documentation)
+ */
+#define AN8855_CREV			0x10005000
+#define   AN8855_ID			0x8855 /* Switch ID */
+
+/* Register for GPHY Power Down
+ * Used to Toggle the Gigabit PHY power and enable them.
+ */
+#define AN8855_RG_GPHY_AFE_PWD		0x1028c840
+
+/* MII Registers */
+#define AN8855_PHY_SELECT_PAGE		0x1f
+#define   AN8855_PHY_PAGE		GENMASK(2, 0)
+#define   AN8855_PHY_PAGE_STANDARD	FIELD_PREP_CONST(AN8855_PHY_PAGE, 0x0)
+#define   AN8855_PHY_PAGE_EXTENDED_1	FIELD_PREP_CONST(AN8855_PHY_PAGE, 0x1)
+#define   AN8855_PHY_PAGE_EXTENDED_4	FIELD_PREP_CONST(AN8855_PHY_PAGE, 0x4)
+
+/* MII Registers Page 4 */
+#define AN8855_PBUS_MODE		0x10
+#define   AN8855_PBUS_MODE_ADDR_FIXED	0x0
+#define   AN8855_PBUS_MODE_ADDR_INCR	BIT(15)
+#define AN8855_PBUS_WR_ADDR_HIGH	0x11
+#define AN8855_PBUS_WR_ADDR_LOW		0x12
+#define AN8855_PBUS_WR_DATA_HIGH	0x13
+#define AN8855_PBUS_WR_DATA_LOW		0x14
+#define AN8855_PBUS_RD_ADDR_HIGH	0x15
+#define AN8855_PBUS_RD_ADDR_LOW		0x16
+#define AN8855_PBUS_RD_DATA_HIGH	0x17
+#define AN8855_PBUS_RD_DATA_LOW		0x18
+
+#define AN8855_MAX_PHY_PORT		5
+
+struct an8855_core_priv {
+	struct mii_bus *bus;
+	struct mii_bus *phy_bus;
+	unsigned int switch_addr;
+	u16 current_page;
+};
+
+struct an8855_phy_priv {
+	u8 addr;
+	struct an8855_core_priv *core;
+};
+
+struct an8855_phy_bus {
+	struct mii_bus *bus;
+	struct fwnode_handle *node;
+	u8 addr;
+};
+
+static const struct mfd_cell an8855_cells[] = {
+	MFD_CELL_OF("an8855-efuse", NULL, NULL, 0, 0,
+		    "airoha,an8855-efuse"),
+	MFD_CELL_OF("an8855-switch", NULL, NULL, 0, 0,
+		    "airoha,an8855-switch"),
+};
+
+static int an8855_mii_set_page(struct an8855_core_priv *priv, u8 addr,
+			       u8 page) __must_hold(&priv->bus->mdio_lock)
+{
+	struct mii_bus *bus = priv->bus;
+	int ret;
+
+	ret = __mdiobus_write(bus, addr, AN8855_PHY_SELECT_PAGE, page);
+	if (ret) {
+		dev_err_ratelimited(&bus->dev, "failed to set mii page\n");
+		return ret;
+	}
+
+	/* Cache current page if next MII read/write is for Switch page */
+	priv->current_page = page;
+	return 0;
+}
+
+static int an8855_mii_read32(struct mii_bus *bus, u8 phy_id, u32 reg,
+			     u32 *val) __must_hold(&bus->mdio_lock)
+{
+	int lo, hi, ret;
+
+	ret = __mdiobus_write(bus, phy_id, AN8855_PBUS_MODE,
+			      AN8855_PBUS_MODE_ADDR_FIXED);
+	if (ret)
+		goto err;
+
+	ret = __mdiobus_write(bus, phy_id, AN8855_PBUS_RD_ADDR_HIGH,
+			      upper_16_bits(reg));
+	if (ret)
+		goto err;
+
+	ret = __mdiobus_write(bus, phy_id, AN8855_PBUS_RD_ADDR_LOW,
+			      lower_16_bits(reg));
+	if (ret)
+		goto err;
+
+	hi = __mdiobus_read(bus, phy_id, AN8855_PBUS_RD_DATA_HIGH);
+	if (hi < 0) {
+		ret = hi;
+		goto err;
+	}
+
+	lo = __mdiobus_read(bus, phy_id, AN8855_PBUS_RD_DATA_LOW);
+	if (lo < 0) {
+		ret = lo;
+		goto err;
+	}
+
+	*val = ((u32)hi << 16) | lo;
+
+	return 0;
+err:
+	dev_err_ratelimited(&bus->dev, "failed to read register\n");
+	return ret;
+}
+
+/*
+ * Protect concurrent access to phy page if switch address also
+ * expose a PHY.
+ */
+static void an8855_regmap_lock(struct an8855_core_priv *priv)
+{
+	if (priv->phy_bus)
+		mutex_lock(&priv->phy_bus->mdio_lock);
+	mutex_lock_nested(&priv->bus->mdio_lock, MDIO_MUTEX_NESTED);
+}
+
+static void an8855_regmap_unlock(struct an8855_core_priv *priv)
+{
+	mutex_unlock(&priv->bus->mdio_lock);
+	if (priv->phy_bus)
+		mutex_unlock(&priv->phy_bus->mdio_lock);
+}
+
+static int an8855_regmap_read(void *ctx, uint32_t reg, uint32_t *val)
+{
+	struct an8855_core_priv *priv = ctx;
+	struct mii_bus *bus = priv->bus;
+	u16 addr = priv->switch_addr;
+	int ret;
+
+	an8855_regmap_lock(priv);
+	ret = an8855_mii_set_page(priv, addr, AN8855_PHY_PAGE_EXTENDED_4);
+	if (ret < 0)
+		goto exit;
+
+	ret = an8855_mii_read32(bus, addr, reg, val);
+
+exit:
+	an8855_regmap_unlock(priv);
+
+	return ret < 0 ? ret : 0;
+}
+
+static int an8855_mii_write32(struct mii_bus *bus, u8 phy_id, u32 reg,
+			      u32 val) __must_hold(&bus->mdio_lock)
+{
+	int ret;
+
+	ret = __mdiobus_write(bus, phy_id, AN8855_PBUS_MODE,
+			      AN8855_PBUS_MODE_ADDR_FIXED);
+	if (ret)
+		goto err;
+
+	ret = __mdiobus_write(bus, phy_id, AN8855_PBUS_WR_ADDR_HIGH,
+			      upper_16_bits(reg));
+	if (ret)
+		goto err;
+	ret = __mdiobus_write(bus, phy_id, AN8855_PBUS_WR_ADDR_LOW,
+			      lower_16_bits(reg));
+	if (ret)
+		goto err;
+
+	ret = __mdiobus_write(bus, phy_id, AN8855_PBUS_WR_DATA_HIGH,
+			      upper_16_bits(val));
+	if (ret)
+		goto err;
+
+	ret = __mdiobus_write(bus, phy_id, AN8855_PBUS_WR_DATA_LOW,
+			      lower_16_bits(val));
+	if (ret)
+		goto err;
+
+	return 0;
+err:
+	dev_err_ratelimited(&bus->dev,
+			    "failed to write an8855 register\n");
+	return ret;
+}
+
+static int an8855_regmap_write(void *ctx, uint32_t reg, uint32_t val)
+{
+	struct an8855_core_priv *priv = ctx;
+	struct mii_bus *bus = priv->bus;
+	u16 addr = priv->switch_addr;
+	int ret;
+
+	an8855_regmap_lock(priv);
+	ret = an8855_mii_set_page(priv, addr, AN8855_PHY_PAGE_EXTENDED_4);
+	if (ret)
+		goto exit;
+
+	ret = an8855_mii_write32(bus, addr, reg, val);
+
+exit:
+	an8855_regmap_unlock(priv);
+
+	return ret < 0 ? ret : 0;
+}
+
+static int an8855_regmap_update_bits(void *ctx, uint32_t reg, uint32_t mask,
+				     uint32_t write_val)
+{
+	struct an8855_core_priv *priv = ctx;
+	struct mii_bus *bus = priv->bus;
+	u16 addr = priv->switch_addr;
+	u32 val;
+	int ret;
+
+	an8855_regmap_lock(priv);
+	ret = an8855_mii_set_page(priv, addr, AN8855_PHY_PAGE_EXTENDED_4);
+	if (ret)
+		goto exit;
+
+	ret = an8855_mii_read32(bus, addr, reg, &val);
+	if (ret < 0)
+		goto exit;
+
+	val &= ~mask;
+	val |= write_val & mask;
+	ret = an8855_mii_write32(bus, addr, reg, val);
+
+exit:
+	an8855_regmap_unlock(priv);
+
+	return ret < 0 ? ret : 0;
+}
+
+static const struct regmap_range an8855_readable_ranges[] = {
+	regmap_reg_range(0x10000000, 0x10000fff), /* SCU */
+	regmap_reg_range(0x10001000, 0x10001fff), /* RBUS */
+	regmap_reg_range(0x10002000, 0x10002fff), /* MCU */
+	regmap_reg_range(0x10005000, 0x10005fff), /* SYS SCU */
+	regmap_reg_range(0x10007000, 0x10007fff), /* I2C Slave */
+	regmap_reg_range(0x10008000, 0x10008fff), /* I2C Master */
+	regmap_reg_range(0x10009000, 0x10009fff), /* PDMA */
+	regmap_reg_range(0x1000a100, 0x1000a2ff), /* General Purpose Timer */
+	regmap_reg_range(0x1000a200, 0x1000a2ff), /* GPU timer */
+	regmap_reg_range(0x1000a300, 0x1000a3ff), /* GPIO */
+	regmap_reg_range(0x1000a400, 0x1000a5ff), /* EFUSE */
+	regmap_reg_range(0x1000c000, 0x1000cfff), /* GDMP CSR */
+	regmap_reg_range(0x10010000, 0x1001ffff), /* GDMP SRAM */
+	regmap_reg_range(0x10200000, 0x10203fff), /* Switch - ARL Global */
+	regmap_reg_range(0x10204000, 0x10207fff), /* Switch - BMU */
+	regmap_reg_range(0x10208000, 0x1020bfff), /* Switch - ARL Port */
+	regmap_reg_range(0x1020c000, 0x1020cfff), /* Switch - SCH */
+	regmap_reg_range(0x10210000, 0x10213fff), /* Switch - MAC */
+	regmap_reg_range(0x10214000, 0x10217fff), /* Switch - MIB */
+	regmap_reg_range(0x10218000, 0x1021bfff), /* Switch - Port Control */
+	regmap_reg_range(0x1021c000, 0x1021ffff), /* Switch - TOP */
+	regmap_reg_range(0x10220000, 0x1022ffff), /* SerDes */
+	regmap_reg_range(0x10286000, 0x10286fff), /* RG Batcher */
+	regmap_reg_range(0x1028c000, 0x1028ffff), /* ETHER_SYS */
+	regmap_reg_range(0x30000000, 0x37ffffff), /* I2C EEPROM */
+	regmap_reg_range(0x38000000, 0x3fffffff), /* BOOT_ROM */
+	regmap_reg_range(0xa0000000, 0xbfffffff), /* GPHY */
+};
+
+static const struct regmap_access_table an8855_readable_table = {
+	.yes_ranges = an8855_readable_ranges,
+	.n_yes_ranges = ARRAY_SIZE(an8855_readable_ranges),
+};
+
+static const struct regmap_config an8855_regmap_config = {
+	.name = "switch",
+	.reg_bits = 32,
+	.val_bits = 32,
+	.reg_stride = 4,
+	.max_register = 0xbfffffff,
+	.reg_read = an8855_regmap_read,
+	.reg_write = an8855_regmap_write,
+	.reg_update_bits = an8855_regmap_update_bits,
+	.disable_locking = true,
+	.rd_table = &an8855_readable_table,
+};
+
+static int an8855_regmap_phy_reset_page(struct an8855_core_priv *priv,
+					int phy) __must_hold(&priv->bus->mdio_lock)
+{
+	/* Check PHY page only for addr shared with switch */
+	if (phy != priv->switch_addr)
+		return 0;
+
+	/* Don't restore page if it's not set to Switch page */
+	if (priv->current_page != AN8855_PHY_PAGE_EXTENDED_4)
+		return 0;
+
+	/*
+	 * Restore page to 0, PHY might change page right after but that
+	 * will be ignored as it won't be a switch page.
+	 */
+	return an8855_mii_set_page(priv, phy, AN8855_PHY_PAGE_STANDARD);
+}
+
+static int an8855_regmap_phy_read(void *ctx, uint32_t reg, uint32_t *val)
+{
+	struct an8855_phy_priv *priv = ctx;
+	struct an8855_core_priv *core_priv;
+	u32 addr = priv->addr;
+	struct mii_bus *bus;
+	int ret;
+
+	core_priv = priv->core;
+	bus = core_priv->bus;
+
+	mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
+	ret = an8855_regmap_phy_reset_page(core_priv, addr);
+	if (ret)
+		goto exit;
+
+	ret = __mdiobus_read(bus, addr, reg);
+	if (ret >= 0)
+		*val = ret;
+
+exit:
+	mutex_unlock(&bus->mdio_lock);
+
+	return ret < 0 ? ret : 0;
+}
+
+static int an8855_regmap_phy_write(void *ctx, uint32_t reg, uint32_t val)
+{
+	struct an8855_phy_priv *priv = ctx;
+	struct an8855_core_priv *core_priv;
+	u32 addr = priv->addr;
+	struct mii_bus *bus;
+	int ret;
+
+	core_priv = priv->core;
+	bus = core_priv->bus;
+
+	mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
+	ret = an8855_regmap_phy_reset_page(core_priv, addr);
+	if (ret)
+		goto exit;
+
+	ret = __mdiobus_write(bus, addr, reg, val);
+
+exit:
+	mutex_unlock(&bus->mdio_lock);
+
+	return ret;
+}
+
+static const struct regmap_config an8855_phy_regmap_config = {
+	.reg_bits = 16,
+	.val_bits = 16,
+	.reg_read = an8855_regmap_phy_read,
+	.reg_write = an8855_regmap_phy_write,
+	.disable_locking = true,
+	.max_register = 0x1f,
+};
+
+static int an8855_read_switch_id(struct device *dev, struct regmap *regmap)
+{
+	u32 id;
+	int ret;
+
+	ret = regmap_read(regmap, AN8855_CREV, &id);
+	if (ret)
+		return ret;
+
+	if (id != AN8855_ID) {
+		dev_err(dev, "Detected Switch ID %x but %x was expected\n",
+			id, AN8855_ID);
+		return -ENODEV;
+	}
+
+	return 0;
+}
+
+static int an8855_phy_bus_register(struct device *dev, struct an8855_core_priv *priv,
+				   struct device_node *phy_np,
+				   struct an8855_phy_bus *phy_bus_info)
+{
+	struct mdio_regmap_config mrc = { };
+	struct an8855_phy_priv *phy_priv;
+	struct regmap *regmap;
+	u32 addr, phy_offset;
+	struct mii_bus *bus;
+	int ret;
+
+	ret = of_property_read_u32(phy_np, "reg", &addr);
+	if (ret)
+		return ret;
+
+	phy_offset = addr - priv->switch_addr;
+	if (phy_offset >= AN8855_MAX_PHY_PORT)
+		return -EINVAL;
+
+	phy_priv = devm_kzalloc(dev, sizeof(*phy_priv), GFP_KERNEL);
+	if (!phy_priv)
+		return -ENOMEM;
+
+	phy_priv->addr = addr;
+	phy_priv->core = priv;
+
+	regmap = devm_regmap_init(dev, NULL, phy_priv, &an8855_phy_regmap_config);
+	if (IS_ERR(regmap))
+		return dev_err_probe(dev, PTR_ERR(regmap),
+				     "phy%d regmap initialization failed\n",
+				      addr);
+
+	mrc.regmap = regmap;
+	mrc.parent = dev;
+	mrc.valid_addr = addr;
+	snprintf(mrc.name, MII_BUS_ID_SIZE, "an8855:%u-phy%u", priv->switch_addr,
+		 phy_offset);
+
+	bus = devm_mdio_regmap_register(dev, &mrc);
+	if (IS_ERR(bus))
+		return PTR_ERR(bus);
+
+	if (addr == priv->switch_addr)
+		priv->phy_bus = bus;
+
+	phy_bus_info->bus = bus;
+	phy_bus_info->addr = addr;
+	phy_bus_info->node = fwnode_handle_get(of_fwnode_handle(phy_np));
+
+	return 0;
+}
+
+static int an8855_mdio_register(struct device *dev, struct an8855_core_priv *priv,
+				struct an8855_phy_bus *phy_bus_infos)
+{
+	struct device_node *mdio_np;
+	int ret = 0;
+	int i = 0;
+
+	mdio_np = of_get_child_by_name(dev->of_node, "mdio");
+	if (!mdio_np)
+		return -ENODEV;
+
+	for_each_available_child_of_node_scoped(mdio_np, phy_np) {
+		if (i >= AN8855_MAX_PHY_PORT) {
+			ret = -EINVAL;
+			goto exit;
+		}
+
+		ret = an8855_phy_bus_register(dev, priv, phy_np,
+					      &phy_bus_infos[i]);
+		if (ret)
+			goto exit;
+
+		i++;
+	}
+
+	of_node_put(mdio_np);
+exit:
+	if (ret) {
+		while (i--)
+			fwnode_handle_put(phy_bus_infos[i].node);
+
+		return ret;
+	}
+
+	return i;
+}
+
+static int an8855_core_probe(struct mdio_device *mdiodev)
+{
+	struct an8855_phy_bus phy_bus_infos[AN8855_MAX_PHY_PORT] = { };
+	struct device *dev = &mdiodev->dev;
+	struct an8855_core_priv *priv;
+	struct regmap *regmap;
+	int num_phys;
+	int i, ret;
+
+	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+	if (!priv)
+		return -ENOMEM;
+
+	priv->bus = mdiodev->bus;
+	priv->switch_addr = mdiodev->addr;
+	/* No DMA for mdiobus, mute warning for DMA mask not set */
+	dev->dma_mask = &dev->coherent_dma_mask;
+
+	/* Register virtual MDIO for each PHY */
+	num_phys = an8855_mdio_register(dev, priv, phy_bus_infos);
+	if (num_phys < 0)
+		return num_phys;
+
+	regmap = devm_regmap_init(dev, NULL, priv, &an8855_regmap_config);
+	if (IS_ERR(regmap)) {
+		ret = PTR_ERR(regmap);
+		dev_err_probe(dev, ret, "regmap initialization failed\n");
+		goto err_put_fwnodes;
+	}
+
+	/* Reset PHY page for switch address */
+	mutex_lock_nested(&priv->bus->mdio_lock, MDIO_MUTEX_NESTED);
+	ret = an8855_mii_set_page(priv, priv->switch_addr,
+				  AN8855_PHY_PAGE_STANDARD);
+	mutex_unlock(&priv->bus->mdio_lock);
+	if (ret)
+		goto err_put_fwnodes;
+
+	ret = an8855_read_switch_id(dev, regmap);
+	if (ret)
+		goto err_put_fwnodes;
+
+	/* Release global PHY power down */
+	ret = regmap_write(regmap, AN8855_RG_GPHY_AFE_PWD, 0x0);
+	if (ret)
+		goto err_put_fwnodes;
+
+	/* Register PHYs */
+	for (i = 0; i < num_phys; i++) {
+		ret = fwnode_mdiobus_register_phy(phy_bus_infos[i].bus,
+						  phy_bus_infos[i].node,
+						  phy_bus_infos[i].addr);
+		fwnode_handle_put(phy_bus_infos[i].node);
+		phy_bus_infos[i].node = NULL;
+
+		if (ret)
+			goto err_put_fwnodes;
+	}
+
+	return devm_mfd_add_devices(dev, PLATFORM_DEVID_AUTO, an8855_cells,
+				    ARRAY_SIZE(an8855_cells), NULL, 0,
+				    NULL);
+
+err_put_fwnodes:
+	for (i = 0; i < num_phys; i++)
+		if (phy_bus_infos[i].node)
+			fwnode_handle_put(phy_bus_infos[i].node);
+
+	return ret;
+}
+
+static const struct of_device_id an8855_core_of_match[] = {
+	{ .compatible = "airoha,an8855" },
+	{ /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, an8855_core_of_match);
+
+static struct mdio_driver an8855_core_driver = {
+	.probe = an8855_core_probe,
+	.mdiodrv.driver = {
+		.name = "an8855",
+		.of_match_table = an8855_core_of_match,
+	},
+};
+mdio_module_driver(an8855_core_driver);
+
+MODULE_AUTHOR("Christian Marangi <ansuelsmth@gmail.com>");
+MODULE_DESCRIPTION("Driver for Airoha AN8855");
+MODULE_LICENSE("GPL");
-- 
2.55.0

Re: [PATCH net-next v23 4/9] mfd: an8855: Add support for Airoha AN8855 Switch

[netdev-bot+sashiko]

Thank you for your contribution! Sashiko AI review found 8 potential
issue(s) to consider.

Critical: 0 · High: 0 · Medium: 5 · Low: 3

If you believe none of the issues are legitimate, please reply to each
issue of Medium severity or higher and explain why the AI is wrong.
If any of them are legitimate and you plan to respin, please let patchwork
know by including "pw-bot: cr" as a separate line at the end of your reply
(one such reply per series is enough).

- [Medium] The patch adds MFD_AIROHA_AN8855, and both the commit message
  and the Kconfig help say this MFD provides an NVMEM provider.
- [Medium] an8855_phy_bus_register() names each virtual MDIO bus with
  snprintf(mrc.name, MII_BUS_ID_SIZE, "an8855:%u-phy%u",…
- [Medium] an8855_phy_bus_register() reads the PHY address from DT "reg"
  and only checks `phy_offset = addr - priv->switch_addr; if (phy_offset…
- [Medium] In an8855_mdio_register(), of_node_put(mdio_np) comes before
  the 'exit:' label.
- [Medium] The MFD binding puts `reset-gpios` on the core `airoha,an8855`
  node, and its example wires `reset-gpios = <&pio 39 GPIO_ACTIVE_HIGH>`.
- [Low] The MFD binding (airoha,an8855.yaml) leaves the 'efuse' child
  optional: required is compatible, reg, mdio, ethernet-switch.
- [Low] Both examples in the AN8855 PHY binding (airoha,an8855-phy.yaml)
  use "ethernet-phy-idc0ff.0410", "ethernet-phy-ieee802.3-c45".
- [Low] an8855_core_probe() clears AN8855_RG_GPHY_AFE_PWD ("Release
  global PHY power down") before registering the PHYs and the MFD…

--

mfd: an8855: Add support for Airoha AN8855 Switch

This adds an MFD core driver for the Airoha AN8855 switch, which is
accessed over MDIO. It adds a paged regmap for the switch registers and
one mdio-regmap bus for each internal PHY. It also registers eFuse and
DSA switch child cells.

> diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
> index e4fd4572472f9..afbdcec0fce8f 100644
> --- a/drivers/mfd/Kconfig
> +++ b/drivers/mfd/Kconfig
> @@ -54,6 +54,20 @@ config MFD_ALTERA_SYSMGR
>  	  using regmap_mmio accesses for ARM32 parts and SMC calls to
>  	  EL3 for ARM64 parts.
>  
> +config MFD_AIROHA_AN8855
> +	tristate "Airoha AN8855 Switch Core"
> +	select MFD_CORE
> +	select REGMAP
> +	select PHYLIB
> +	select MDIO_REGMAP
> +	depends on NETDEVICES && OF
> +	help
> +	  Support for the Airoha AN8855 Switch Core. This is an SoC
> +	  that provides various peripherals, to count, i2c, an Ethrnet
> +	  Switch, a CPU timer, GPIO, eFUSE.
> +
> +	  Currently it provides a DSA switch and a NVMEM provider.

[Severity: Medium]
The help text and the commit message both say this provides an NVMEM
provider. However, NVMEM_AN8855_EFUSE in drivers/nvmem/Kconfig still
only has:

	depends on COMPILE_TEST

It was reduced to that by commit 4796eaafd6a1 ("nvmem: an8855: drop an
unused Kconfig symbol"), because MFD_AIROHA_AN8855 was referenced but
never defined.

Now that this patch defines the symbol, should the nvmem entry go back
to "depends on MFD_AIROHA_AN8855 || COMPILE_TEST"? NET_DSA_AN8855, added
later in the series, already uses that form.

As it stands, the eFuse driver can't be enabled when COMPILE_TEST is not
set. That leaves the an8855-efuse cell with no driver to bind. The PHY
nodes' nvmem-cells (tx_a..tx_d) then point at a provider that never
registers, so an8855_probe()->an8855_get_r50ohm_val() in the AN8855 PHY
driver can't get its calibration cells.

[ ... ]

> diff --git a/drivers/mfd/airoha-an8855.c b/drivers/mfd/airoha-an8855.c
> new file mode 100644
> index 0000000000000..a2a36704a9fca
> --- /dev/null
> +++ b/drivers/mfd/airoha-an8855.c
> @@ -0,0 +1,580 @@

[ ... ]

> +static const struct mfd_cell an8855_cells[] = {
> +	MFD_CELL_OF("an8855-efuse", NULL, NULL, 0, 0,
> +		    "airoha,an8855-efuse"),

[Severity: Low]
The MFD binding (airoha,an8855.yaml) makes the efuse child optional. Its
required list is compatible, reg, mdio and ethernet-switch. This cell is
still registered every time.

When the DT has no efuse node, won't mfd_add_device() print a "Failed to
locate of_node" warning and register the platform device anyway? The
efuse driver would then bind by platform name and register an NVMEM
device that the DT never described.

> +	MFD_CELL_OF("an8855-switch", NULL, NULL, 0, 0,
> +		    "airoha,an8855-switch"),
> +};

[ ... ]

> +static int an8855_phy_bus_register(struct device *dev, struct an8855_core_priv *priv,
> +				   struct device_node *phy_np,
> +				   struct an8855_phy_bus *phy_bus_info)
> +{

[ ... ]

> +	ret = of_property_read_u32(phy_np, "reg", &addr);
> +	if (ret)
> +		return ret;
> +
> +	phy_offset = addr - priv->switch_addr;
> +	if (phy_offset >= AN8855_MAX_PHY_PORT)
> +		return -EINVAL;

[Severity: Medium]
Is addr ever checked against PHY_MAX_ADDR? The only check here is
relative to switch_addr. If the switch sits at MDIO address 28..31, a
child reg of 32..35 passes.

That addr goes straight to fwnode_mdiobus_register_phy() in
an8855_core_probe(), which skips the of_mdio_parse_addr() check done on
the normal OF MDIO path. For a C22 compatible such as
ethernet-phy-idc0ff.0410, the call chain is:

an8855_core_probe()
  fwnode_mdiobus_register_phy(bus, node, addr)
    phy_device_create(bus, addr, ...)
      dev->irq = bus->irq[addr];
    fwnode_mdiobus_phy_device_register()
      mdio->irq[addr] = rc;
      mdio->phy_ignore_ta_mask |= 1 << addr;
      phy_device_register()
        mdiobus_register_device()
          mdiodev->bus->mdio_map[mdiodev->addr] = mdiodev;

Could this read and write past the end of bus->irq[] and
bus->mdio_map[]? Those writes could overwrite later fields of struct
mii_bus, such as reset_delay_us, reset_post_delay_us or reset_gpiod.

Such a DT would violate mdio.yaml (reg maximum 31), but nothing enforces
that at runtime.

[ ... ]

> +	mrc.regmap = regmap;
> +	mrc.parent = dev;
> +	mrc.valid_addr = addr;
> +	snprintf(mrc.name, MII_BUS_ID_SIZE, "an8855:%u-phy%u", priv->switch_addr,
> +		 phy_offset);
> +
> +	bus = devm_mdio_regmap_register(dev, &mrc);
> +	if (IS_ERR(bus))
> +		return PTR_ERR(bus);

[Severity: Medium]
Can two AN8855 chips on different host MDIO buses end up with the same
mii_bus name? The name is built only from switch_addr and phy_offset.
Two switches at the same address on two MACs would therefore both
produce the same "an8855:<addr>-phy<n>" names.

devm_mdio_regmap_register() copies this into mii->id, and
__mdiobus_register() then does:

	dev_set_name(&bus->dev, "%s", bus->id);

The bus is in mdio_bus_class, so the second device_add() looks like it
would fail with -EEXIST. The whole second an8855_core_probe() would fail
with it. PHY device names built with PHY_ID_FMT would collide in the
same way.

Could the name include something unique to the parent, such as
dev_name(dev)?

[ ... ]

> +static int an8855_mdio_register(struct device *dev, struct an8855_core_priv *priv,
> +				struct an8855_phy_bus *phy_bus_infos)
> +{
> +	struct device_node *mdio_np;
> +	int ret = 0;
> +	int i = 0;
> +
> +	mdio_np = of_get_child_by_name(dev->of_node, "mdio");
> +	if (!mdio_np)
> +		return -ENODEV;
> +
> +	for_each_available_child_of_node_scoped(mdio_np, phy_np) {
> +		if (i >= AN8855_MAX_PHY_PORT) {
> +			ret = -EINVAL;
> +			goto exit;
> +		}
> +
> +		ret = an8855_phy_bus_register(dev, priv, phy_np,
> +					      &phy_bus_infos[i]);
> +		if (ret)
> +			goto exit;
> +
> +		i++;
> +	}
> +
> +	of_node_put(mdio_np);
> +exit:

[Severity: Medium]
Does this leak the reference on mdio_np taken by
of_get_child_by_name()? of_node_put(mdio_np) sits above the exit label.
Both gotos inside the loop skip it: the one for too many children and
the one for an8855_phy_bus_register() failing.

This function also mixes goto-based cleanup with the __free(device_node)
scoped iterator from for_each_available_child_of_node_scoped().
include/linux/cleanup.h asks that goto and cleanup helpers not be mixed
in the same function.

Would declaring mdio_np with __free(device_node) and dropping the gotos
fix both?

[ ... ]

> +static int an8855_core_probe(struct mdio_device *mdiodev)
> +{

[ ... ]

> +	/* Reset PHY page for switch address */
> +	mutex_lock_nested(&priv->bus->mdio_lock, MDIO_MUTEX_NESTED);
> +	ret = an8855_mii_set_page(priv, priv->switch_addr,
> +				  AN8855_PHY_PAGE_STANDARD);

[Severity: Medium]
The MFD binding documents reset-gpios on the airoha,an8855 node, and its
example uses reset-gpios = <&pio 39 GPIO_ACTIVE_HIGH>. Does anything
request or deassert that GPIO before this first MDIO access?

an8855_core_probe() doesn't touch it. mdiobus_register_device() only
sets up reset for MDIO_DEVICE_FLAG_PHY devices, so mdio_device_reset()
in mdio_probe() does nothing for this mdio_device. The DSA driver at the
end of the series doesn't handle the reset line either.

There is also no wait for the chip to finish its internal init before
the page select, the CREV read and the AFE_PWD write.
linux/gpio/consumer.h is included but unused, and so is this define:

#define AN8855_HWTRAP			0x1000009c

Was a reset and HWTRAP poll sequence lost when this code moved into the
MFD? On boards where reset is still asserted at boot, it looks like
an8855_read_switch_id() would fail and the switch would be unusable.

> +	mutex_unlock(&priv->bus->mdio_lock);
> +	if (ret)
> +		goto err_put_fwnodes;
> +
> +	ret = an8855_read_switch_id(dev, regmap);
> +	if (ret)
> +		goto err_put_fwnodes;
> +
> +	/* Release global PHY power down */
> +	ret = regmap_write(regmap, AN8855_RG_GPHY_AFE_PWD, 0x0);
> +	if (ret)
> +		goto err_put_fwnodes;

[Severity: Low]
Nothing appears to set the AN8855_RG_GPHY_AFE_PWD bits again later.
fwnode_mdiobus_register_phy() or devm_mfd_add_devices() can still fail
after this write. The err_put_fwnodes path only drops fwnode references,
and there is no .remove callback or devm action for unbind.

Should power down be restored on those paths, so the PHY analog front
ends aren't left powered with no driver managing the ports?

> +
> +	/* Register PHYs */
> +	for (i = 0; i < num_phys; i++) {
> +		ret = fwnode_mdiobus_register_phy(phy_bus_infos[i].bus,
> +						  phy_bus_infos[i].node,
> +						  phy_bus_infos[i].addr);

[Severity: Low]
Both examples in Documentation/devicetree/bindings/net/airoha,an8855-phy.yaml
use:

compatible = "ethernet-phy-idc0ff.0410",
             "ethernet-phy-ieee802.3-c45";

The buses created by devm_mdio_regmap_register() only provide C22
read/write callbacks. With that compatible, fwnode_mdiobus_register_phy()
does:

	is_c45 = fwnode_device_is_compatible(child, "ethernet-phy-ieee802.3-c45");
	if (is_c45 || fwnode_get_phy_id(child, &phy_id))
		phy = get_phy_device(bus, addr, is_c45);

The explicit PHY ID is then ignored. get_phy_c45_ids() fails because
__mdiobus_c45_read() returns -EOPNOTSUPP when bus->read_c45 is not set.

Would a DT copied from that example make the whole an8855_core_probe()
fail? The MFD binding example uses the c22 compatible, so the two
bindings seem to disagree.

-- 
Sashiko AI review · https://netdev-ai.bots.linux.dev/sashiko/#/patchset/20260925182435.21207-1-ansuelsmth%40gmail.com

[PATCH net-next v23 5/9] net: phy: Add Airoha AN8855 Internal Switch Gigabit PHY

[Christian Marangi]

Add support for Airoha AN8855 Internal Switch Gigabit PHY.

This is a simple PHY driver to configure and calibrate the PHY for the
AN8855 Switch with the use of NVMEM cells.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
---
 drivers/net/phy/Kconfig      |   6 +
 drivers/net/phy/Makefile     |   1 +
 drivers/net/phy/air_an8855.c | 275 +++++++++++++++++++++++++++++++++++
 3 files changed, 282 insertions(+)
 create mode 100644 drivers/net/phy/air_an8855.c

diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig
index d3835597e379..eca2ce135c86 100644
--- a/drivers/net/phy/Kconfig
+++ b/drivers/net/phy/Kconfig
@@ -96,6 +96,12 @@ config AIR_AN8801_PHY
 	help
 	  Currently supports the Airoha AN8801R PHY.
 
+config AIR_AN8855_PHY
+	tristate "Airoha AN8855 Internal Gigabit PHY"
+	depends on NVMEM || !NVMEM
+	help
+	  Currently supports the internal Airoha AN8855 Switch PHY.
+
 config AIR_EN8811H_PHY
 	tristate "Airoha EN8811H 2.5 Gigabit PHY"
 	select AIR_NET_PHYLIB
diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile
index 579066a638f0..d5c633db0742 100644
--- a/drivers/net/phy/Makefile
+++ b/drivers/net/phy/Makefile
@@ -31,6 +31,7 @@ obj-$(CONFIG_ADIN_PHY)		+= adin.o
 obj-$(CONFIG_ADIN1100_PHY)	+= adin1100.o
 obj-$(CONFIG_ADIN1140_PHY)	+= adin1140-phy.o
 obj-$(CONFIG_AIR_AN8801_PHY)	+= air_an8801.o
+obj-$(CONFIG_AIR_AN8855_PHY)	+= air_an8855.o
 obj-$(CONFIG_AIR_EN8811H_PHY)   += air_en8811h.o
 obj-$(CONFIG_AIR_NET_PHYLIB)	+= air_phy_lib.o
 obj-$(CONFIG_AMD_PHY)		+= amd.o
diff --git a/drivers/net/phy/air_an8855.c b/drivers/net/phy/air_an8855.c
new file mode 100644
index 000000000000..bc22256fd5f9
--- /dev/null
+++ b/drivers/net/phy/air_an8855.c
@@ -0,0 +1,275 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2024 Christian Marangi <ansuelsmth@gmail.com>
+ */
+
+#include <linux/bitfield.h>
+#include <linux/module.h>
+#include <linux/nvmem-consumer.h>
+#include <linux/of.h>
+#include <linux/phy.h>
+
+#define AN8855_PHY_SELECT_PAGE			0x1f
+#define   AN8855_PHY_PAGE			GENMASK(2, 0)
+#define   AN8855_PHY_PAGE_STANDARD		FIELD_PREP_CONST(AN8855_PHY_PAGE, 0x0)
+#define   AN8855_PHY_PAGE_EXTENDED_1		FIELD_PREP_CONST(AN8855_PHY_PAGE, 0x1)
+
+/* MII Registers Page 1 */
+#define AN8855_PHY_EXT_REG_14			0x14
+#define   AN8855_PHY_EN_DOWN_SHIFT		BIT(4)
+
+/* R50 Calibration regs in MDIO_MMD_VEND1 */
+#define AN8855_PHY_R50OHM_RSEL_TX_AB		0x174
+#define AN8855_PHY_R50OHM_RSEL_TX_A_EN		BIT(15)
+#define AN8855_PHY_R50OHM_RSEL_TX_A		GENMASK(14, 8)
+#define AN8855_PHY_R50OHM_RSEL_TX_B_EN		BIT(7)
+#define AN8855_PHY_R50OHM_RSEL_TX_B		GENMASK(6, 0)
+#define AN8855_PHY_R50OHM_RSEL_TX_CD		0x175
+#define AN8855_PHY_R50OHM_RSEL_TX_C_EN		BIT(15)
+#define AN8855_PHY_R50OHM_RSEL_TX_C		GENMASK(14, 8)
+#define AN8855_PHY_R50OHM_RSEL_TX_D_EN		BIT(7)
+#define AN8855_PHY_R50OHM_RSEL_TX_D		GENMASK(6, 0)
+
+#define AN8855_SWITCH_EFUSE_R50O		GENMASK(30, 24)
+
+/* PHY TX PAIR DELAY SELECT Register */
+#define AN8855_PHY_TX_PAIR_DLY_SEL_GBE		0x013
+#define   AN8855_PHY_CR_DA_TX_PAIR_DELAY_SEL_A_GBE GENMASK(14, 12)
+#define   AN8855_PHY_CR_DA_TX_PAIR_DELAY_SEL_B_GBE GENMASK(10, 8)
+#define   AN8855_PHY_CR_DA_TX_PAIR_DELAY_SEL_C_GBE GENMASK(6, 4)
+#define   AN8855_PHY_CR_DA_TX_PAIR_DELAY_SEL_D_GBE GENMASK(2, 0)
+/* PHY ADC Register */
+#define AN8855_PHY_RXADC_CTRL			0x0d8
+#define   AN8855_PHY_RG_AD_SAMPLE_PHSEL_A	BIT(12)
+#define   AN8855_PHY_RG_AD_SAMPLE_PHSEL_B	BIT(8)
+#define   AN8855_PHY_RG_AD_SAMPLE_PHSEL_C	BIT(4)
+#define   AN8855_PHY_RG_AD_SAMPLE_PHSEL_D	BIT(0)
+#define AN8855_PHY_RXADC_REV_0			0x0d9
+#define   AN8855_PHY_RG_AD_RESERVE0_A		GENMASK(15, 8)
+#define   AN8855_PHY_RG_AD_RESERVE0_B		GENMASK(7, 0)
+#define AN8855_PHY_RXADC_REV_1			0x0da
+#define   AN8855_PHY_RG_AD_RESERVE0_C		GENMASK(15, 8)
+#define   AN8855_PHY_RG_AD_RESERVE0_D		GENMASK(7, 0)
+
+#define AN8855_PHY_ID				0xc0ff0410
+
+struct air_an8855_priv {
+	bool needs_calibration;
+	u8 calibration_data[4];
+};
+
+static const u8 dsa_r50ohm_table[] = {
+	127, 127, 127, 127, 127, 127, 127, 127, 127, 127,
+	127, 127, 127, 127, 127, 127, 127, 126, 122, 117,
+	112, 109, 104, 101,  97,  94,  90,  88,  84,  80,
+	78,  74,  72,  68,  66,  64,  61,  58,  56,  53,
+	51,  48,  47,  44,  42,  40,  38,  36,  34,  32,
+	31,  28,  27,  24,  24,  22,  20,  18,  16,  16,
+	14,  12,  11,   9
+};
+
+static int an8855_get_r50ohm_val(struct device *dev, const char *calib_name,
+				 u8 *dest)
+{
+	u32 shift_sel, val;
+	int ret;
+	int i;
+
+	ret = nvmem_cell_read_u32(dev, calib_name, &val);
+	if (ret)
+		return ret;
+
+	shift_sel = FIELD_GET(AN8855_SWITCH_EFUSE_R50O, val);
+	for (i = 0; i < ARRAY_SIZE(dsa_r50ohm_table); i++)
+		if (dsa_r50ohm_table[i] == shift_sel)
+			break;
+
+	if (i < 8 || i >= ARRAY_SIZE(dsa_r50ohm_table))
+		*dest = dsa_r50ohm_table[25];
+	else
+		*dest = dsa_r50ohm_table[i - 8];
+
+	return 0;
+}
+
+static int an8855_probe(struct phy_device *phydev)
+{
+	struct device *dev = &phydev->mdio.dev;
+	struct air_an8855_priv *priv;
+
+	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+	if (!priv)
+		return -ENOMEM;
+
+	priv->needs_calibration = of_property_present(dev->of_node,
+						      "nvmem-cells");
+
+	if (priv->needs_calibration) {
+		int ret;
+
+		ret = an8855_get_r50ohm_val(dev, "tx_a", &priv->calibration_data[0]);
+		if (ret)
+			return ret;
+
+		ret = an8855_get_r50ohm_val(dev, "tx_b", &priv->calibration_data[1]);
+		if (ret)
+			return ret;
+
+		ret = an8855_get_r50ohm_val(dev, "tx_c", &priv->calibration_data[2]);
+		if (ret)
+			return ret;
+
+		ret = an8855_get_r50ohm_val(dev, "tx_d", &priv->calibration_data[3]);
+		if (ret)
+			return ret;
+	}
+
+	phydev->priv = priv;
+
+	return 0;
+}
+
+static int an8855_get_downshift(struct phy_device *phydev, u8 *data)
+{
+	int val;
+
+	val = phy_read_paged(phydev, AN8855_PHY_PAGE_EXTENDED_1, AN8855_PHY_EXT_REG_14);
+	if (val < 0)
+		return val;
+
+	*data = val & AN8855_PHY_EN_DOWN_SHIFT ? DOWNSHIFT_DEV_DEFAULT_COUNT :
+						 DOWNSHIFT_DEV_DISABLE;
+
+	return 0;
+}
+
+static int an8855_set_downshift(struct phy_device *phydev, u8 cnt)
+{
+	u16 ds = cnt != DOWNSHIFT_DEV_DISABLE ? AN8855_PHY_EN_DOWN_SHIFT : 0;
+
+	return phy_modify_paged(phydev, AN8855_PHY_PAGE_EXTENDED_1,
+				AN8855_PHY_EXT_REG_14, AN8855_PHY_EN_DOWN_SHIFT,
+				ds);
+}
+
+static int an8855_config_init(struct phy_device *phydev)
+{
+	struct air_an8855_priv *priv = phydev->priv;
+	int ret;
+
+	/* Enable HW auto downshift */
+	ret = an8855_set_downshift(phydev, DOWNSHIFT_DEV_DEFAULT_COUNT);
+	if (ret)
+		return ret;
+
+	if (priv->needs_calibration) {
+		ret = phy_modify_mmd(phydev, MDIO_MMD_VEND1, AN8855_PHY_R50OHM_RSEL_TX_AB,
+				     AN8855_PHY_R50OHM_RSEL_TX_A_EN | AN8855_PHY_R50OHM_RSEL_TX_A |
+				     AN8855_PHY_R50OHM_RSEL_TX_B_EN | AN8855_PHY_R50OHM_RSEL_TX_B,
+				     AN8855_PHY_R50OHM_RSEL_TX_A_EN |
+				     FIELD_PREP(AN8855_PHY_R50OHM_RSEL_TX_A,
+						priv->calibration_data[0]) |
+				     AN8855_PHY_R50OHM_RSEL_TX_B_EN |
+				     FIELD_PREP(AN8855_PHY_R50OHM_RSEL_TX_B,
+						priv->calibration_data[1]));
+		if (ret)
+			return ret;
+		ret = phy_modify_mmd(phydev, MDIO_MMD_VEND1, AN8855_PHY_R50OHM_RSEL_TX_CD,
+				     AN8855_PHY_R50OHM_RSEL_TX_C_EN | AN8855_PHY_R50OHM_RSEL_TX_C |
+				     AN8855_PHY_R50OHM_RSEL_TX_D_EN | AN8855_PHY_R50OHM_RSEL_TX_D,
+				     AN8855_PHY_R50OHM_RSEL_TX_C_EN |
+				     FIELD_PREP(AN8855_PHY_R50OHM_RSEL_TX_C,
+						priv->calibration_data[2]) |
+				     AN8855_PHY_R50OHM_RSEL_TX_D_EN |
+				     FIELD_PREP(AN8855_PHY_R50OHM_RSEL_TX_D,
+						priv->calibration_data[3]));
+		if (ret)
+			return ret;
+	}
+
+	/* Apply values to reduce signal noise */
+	ret = phy_modify_mmd(phydev, MDIO_MMD_VEND1, AN8855_PHY_TX_PAIR_DLY_SEL_GBE,
+			     AN8855_PHY_CR_DA_TX_PAIR_DELAY_SEL_A_GBE |
+			     AN8855_PHY_CR_DA_TX_PAIR_DELAY_SEL_C_GBE,
+			     FIELD_PREP(AN8855_PHY_CR_DA_TX_PAIR_DELAY_SEL_A_GBE, 0x4) |
+			     FIELD_PREP(AN8855_PHY_CR_DA_TX_PAIR_DELAY_SEL_C_GBE, 0x4));
+	if (ret)
+		return ret;
+	ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, AN8855_PHY_RXADC_CTRL,
+			       AN8855_PHY_RG_AD_SAMPLE_PHSEL_A |
+			       AN8855_PHY_RG_AD_SAMPLE_PHSEL_C);
+	if (ret)
+		return ret;
+	ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AN8855_PHY_RXADC_REV_0,
+			    FIELD_PREP(AN8855_PHY_RG_AD_RESERVE0_A, 0x1));
+	if (ret)
+		return ret;
+	ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AN8855_PHY_RXADC_REV_1,
+			    FIELD_PREP(AN8855_PHY_RG_AD_RESERVE0_C, 0x1));
+	if (ret)
+		return ret;
+
+	return 0;
+}
+
+static int an8855_get_tunable(struct phy_device *phydev,
+			      struct ethtool_tunable *tuna, void *data)
+{
+	switch (tuna->id) {
+	case ETHTOOL_PHY_DOWNSHIFT:
+		return an8855_get_downshift(phydev, data);
+	default:
+		return -EOPNOTSUPP;
+	}
+}
+
+static int an8855_set_tunable(struct phy_device *phydev,
+			      struct ethtool_tunable *tuna, const void *data)
+{
+	switch (tuna->id) {
+	case ETHTOOL_PHY_DOWNSHIFT:
+		return an8855_set_downshift(phydev, *(const u8 *)data);
+	default:
+		return -EOPNOTSUPP;
+	}
+}
+
+static int an8855_read_page(struct phy_device *phydev)
+{
+	return __phy_read(phydev, AN8855_PHY_SELECT_PAGE);
+}
+
+static int an8855_write_page(struct phy_device *phydev, int page)
+{
+	return __phy_write(phydev, AN8855_PHY_SELECT_PAGE, page);
+}
+
+static struct phy_driver an8855_driver[] = {
+{
+	PHY_ID_MATCH_EXACT(AN8855_PHY_ID),
+	.name			= "Airoha AN8855 internal PHY",
+	/* PHY_GBIT_FEATURES */
+	.flags			= PHY_IS_INTERNAL,
+	.probe			= an8855_probe,
+	.config_init		= an8855_config_init,
+	.soft_reset		= genphy_soft_reset,
+	.get_tunable		= an8855_get_tunable,
+	.set_tunable		= an8855_set_tunable,
+	.suspend		= genphy_suspend,
+	.resume			= genphy_resume,
+	.read_page		= an8855_read_page,
+	.write_page		= an8855_write_page,
+}, };
+
+module_phy_driver(an8855_driver);
+
+static struct mdio_device_id __maybe_unused an8855_tbl[] = {
+	{ PHY_ID_MATCH_EXACT(AN8855_PHY_ID) },
+	{ }
+};
+
+MODULE_DEVICE_TABLE(mdio, an8855_tbl);
+
+MODULE_DESCRIPTION("Airoha AN8855 PHY driver");
+MODULE_AUTHOR("Christian Marangi <ansuelsmth@gmail.com>");
+MODULE_LICENSE("GPL");
-- 
2.55.0

Re: [PATCH net-next v23 5/9] net: phy: Add Airoha AN8855 Internal Switch Gigabit PHY

[Andrew Lunn]

On Fri, Sep 25, 2026 at 08:24:27PM +0200, Christian Marangi wrote:
> Add support for Airoha AN8855 Internal Switch Gigabit PHY.
> 
> This is a simple PHY driver to configure and calibrate the PHY for the
> AN8855 Switch with the use of NVMEM cells.
> 
> Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>

Reviewed-by: Andrew Lunn <andrew@lunn.ch>

    Andrew

Re: [PATCH net-next v23 5/9] net: phy: Add Airoha AN8855 Internal Switch Gigabit PHY

[netdev-bot+sashiko]

Thank you for your contribution! Sashiko AI review found 4 potential
issue(s) to consider.

Critical: 0 · High: 0 · Medium: 4 · Low: 0

If you believe none of the issues are legitimate, please reply to each
issue of Medium severity or higher and explain why the AI is wrong.
If any of them are legitimate and you plan to respin, please let patchwork
know by including "pw-bot: cr" as a separate line at the end of your reply
(one such reply per series is enough).

- [Medium] The downshift tunable accepts retry counts the hardware cannot
  program and reports a sentinel as the count.
- [Medium] Probe fails, and the driver never binds, when the DT has
  "nvmem-cells" but NVMEM support or the AN8855 efuse provider is…
- [Medium] The PHY binding example contradicts the driver and bus.
- [Medium] net: phy: air_an8855: register clobbering in
  AN8855_PHY_RXADC_REV registers

--

net: phy: Add Airoha AN8855 Internal Switch Gigabit PHY

This commit adds a PHY driver for the internal gigabit PHYs of the Airoha
AN8855 switch. At probe time it reads R50 ohm calibration values from NVMEM
cells. In config_init it applies them together with downshift and
noise-reduction settings.

> diff --git a/drivers/net/phy/air_an8855.c b/drivers/net/phy/air_an8855.c
> new file mode 100644
> index 0000000000000..bc22256fd5f95
> --- /dev/null
> +++ b/drivers/net/phy/air_an8855.c
> @@ -0,0 +1,275 @@

[ ... ]

> +static int an8855_probe(struct phy_device *phydev)
> +{
> +	struct device *dev = &phydev->mdio.dev;
> +	struct air_an8855_priv *priv;
> +
> +	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
> +	if (!priv)
> +		return -ENOMEM;
> +
> +	priv->needs_calibration = of_property_present(dev->of_node,
> +						      "nvmem-cells");
> +
> +	if (priv->needs_calibration) {
> +		int ret;
> +
> +		ret = an8855_get_r50ohm_val(dev, "tx_a", &priv->calibration_data[0]);
> +		if (ret)
> +			return ret;

[Severity: Medium]
Do these two writes also clear the B and D reserve fields?

phy_write_mmd() writes the whole 16-bit register. The value written to
AN8855_PHY_RXADC_REV_0 is 0x0100. That sets AN8855_PHY_RG_AD_RESERVE0_A
to 0x1, but it also forces AN8855_PHY_RG_AD_RESERVE0_B (bits 7:0) to
zero. AN8855_PHY_RXADC_REV_1 has the same problem: only
AN8855_PHY_RG_AD_RESERVE0_C is meant to be set, but
AN8855_PHY_RG_AD_RESERVE0_D ends up zeroed as well.

The rest of the noise-reduction sequence in an8855_config_init() only
touches pairs A and C:

- AN8855_PHY_TX_PAIR_DLY_SEL_GBE is updated with phy_modify_mmd(),
  masking only the A and C delay fields.
- AN8855_PHY_RXADC_CTRL uses phy_set_bits_mmd() for the A and C phase
  select bits.

The B and D masks are defined but never used.

Writing the REV registers wholesale breaks that pattern. It overwrites
the hardware reset defaults in the B and D reserve fields, which could
change RX ADC behaviour on those pairs. This happens every time
phy_init_hw() runs config_init, not just once at first attach.

If B and D should keep their defaults, could these be phy_modify_mmd()
calls with AN8855_PHY_RG_AD_RESERVE0_A and AN8855_PHY_RG_AD_RESERVE0_C
as the masks? If the vendor sequence really writes the full register,
could a comment say so?

[Severity: Medium]
Can this probe fail on configurations where the NVMEM cells cannot be read?

needs_calibration depends only on whether "nvmem-cells" is present in the
DT. an8855_probe() returns any error from an8855_get_r50ohm_val().

NVMEM is a bool symbol, so the Kconfig line added in this patch is always
true and has no effect:

    depends on NVMEM || !NVMEM

With CONFIG_NVMEM=n, the stub in include/linux/nvmem-consumer.h is used, so
probe fails with -EOPNOTSUPP:

static inline int nvmem_cell_read_u32(struct device *dev,
				      const char *cell_id, u32 *val)
{
	return -EOPNOTSUPP;
}

With CONFIG_NVMEM=y, the only provider for these cells is
NVMEM_AN8855_EFUSE in drivers/nvmem/Kconfig. It currently has only "depends
on COMPILE_TEST", and nothing in this series changes that. On a
non-COMPILE_TEST config the provider can't be built. nvmem_cell_read_u32()
then keeps returning -EPROBE_DEFER, and this driver never probes.

In both cases, a DT that follows the MFD binding example leaves this driver
unbound, because that example puts nvmem-cells on every PHY.
phy_attach_direct() then falls back to genphy. The downshift and
noise-reduction settings in an8855_config_init() are lost as well, even
though they don't need NVMEM.

Could the calibration be skipped, perhaps with a warning, when the cells are
unavailable? And could the Kconfig dependency reflect what is actually
required?

> +
> +		ret = an8855_get_r50ohm_val(dev, "tx_b", &priv->calibration_data[1]);
> +		if (ret)
> +			return ret;

[ ... ]

> +static int an8855_get_downshift(struct phy_device *phydev, u8 *data)
> +{
> +	int val;
> +
> +	val = phy_read_paged(phydev, AN8855_PHY_PAGE_EXTENDED_1, AN8855_PHY_EXT_REG_14);
> +	if (val < 0)
> +		return val;
> +
> +	*data = val & AN8855_PHY_EN_DOWN_SHIFT ? DOWNSHIFT_DEV_DEFAULT_COUNT :
> +						 DOWNSHIFT_DEV_DISABLE;
> +
> +	return 0;
> +}
> +
> +static int an8855_set_downshift(struct phy_device *phydev, u8 cnt)
> +{
> +	u16 ds = cnt != DOWNSHIFT_DEV_DISABLE ? AN8855_PHY_EN_DOWN_SHIFT : 0;
> +
> +	return phy_modify_paged(phydev, AN8855_PHY_PAGE_EXTENDED_1,
> +				AN8855_PHY_EXT_REG_14, AN8855_PHY_EN_DOWN_SHIFT,
> +				ds);
> +}

[Severity: Medium]
Are retry counts other than enable/disable silently accepted here?

an8855_set_downshift() maps every non-zero cnt to the same enable bit and
returns success. For ETHTOOL_PHY_DOWNSHIFT, ethtool_phy_tunable_valid() in
net/ethtool/ioctl.c only checks len and type_id, so any u8 value reaches
this function. For example, this succeeds without applying a count of 3:

    ethtool --set-phy-tunable ethX downshift on count 3

On the read side, an8855_get_downshift() reports
DOWNSHIFT_DEV_DEFAULT_COUNT (0xff) whenever the bit is set.
DOWNSHIFT_DEV_DEFAULT_COUNT is an input sentinel that means "use the default
count", so a later get shows userspace a count of 255.

Other phylib drivers reject counts they can't program. For example,
bcm54140_set_downshift() does:

	if (cnt > BCM54140_MAX_DOWNSHIFT && cnt != DOWNSHIFT_DEV_DEFAULT_COUNT)
		return -EINVAL;

Could this driver return -EINVAL for counts it can't program, and report the
count the hardware actually uses on get?

[ ... ]

> +static struct phy_driver an8855_driver[] = {
> +{
> +	PHY_ID_MATCH_EXACT(AN8855_PHY_ID),
> +	.name			= "Airoha AN8855 internal PHY",
> +	/* PHY_GBIT_FEATURES */
> +	.flags			= PHY_IS_INTERNAL,
> +	.probe			= an8855_probe,
> +	.config_init		= an8855_config_init,
> +	.soft_reset		= genphy_soft_reset,
> +	.get_tunable		= an8855_get_tunable,
> +	.set_tunable		= an8855_set_tunable,
> +	.suspend		= genphy_suspend,
> +	.resume			= genphy_resume,
> +	.read_page		= an8855_read_page,
> +	.write_page		= an8855_write_page,
> +}, };

[Severity: Medium]
This one is in another patch of the series, "dt-bindings: net: Document
support for AN8855 Switch Internal PHY". Both PHY nodes in that binding
example use:

    compatible = "ethernet-phy-idc0ff.0410",
                 "ethernet-phy-ieee802.3-c45";

Would a DT written from that example make the whole switch fail to probe?

fwnode_mdiobus_register_phy() sets is_c45 from that compatible. When is_c45
is set, it ignores the explicit PHY ID:

	is_c45 = fwnode_device_is_compatible(child, "ethernet-phy-ieee802.3-c45");
	if (is_c45 || fwnode_get_phy_id(child, &phy_id))
		phy = get_phy_device(bus, addr, is_c45);

The per-PHY bus comes from devm_mdio_regmap_register(), which only installs
C22 ops:

	mii->read = mdio_regmap_read_c22;
	mii->write = mdio_regmap_write_c22;

So get_phy_c45_ids()->get_phy_c45_devs_in_pkg()->mdiobus_c45_read() gets
-EOPNOTSUPP. That becomes -EIO, and an8855_core_probe() aborts.

This driver is Clause 22 only: paged access through register 0x1f,
genphy_soft_reset(), and PHY_ID_MATCH_EXACT() on the C22 ID. The MFD binding
example already uses "ethernet-phy-ieee802.3-c22".

Should the PHY binding example use "ethernet-phy-ieee802.3-c22" as well?

-- 
Sashiko AI review · https://netdev-ai.bots.linux.dev/sashiko/#/patchset/20260925182435.21207-1-ansuelsmth%40gmail.com

[PATCH net-next v23 6/9] net: dsa: tag_mtk: add Airoha variant usage of this TAG

[Christian Marangi]

Add variant of the MTK TAG for Airoha Switch and comments about difference
between Airoha AN8855 and Mediatek tag bitmap.

Airoha AN8855 doesn't support controlling SA learning and Leaky VLAN
from tag. Although these bits are not used (and even not defined for
Leaky VLAN), it's worth to add comments for these difference to prevent
any kind of regression in the future if ever these bits will be used.

Rework the makefile, config and tag driver to better report to
external tool (like libpcap) the usage of this variant with a dedicated
"Airoha" name.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
---
 include/net/dsa.h |  2 ++
 net/dsa/Kconfig   | 11 +++++++++++
 net/dsa/Makefile  |  2 +-
 net/dsa/tag_mtk.c | 36 +++++++++++++++++++++++++++++++++---
 4 files changed, 47 insertions(+), 4 deletions(-)

diff --git a/include/net/dsa.h b/include/net/dsa.h
index 5d12191b6f6f..9824c63ad50b 100644
--- a/include/net/dsa.h
+++ b/include/net/dsa.h
@@ -62,6 +62,7 @@ struct tc_action;
 #define DSA_TAG_PROTO_KSZ8463_VALUE		34
 #define DSA_TAG_PROTO_MT7628_VALUE		35
 #define DSA_TAG_PROTO_KS8995_VALUE		36
+#define DSA_TAG_PROTO_AIROHA_VALUE		37
 
 enum dsa_tag_protocol {
 	DSA_TAG_PROTO_NONE		= DSA_TAG_PROTO_NONE_VALUE,
@@ -76,6 +77,7 @@ enum dsa_tag_protocol {
 	DSA_TAG_PROTO_KSZ9893		= DSA_TAG_PROTO_KSZ9893_VALUE,
 	DSA_TAG_PROTO_LAN9303		= DSA_TAG_PROTO_LAN9303_VALUE,
 	DSA_TAG_PROTO_MTK		= DSA_TAG_PROTO_MTK_VALUE,
+	DSA_TAG_PROTO_AIROHA		= DSA_TAG_PROTO_AIROHA_VALUE,
 	DSA_TAG_PROTO_QCA		= DSA_TAG_PROTO_QCA_VALUE,
 	DSA_TAG_PROTO_TRAILER		= DSA_TAG_PROTO_TRAILER_VALUE,
 	DSA_TAG_PROTO_8021Q		= DSA_TAG_PROTO_8021Q_VALUE,
diff --git a/net/dsa/Kconfig b/net/dsa/Kconfig
index 4f44bf3ede23..28a249f04a43 100644
--- a/net/dsa/Kconfig
+++ b/net/dsa/Kconfig
@@ -24,6 +24,13 @@ config NET_DSA_TAG_NONE
 	  Say Y or M if you want to enable support for switches which don't tag
 	  frames over the CPU port.
 
+config NET_DSA_TAG_AIROHA
+	tristate "Tag driver for Airoha switches"
+	select NET_DSA_TAG_MTK_COMMON
+	help
+	  Say Y or M if you want to enable support for tagging frames for
+	  Airoha switches.
+
 config NET_DSA_TAG_AR9331
 	tristate "Tag driver for Atheros AR9331 SoC with built-in switch"
 	help
@@ -104,8 +111,12 @@ config NET_DSA_TAG_MT7628
 	  Say Y or M if you want to enable support for tagging frames for the
 	  switch embedded in the MT7628 SoC.
 
+config NET_DSA_TAG_MTK_COMMON
+	tristate
+
 config NET_DSA_TAG_MTK
 	tristate "Tag driver for Mediatek switches"
+	select NET_DSA_TAG_MTK_COMMON
 	help
 	  Say Y or M if you want to enable support for tagging frames for
 	  Mediatek switches.
diff --git a/net/dsa/Makefile b/net/dsa/Makefile
index 1f9cc30e9988..7ccaa528a989 100644
--- a/net/dsa/Makefile
+++ b/net/dsa/Makefile
@@ -29,7 +29,7 @@ obj-$(CONFIG_NET_DSA_TAG_KS8995) += tag_ks8995.o
 obj-$(CONFIG_NET_DSA_TAG_KSZ) += tag_ksz.o
 obj-$(CONFIG_NET_DSA_TAG_LAN9303) += tag_lan9303.o
 obj-$(CONFIG_NET_DSA_TAG_MT7628) += tag_mt7628.o
-obj-$(CONFIG_NET_DSA_TAG_MTK) += tag_mtk.o
+obj-$(CONFIG_NET_DSA_TAG_MTK_COMMON) += tag_mtk.o
 obj-$(CONFIG_NET_DSA_TAG_MXL_862XX) += tag_mxl862xx.o
 obj-$(CONFIG_NET_DSA_TAG_MXL_GSW1XX) += tag_mxl-gsw1xx.o
 obj-$(CONFIG_NET_DSA_TAG_NETC) += tag_netc.o
diff --git a/net/dsa/tag_mtk.c b/net/dsa/tag_mtk.c
index c7dc7731675e..f8087d768da6 100644
--- a/net/dsa/tag_mtk.c
+++ b/net/dsa/tag_mtk.c
@@ -11,6 +11,7 @@
 #include "tag.h"
 
 #define MTK_NAME		"mtk"
+#define AIROHA_NAME		"airoha"
 
 #define MTK_HDR_LEN		4
 #define MTK_HDR_XMIT_UNTAGGED		0
@@ -18,6 +19,9 @@
 #define MTK_HDR_XMIT_TAGGED_TPID_88A8	2
 #define MTK_HDR_RECV_SOURCE_PORT_MASK	GENMASK(2, 0)
 #define MTK_HDR_XMIT_DP_BIT_MASK	GENMASK(5, 0)
+/* AN8855 doesn't support SA_DIS and Leaky VLAN
+ * control in tag as these bits doesn't exist.
+ */
 #define MTK_HDR_XMIT_SA_DIS		BIT(6)
 
 static struct sk_buff *mtk_tag_xmit(struct sk_buff *skb,
@@ -99,6 +103,7 @@ static struct sk_buff *mtk_tag_rcv(struct sk_buff *skb, struct net_device *dev)
 	return skb;
 }
 
+#if IS_ENABLED(CONFIG_NET_DSA_TAG_MTK)
 static const struct dsa_device_ops mtk_netdev_ops = {
 	.name		= MTK_NAME,
 	.proto		= DSA_TAG_PROTO_MTK,
@@ -107,8 +112,33 @@ static const struct dsa_device_ops mtk_netdev_ops = {
 	.needed_headroom = MTK_HDR_LEN,
 };
 
-MODULE_DESCRIPTION("DSA tag driver for Mediatek switches");
-MODULE_LICENSE("GPL");
+DSA_TAG_DRIVER(mtk_netdev_ops);
 MODULE_ALIAS_DSA_TAG_DRIVER(DSA_TAG_PROTO_MTK, MTK_NAME);
+#endif
 
-module_dsa_tag_driver(mtk_netdev_ops);
+#if IS_ENABLED(CONFIG_NET_DSA_TAG_AIROHA)
+static const struct dsa_device_ops airoha_netdev_ops = {
+	.name		= AIROHA_NAME,
+	.proto		= DSA_TAG_PROTO_AIROHA,
+	.xmit		= mtk_tag_xmit,
+	.rcv		= mtk_tag_rcv,
+	.needed_headroom = MTK_HDR_LEN,
+};
+
+DSA_TAG_DRIVER(airoha_netdev_ops);
+MODULE_ALIAS_DSA_TAG_DRIVER(DSA_TAG_PROTO_AIROHA, AIROHA_NAME);
+#endif
+
+static struct dsa_tag_driver *dsa_tag_driver_array[] =	{
+#if IS_ENABLED(CONFIG_NET_DSA_TAG_MTK)
+	&DSA_TAG_DRIVER_NAME(mtk_netdev_ops),
+#endif
+#if IS_ENABLED(CONFIG_NET_DSA_TAG_AIROHA)
+	&DSA_TAG_DRIVER_NAME(airoha_netdev_ops),
+#endif
+};
+
+module_dsa_tag_drivers(dsa_tag_driver_array);
+
+MODULE_DESCRIPTION("DSA tag driver for Mediatek switches");
+MODULE_LICENSE("GPL");
-- 
2.55.0

Re: [PATCH net-next v23 6/9] net: dsa: tag_mtk: add Airoha variant usage of this TAG

[Andrew Lunn]

On Fri, Sep 25, 2026 at 08:24:28PM +0200, Christian Marangi wrote:
> Add variant of the MTK TAG for Airoha Switch and comments about difference
> between Airoha AN8855 and Mediatek tag bitmap.
> 
> Airoha AN8855 doesn't support controlling SA learning and Leaky VLAN
> from tag. Although these bits are not used (and even not defined for
> Leaky VLAN), it's worth to add comments for these difference to prevent
> any kind of regression in the future if ever these bits will be used.
> 
> Rework the makefile, config and tag driver to better report to
> external tool (like libpcap) the usage of this variant with a dedicated
> "Airoha" name.
> 
> Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>

Reviewed-by: Andrew Lunn <andrew@lunn.ch>

    Andrew

Re: [PATCH net-next v23 6/9] net: dsa: tag_mtk: add Airoha variant usage of this TAG

[netdev-bot+sashiko]

Thank you for your contribution! Sashiko AI review found 1 potential
issue(s) to consider.

Critical: 0 · High: 0 · Medium: 1 · Low: 0

If you believe none of the issues are legitimate, please reply to each
issue of Medium severity or higher and explain why the AI is wrong.
If any of them are legitimate and you plan to respin, please let patchwork
know by including "pw-bot: cr" as a separate line at the end of your reply
(one such reply per series is enough).

- [Medium] The patch adds DSA_TAG_PROTO_AIROHA (37) and gives it the same
  handlers as DSA_TAG_PROTO_MTK (mtk_tag_xmit/mtk_tag_rcv, MTK_HDR_LEN…

--

net: dsa: tag_mtk: add Airoha variant usage of this TAG

This adds a DSA_TAG_PROTO_AIROHA protocol ID and an "airoha" tag driver
that reuses the MTK xmit/rcv handlers. It also adds comments on how the
AN8855 tag bitmap differs from the Mediatek one. Kconfig and the Makefile
now build tag_mtk.o through a shared NET_DSA_TAG_MTK_COMMON symbol.

> diff --git a/net/dsa/tag_mtk.c b/net/dsa/tag_mtk.c
> index c7dc7731675ec..f8087d768da6d 100644
> --- a/net/dsa/tag_mtk.c
> +++ b/net/dsa/tag_mtk.c

[ ... ]

> @@ -107,8 +112,33 @@ static const struct dsa_device_ops mtk_netdev_ops = {
>  	.needed_headroom = MTK_HDR_LEN,
>  };
>
> -MODULE_DESCRIPTION("DSA tag driver for Mediatek switches");
> -MODULE_LICENSE("GPL");
> +DSA_TAG_DRIVER(mtk_netdev_ops);
>  MODULE_ALIAS_DSA_TAG_DRIVER(DSA_TAG_PROTO_MTK, MTK_NAME);
> +#endif
>
> -module_dsa_tag_driver(mtk_netdev_ops);
> +#if IS_ENABLED(CONFIG_NET_DSA_TAG_AIROHA)
> +static const struct dsa_device_ops airoha_netdev_ops = {
> +	.name		= AIROHA_NAME,
> +	.proto		= DSA_TAG_PROTO_AIROHA,
> +	.xmit		= mtk_tag_xmit,
> +	.rcv		= mtk_tag_rcv,
> +	.needed_headroom = MTK_HDR_LEN,
> +};

[Severity: Medium]
Frames on the wire are identical for DSA_TAG_PROTO_AIROHA and
DSA_TAG_PROTO_MTK. What about the conduit Ethernet drivers that check for
the MTK tag format by comparing against DSA_TAG_PROTO_MTK? None of them
are updated here.

Later in this series, an8855_get_tag_protocol() returns
DSA_TAG_PROTO_AIROHA. For an AN8855 behind a MediaTek or Airoha SoC
conduit, dsa_ptr->tag_ops->proto would then be 37, and these checks
would stop matching.

drivers/net/ethernet/mediatek/mtk_eth_soc.c:mtk_uses_dsa() {
	return netdev_uses_dsa(dev) &&
	       dev->dsa_ptr->tag_ops->proto == DSA_TAG_PROTO_MTK;
}

On NETSYS v1, mtk_open() would then take the else branch. It clears
MTK_CDMP_STAG_EN and skips the dsa_meta allocation, so hardware special
tag untagging is turned off.

drivers/net/ethernet/mediatek/mtk_ppe.c:__mtk_ppe_check_skb() {
	case htons(ETH_P_XDSA):
		if (!netdev_uses_dsa(skb->dev) ||
		    skb->dev->dsa_ptr->tag_ops->proto != DSA_TAG_PROTO_MTK)
			goto out;
}

drivers/net/ethernet/mediatek/mtk_ppe_offload.c:mtk_flow_get_dsa_port() {
	if (dp->cpu_dp->tag_ops->proto != DSA_TAG_PROTO_MTK)
		return -ENODEV;
}

These two checks mean PPE entries are never bound for DSA frames, and
flowtable hardware offload through the switch ports would be refused.

drivers/net/ethernet/airoha/airoha_eth.c:airoha_get_dsa_tag() {
	if (dev->dsa_ptr->tag_ops->proto != DSA_TAG_PROTO_MTK)
		return 0;
}

On the Airoha conduit, this returns before the VLAN TPID is restored and
before the special tag is moved into the QDMA descriptor. The comment in
that function says the PPE needs that move. airoha_dev_xmit() would then
send the frame with the inline tag and SP_TAG=0.

airoha_get_dsa_port() in airoha_ppe.c has no proto check, though, so the
Airoha PPE would still accept flow offload for these ports. Can the TX
path and the PPE path then disagree about how the tag is handled?

The commit message describes this as giving external tools like libpcap
a dedicated "Airoha" name. It doesn't mention these behaviour changes on
the conduit side.

Should these call sites accept both protocols in this series, for
example through a helper that checks for an MTK-format tag?

> +
> +DSA_TAG_DRIVER(airoha_netdev_ops);
> +MODULE_ALIAS_DSA_TAG_DRIVER(DSA_TAG_PROTO_AIROHA, AIROHA_NAME);
> +#endif

[ ... ]

-- 
Sashiko AI review · https://netdev-ai.bots.linux.dev/sashiko/#/patchset/20260925182435.21207-1-ansuelsmth%40gmail.com

[PATCH net-next v23 7/9] MAINTAINERS: add myself as maintainer for Airoha AN8855 Switch

[Christian Marangi]

Add myself as maintainer for AN8855 DSA driver and all the related
subdriver (mfd, mdio, phy, nvmem)

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
---
 MAINTAINERS | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index 6de1ff058db6..f6749933aa0b 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -759,6 +759,22 @@ S:	Maintained
 F:	Documentation/devicetree/bindings/net/airoha,en7581-eth.yaml
 F:	drivers/net/ethernet/airoha/
 
+AIROHA AN8855 DSA DRIVER
+M:	Christian Marangi <ansuelsmth@gmail.com>
+L:	linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
+L:	linux-mediatek@lists.infradead.org (moderated for non-subscribers)
+L:	netdev@vger.kernel.org
+S:	Maintained
+F:	Documentation/devicetree/bindings/mfd/airoha,an8855.yaml
+F:	Documentation/devicetree/bindings/net/airoha,an8855-phy.yaml
+F:	Documentation/devicetree/bindings/net/dsa/airoha,an8855-switch.yaml
+F:	Documentation/devicetree/bindings/nvmem/airoha,an8855-efuse.yaml
+F:	drivers/mfd/airoha-an8855.c
+F:	drivers/net/dsa/an8855.c
+F:	drivers/net/dsa/an8855.h
+F:	drivers/net/phy/air_an8855.c
+F:	drivers/nvmem/an8855-efuse.c
+
 AIROHA PCIE PHY DRIVER
 M:	Lorenzo Bianconi <lorenzo@kernel.org>
 L:	linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
-- 
2.55.0

Re: [PATCH net-next v23 7/9] MAINTAINERS: add myself as maintainer for Airoha AN8855 Switch

[Andrew Lunn]

On Fri, Sep 25, 2026 at 08:24:29PM +0200, Christian Marangi wrote:
> Add myself as maintainer for AN8855 DSA driver and all the related
> subdriver (mfd, mdio, phy, nvmem)
> 
> Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>

Reviewed-by: Andrew Lunn <andrew@lunn.ch>

    Andrew

[PATCH net-next v23 9/9] net: dsa: Add Airoha AN8855 5-Port Gigabit DSA Switch driver

[Christian Marangi]

Add Airoha AN8855 5-Port Gigabit DSA switch. Switch can support
10M, 100M, 1Gb, 2.5G and 5G Ethernet Speed but 5G is currently error out
as it's not currently supported as requires additional configuration for
the PCS.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
---
 drivers/net/dsa/Kconfig      |   10 +
 drivers/net/dsa/Makefile     |    1 +
 drivers/net/dsa/an8855.c     | 1740 ++++++++++++++++++++++++++++++++++
 drivers/net/dsa/an8855.h     |  755 +++++++++++++++
 drivers/net/dsa/mt7530-lib.c |   68 +-
 drivers/net/dsa/mt7530-lib.h |   22 +
 6 files changed, 2576 insertions(+), 20 deletions(-)
 create mode 100644 drivers/net/dsa/an8855.c
 create mode 100644 drivers/net/dsa/an8855.h

diff --git a/drivers/net/dsa/Kconfig b/drivers/net/dsa/Kconfig
index f13ac7e77200..1753578c8e03 100644
--- a/drivers/net/dsa/Kconfig
+++ b/drivers/net/dsa/Kconfig
@@ -24,6 +24,16 @@ config NET_DSA_LOOP
 	  This enables support for a fake mock-up switch chip which
 	  exercises the DSA APIs.
 
+config NET_DSA_AN8855
+	tristate "Airoha AN8855 Ethernet switch support"
+	depends on MFD_AIROHA_AN8855 || COMPILE_TEST
+	depends on NET_DSA
+	select NET_DSA_MT7530_LIB
+	select NET_DSA_TAG_AIROHA
+	help
+	  This enables support for the Ethernet switch inside the
+	  Airoha AN8855 chip.
+
 source "drivers/net/dsa/hirschmann/Kconfig"
 
 source "drivers/net/dsa/lantiq/Kconfig"
diff --git a/drivers/net/dsa/Makefile b/drivers/net/dsa/Makefile
index 447e849a78e5..76888495c5b3 100644
--- a/drivers/net/dsa/Makefile
+++ b/drivers/net/dsa/Makefile
@@ -1,4 +1,5 @@
 # SPDX-License-Identifier: GPL-2.0
+obj-$(CONFIG_NET_DSA_AN8855)	+= an8855.o
 obj-$(CONFIG_NET_DSA_BCM_SF2)	+= bcm-sf2.o
 bcm-sf2-objs			:= bcm_sf2.o bcm_sf2_cfp.o
 obj-$(CONFIG_NET_DSA_LOOP)	+= dsa_loop.o
diff --git a/drivers/net/dsa/an8855.c b/drivers/net/dsa/an8855.c
new file mode 100644
index 000000000000..428d7dd85dd8
--- /dev/null
+++ b/drivers/net/dsa/an8855.c
@@ -0,0 +1,1740 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Airoha AN8855 DSA Switch driver
+ * Copyright (C) 2023 Min Yao <min.yao@airoha.com>
+ * Copyright (C) 2024 Christian Marangi <ansuelsmth@gmail.com>
+ */
+#include <linux/bitfield.h>
+#include <linux/ethtool.h>
+#include <linux/etherdevice.h>
+#include <linux/if_bridge.h>
+#include <linux/iopoll.h>
+#include <linux/netdevice.h>
+#include <linux/of_net.h>
+#include <linux/of_platform.h>
+#include <linux/phylink.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+#include <net/dsa.h>
+
+#include "an8855.h"
+#include "mt7530-lib.h"
+
+static const struct mt7530_reg_field an8855_fields[] = {
+	{ MT7530_BC_FFP, REG_FIELD(AN8855_BCF, 0, 7) },
+	{ MT7530_UNM_FFP, REG_FIELD(AN8855_UNMF, 0, 7) },
+	{ MT7530_UNU_FFP, REG_FIELD(AN8855_UNUF, 0, 7) },
+
+	{ MT7530_CCR_MIB_ENABLE, REG_FIELD(AN8855_MIB_CCR, 31, 31) },
+	{ MT7530_CCR_RX_OCT_CNT_GOOD, REG_FIELD(AN8855_MIB_CCR, 7, 7) },
+	{ MT7530_CCR_RX_OCT_CNT_BAD, REG_FIELD(AN8855_MIB_CCR, 6, 6) },
+	{ MT7530_CCR_TX_OCT_CNT_GOOD, REG_FIELD(AN8855_MIB_CCR, 5, 5) },
+	{ MT7530_CCR_TX_OCT_CNT_BAD, REG_FIELD(AN8855_MIB_CCR, 4, 4) },
+
+	{ MT7530_BPDU_EG_TAG, REG_FIELD(AN8855_BPC, 9, 11) },
+	{ MT7530_BPDU_PORT_FW, REG_FIELD(AN8855_BPC, 0, 2) },
+	{ MT7530_PAE_BPDU_FR, REG_FIELD(AN8855_PAC, 28, 28) },
+	{ MT7530_PAE_EG_TAG, REG_FIELD(AN8855_PAC, 25, 27) },
+	{ MT7530_PAE_PORT_FW, REG_FIELD(AN8855_PAC, 16, 18) },
+	{ MT7530_R01_BPDU_FR, REG_FIELD(AN8855_RGAC1, 12, 12) },
+	{ MT7530_R01_EG_TAG, REG_FIELD(AN8855_RGAC1, 9, 11) },
+	{ MT7530_R01_PORT_FW, REG_FIELD(AN8855_RGAC1, 0, 2) },
+	{ MT7530_R02_BPDU_FR, REG_FIELD(AN8855_RGAC1, 28, 28) },
+	{ MT7530_R02_EG_TAG, REG_FIELD(AN8855_RGAC1, 25, 27) },
+	{ MT7530_R02_PORT_FW, REG_FIELD(AN8855_RGAC1, 16, 18) },
+	{ MT7530_R03_BPDU_FR, REG_FIELD(AN8855_RGAC2, 12, 12) },
+	{ MT7530_R03_EG_TAG, REG_FIELD(AN8855_RGAC2, 9, 11) },
+	{ MT7530_R03_PORT_FW, REG_FIELD(AN8855_RGAC2, 0, 2) },
+	{ MT7530_R0E_BPDU_FR, REG_FIELD(AN8855_RGAC2, 28, 28) },
+	{ MT7530_R0E_EG_TAG, REG_FIELD(AN8855_RGAC2, 25, 27) },
+	{ MT7530_R0E_PORT_FW, REG_FIELD(AN8855_RGAC2, 16, 18) },
+
+	{ MT7530_VAWD_IVL_MAC, REG_FIELD(AN8855_VAWD0, 5, 5) },
+	{ MT7530_VAWD_EG_CON, REG_FIELD(AN8855_VAWD0, 11, 11) },
+	{ MT7530_VAWD_VTAG_EN, REG_FIELD(AN8855_VAWD0, 10, 10) },
+	{ MT7530_VAWD_PORT_MEM, REG_FIELD(AN8855_VAWD0, 26, 31) },
+	{ MT7530_VAWD_FID, REG_FIELD(AN8855_VAWD0, 1, 4) },
+	{ MT7530_VAWD_VLAN_VALID, REG_FIELD(AN8855_VAWD0, 0, 0) },
+	{ __MT7530_VAWD1, REG_FIELD(AN8855_VAWD0, 0, 31) },
+
+	{ MT7530_VAWD_ETAG, REG_FIELD(AN8855_VAWD0, 12, 23) },
+	{ __MT7530_VAWD2, REG_FIELD(AN8855_VAWD1, 0, 31) },
+
+	{ MT7530_VTCR_BUSY, REG_FIELD(AN8855_VTCR, 31, 31) },
+	{ MT7530_VTCR_FUNC, REG_FIELD(AN8855_VTCR, 12, 15) },
+	{ MT7530_VTCR_VID, REG_FIELD(AN8855_VTCR, 0, 11) },
+
+	{ MT7530_ATWD_CVID, REG_FIELD(AN8855_ATWD, 16, 27), },
+	{ MT7530_ATWD_IVL, REG_FIELD(AN8855_ATWD, 15, 15), },
+	{ MT7530_ATWD_FID, REG_FIELD(AN8855_ATWD, 28, 31), },
+	{ MT7530_ATWD_AGE_TIMER, REG_FIELD(AN8855_ATA2, 0, 8), },
+	{ MT7530_ATWD_PORT_MAP, REG_FIELD(AN8855_ATWD2, 0, 7), },
+	{ AN8855_ATWD_TYPE, REG_FIELD(AN8855_ATA2, 9, 9), },
+	{ AN8855_ATWD_VLD, REG_FIELD(AN8855_ATWD, 0, 0), },
+	{ MT7530_ATWD_MAC_BYTE_5, REG_FIELD(AN8855_ATA2, 16, 23), },
+	{ MT7530_ATWD_MAC_BYTE_4, REG_FIELD(AN8855_ATA2, 24, 31), },
+	{ MT7530_ATWD_MAC_BYTE_3, REG_FIELD(AN8855_ATA1, 0, 7), },
+	{ MT7530_ATWD_MAC_BYTE_2, REG_FIELD(AN8855_ATA1, 8, 15), },
+	{ MT7530_ATWD_MAC_BYTE_1, REG_FIELD(AN8855_ATA1, 16, 23), },
+	{ MT7530_ATWD_MAC_BYTE_0, REG_FIELD(AN8855_ATA1, 24, 31), },
+
+	{ __MT7530_ATWD1, REG_FIELD(AN8855_ATWD, 0, 31), },
+	{ __MT7530_ATWD2, REG_FIELD(AN8855_ATWD2, 0, 31), },
+	{ __MT7530_ATWD3, REG_FIELD(AN8855_ATA1, 0, 31), },
+	{ __MT7530_ATWD4, REG_FIELD(AN8855_ATA2, 0, 31), },
+
+	{ MT7530_ATRD_CVID, REG_FIELD(AN8855_ATRD0, 10, 21), },
+	{ MT7530_ATRD_AGE_TIMER, REG_FIELD(AN8855_ATRD1, 3, 11), },
+	{ MT7530_ATRD_PORT_MAP, REG_FIELD(AN8855_ATRD3, 0, 7), },
+	{ AN8855_ATRD_ARP, REG_FIELD(AN8855_ATRD0, 1, 2), },
+	{ MT7530_ATRD_MAC_BYTE_5, REG_FIELD(AN8855_ATRD1, 16, 23), },
+	{ MT7530_ATRD_MAC_BYTE_4, REG_FIELD(AN8855_ATRD1, 24, 31), },
+	{ MT7530_ATRD_MAC_BYTE_3, REG_FIELD(AN8855_ATRD2, 0, 7), },
+	{ MT7530_ATRD_MAC_BYTE_2, REG_FIELD(AN8855_ATRD2, 8, 15), },
+	{ MT7530_ATRD_MAC_BYTE_1, REG_FIELD(AN8855_ATRD2, 16, 23), },
+	{ MT7530_ATRD_MAC_BYTE_0, REG_FIELD(AN8855_ATRD2, 24, 31), },
+
+	{ MT7530_ATC_BUSY, REG_FIELD(AN8855_ATC, 31, 31), },
+	{ MT7530_ATC_MAT, REG_FIELD(AN8855_ATC, 7, 11), },
+	{ MT7530_ATC_CMD, REG_FIELD(AN8855_ATC, 0, 2), },
+	{ __MT7530_ATC, REG_FIELD(AN8855_ATC, 0, 31), },
+
+	{ MT7530_MIRROR_EN, REG_FIELD(AN8855_MIR, 7, 7) },
+	{ MT7530_MIRROR_PORT, REG_FIELD(AN8855_MIR, 0, 4) },
+
+	{ MT7530_SSP_FID_PST, REG_FIELD_ID(AN8855_SSP, 0, 15, AN8855_NUM_PORTS, 0x200) },
+
+	{ MT7530_PCR_PORT_TX_MIR, REG_FIELD_ID(AN8855_PCR, 20, 20, AN8855_NUM_PORTS, 0x200) },
+	{ MT7530_PCR_PORT_RX_MIR, REG_FIELD_ID(AN8855_PCR, 16, 16, AN8855_NUM_PORTS, 0x200) },
+	{ MT7530_PCR_PORT_VLAN, REG_FIELD_ID(AN8855_PCR, 0, 1, AN8855_NUM_PORTS, 0x200) },
+
+	{ MT7530_PCR_MATRIX, REG_FIELD_ID(AN8855_PORTMATRIX, 0, 5, AN8855_NUM_PORTS, 0x200) },
+
+	{ MT7530_PSC_SA_DIS, REG_FIELD_ID(AN8855_PSC, 4, 4, AN8855_NUM_PORTS, 0x200) },
+
+	{ MT7530_PVC_EG_TAG, REG_FIELD_ID(AN8855_PVC, 8, 10, AN8855_NUM_PORTS, 0x200) },
+	{ MT7530_PVC_VLAN_ATTR, REG_FIELD_ID(AN8855_PVC, 6, 7, AN8855_NUM_PORTS, 0x200) },
+	{ MT7530_PVC_ACC_FRM, REG_FIELD_ID(AN8855_PVC, 0, 1, AN8855_NUM_PORTS, 0x200) },
+
+	{ MT7530_PPBV1_G0_PORT_VID, REG_FIELD_ID(AN8855_PPBV1, 0, 11, AN8855_NUM_PORTS, 0x200) },
+	{ AN8855_PVID_G0_PORT_VID, REG_FIELD_ID(AN8855_PVID, 0, 11, AN8855_NUM_PORTS, 0x200) },
+
+	{ MT7530_GMACCR_MAX_RX_JUMBO, REG_FIELD(AN8855_GMACCR, 4, 7) },
+	{ MT7530_GMACCR_MAX_RX_PKT_LEN, REG_FIELD(AN8855_GMACCR, 0, 1) },
+
+	{ MT7530_MIB_TX_DROP, REG_FIELD_ID(AN8855_PORT_MIB_TX_DROP, 0, 31, AN8855_NUM_PORTS, 0x200) },
+	{ MT7530_MIB_TX_CRC_ERR, REG_FIELD_ID(AN8855_PORT_MIB_TX_CRC_ERR, 0, 31, AN8855_NUM_PORTS, 0x200) },
+	{ MT7530_MIB_TX_UNICAST, REG_FIELD_ID(AN8855_PORT_MIB_TX_UNICAST, 0, 31, AN8855_NUM_PORTS, 0x200) },
+	{ MT7530_MIB_TX_MULTICAST, REG_FIELD_ID(AN8855_PORT_MIB_TX_MULTICAST, 0, 31, AN8855_NUM_PORTS, 0x200) },
+	{ MT7530_MIB_TX_BROADCAST, REG_FIELD_ID(AN8855_PORT_MIB_TX_BROADCAST, 0, 31, AN8855_NUM_PORTS, 0x200) },
+	{ MT7530_MIB_TX_COLLISION, REG_FIELD_ID(AN8855_PORT_MIB_TX_COLLISION, 0, 31, AN8855_NUM_PORTS, 0x200) },
+	{ MT7530_MIB_TX_SINGLE_COLLISION, REG_FIELD_ID(AN8855_PORT_MIB_TX_SINGLE_COLLISION, 0, 31, AN8855_NUM_PORTS, 0x200) },
+	{ MT7530_MIB_TX_MULTIPLE_COLLISION, REG_FIELD_ID(AN8855_PORT_MIB_TX_MULTIPLE_COLLISION, 0, 31, AN8855_NUM_PORTS, 0x200) },
+	{ MT7530_MIB_TX_DEFERRED, REG_FIELD_ID(AN8855_PORT_MIB_TX_DEFERRED, 0, 31, AN8855_NUM_PORTS, 0x200) },
+	{ MT7530_MIB_TX_LATE_COLLISION, REG_FIELD_ID(AN8855_PORT_MIB_TX_LATE_COLLISION, 0, 31, AN8855_NUM_PORTS, 0x200) },
+	{ MT7530_MIB_TX_EXCESSIVE_COLLISION, REG_FIELD_ID(AN8855_PORT_MIB_TX_EXCESSIVE_COLLISION, 0, 31, AN8855_NUM_PORTS, 0x200) },
+	{ MT7530_MIB_TX_PAUSE, REG_FIELD_ID(AN8855_PORT_MIB_TX_PAUSE, 0, 31, AN8855_NUM_PORTS, 0x200) },
+	{ MT7530_MIB_TX_PKT_SZ_64, REG_FIELD_ID(AN8855_PORT_MIB_TX_PKT_SZ_64, 0, 31, AN8855_NUM_PORTS, 0x200) },
+	{ MT7530_MIB_TX_PKT_SZ_65_TO_127, REG_FIELD_ID(AN8855_PORT_MIB_TX_PKT_SZ_65_TO_127, 0, 31, AN8855_NUM_PORTS, 0x200) },
+	{ MT7530_MIB_TX_PKT_SZ_128_TO_255, REG_FIELD_ID(AN8855_PORT_MIB_TX_PKT_SZ_128_TO_255, 0, 31, AN8855_NUM_PORTS, 0x200) },
+	{ MT7530_MIB_TX_PKT_SZ_256_TO_511, REG_FIELD_ID(AN8855_PORT_MIB_TX_PKT_SZ_256_TO_511, 0, 31, AN8855_NUM_PORTS, 0x200) },
+	{ MT7530_MIB_TX_PKT_SZ_512_TO_1023, REG_FIELD_ID(AN8855_PORT_MIB_TX_PKT_SZ_512_TO_1023, 0, 31, AN8855_NUM_PORTS, 0x200) },
+	{ AN8855_MIB_TX_PKT_SZ_1024_TO_1518, REG_FIELD_ID(AN8855_PORT_MIB_TX_PKT_SZ_1024_TO_1518, 0, 31, AN8855_NUM_PORTS, 0x200) },
+	{ AN8855_MIB_TX_PKT_SZ_1519_TO_MAX, REG_FIELD_ID(AN8855_PORT_MIB_TX_PKT_SZ_1519_TO_MAX, 0, 31, AN8855_NUM_PORTS, 0x200) },
+	{ MT7530_MIB_TX_BYTES_LOW, REG_FIELD_ID(AN8855_PORT_MIB_TX_BYTES_LOW, 0, 31, AN8855_NUM_PORTS, 0x200) },
+	{ MT7530_MIB_TX_BYTES_HIGH, REG_FIELD_ID(AN8855_PORT_MIB_TX_BYTES_HIGH, 0, 31, AN8855_NUM_PORTS, 0x200) },
+	{ AN8855_MIB_TX_OVERSIZE_DROP, REG_FIELD_ID(AN8855_PORT_MIB_TX_OVERSIZE_DROP, 0, 31, AN8855_NUM_PORTS, 0x200) },
+	{ AN8855_MIB_TX_BAD_PKT_BYTES_LOW, REG_FIELD_ID(AN8855_PORT_MIB_TX_BAD_PKT_BYTES_LOW, 0, 31, AN8855_NUM_PORTS, 0x200) },
+	{ AN8855_MIB_TX_BAD_PKT_BYTES_HIGH, REG_FIELD_ID(AN8855_PORT_MIB_TX_BAD_PKT_BYTES_HIGH, 0, 31, AN8855_NUM_PORTS, 0x200) },
+	{ MT7530_MIB_RX_DROP, REG_FIELD_ID(AN8855_PORT_MIB_RX_DROP, 0, 31, AN8855_NUM_PORTS, 0x200) },
+	{ MT7530_MIB_RX_FILTERING, REG_FIELD_ID(AN8855_PORT_MIB_RX_FILTERING, 0, 31, AN8855_NUM_PORTS, 0x200) },
+	{ MT7530_MIB_RX_UNICAST, REG_FIELD_ID(AN8855_PORT_MIB_RX_UNICAST, 0, 31, AN8855_NUM_PORTS, 0x200) },
+	{ MT7530_MIB_RX_MULTICAST, REG_FIELD_ID(AN8855_PORT_MIB_RX_MULTICAST, 0, 31, AN8855_NUM_PORTS, 0x200) },
+	{ MT7530_MIB_RX_BROADCAST, REG_FIELD_ID(AN8855_PORT_MIB_RX_BROADCAST, 0, 31, AN8855_NUM_PORTS, 0x200) },
+	{ MT7530_MIB_RX_ALIGN_ERR, REG_FIELD_ID(AN8855_PORT_MIB_RX_ALIGN_ERR, 0, 31, AN8855_NUM_PORTS, 0x200) },
+	{ MT7530_MIB_RX_CRC_ERR, REG_FIELD_ID(AN8855_PORT_MIB_RX_CRC_ERR, 0, 31, AN8855_NUM_PORTS, 0x200) },
+	{ MT7530_MIB_RX_UNDER_SIZE_ERR, REG_FIELD_ID(AN8855_PORT_MIB_RX_UNDER_SIZE_ERR, 0, 31, AN8855_NUM_PORTS, 0x200) },
+	{ MT7530_MIB_RX_FRAG_ERR, REG_FIELD_ID(AN8855_PORT_MIB_RX_FRAG_ERR, 0, 31, AN8855_NUM_PORTS, 0x200) },
+	{ MT7530_MIB_RX_OVER_SZ_ERR, REG_FIELD_ID(AN8855_PORT_MIB_RX_OVER_SZ_ERR, 0, 31, AN8855_NUM_PORTS, 0x200) },
+	{ MT7530_MIB_RX_JABBER_ERR, REG_FIELD_ID(AN8855_PORT_MIB_RX_JABBER_ERR, 0, 31, AN8855_NUM_PORTS, 0x200) },
+	{ MT7530_MIB_RX_PAUSE, REG_FIELD_ID(AN8855_PORT_MIB_RX_PAUSE, 0, 31, AN8855_NUM_PORTS, 0x200) },
+	{ MT7530_MIB_RX_PKT_SZ_64, REG_FIELD_ID(AN8855_PORT_MIB_RX_PKT_SZ_64, 0, 31, AN8855_NUM_PORTS, 0x200) },
+	{ MT7530_MIB_RX_PKT_SZ_65_TO_127, REG_FIELD_ID(AN8855_PORT_MIB_RX_PKT_SZ_65_TO_127, 0, 31, AN8855_NUM_PORTS, 0x200) },
+	{ MT7530_MIB_RX_PKT_SZ_128_TO_255, REG_FIELD_ID(AN8855_PORT_MIB_RX_PKT_SZ_128_TO_255, 0, 31, AN8855_NUM_PORTS, 0x200) },
+	{ MT7530_MIB_RX_PKT_SZ_256_TO_511, REG_FIELD_ID(AN8855_PORT_MIB_RX_PKT_SZ_256_TO_511, 0, 31, AN8855_NUM_PORTS, 0x200) },
+	{ MT7530_MIB_RX_PKT_SZ_512_TO_1023, REG_FIELD_ID(AN8855_PORT_MIB_RX_PKT_SZ_512_TO_1023, 0, 31, AN8855_NUM_PORTS, 0x200) },
+	{ AN8855_MIB_RX_PKT_SZ_1024_TO_1518, REG_FIELD_ID(AN8855_PORT_MIB_RX_PKT_SZ_1024_TO_1518, 0, 31, AN8855_NUM_PORTS, 0x200) },
+	{ AN8855_MIB_RX_PKT_SZ_1519_TO_MAX, REG_FIELD_ID(AN8855_PORT_MIB_RX_PKT_SZ_1519_TO_MAX, 0, 31, AN8855_NUM_PORTS, 0x200) },
+	{ MT7530_MIB_RX_BYTES_LOW, REG_FIELD_ID(AN8855_PORT_MIB_RX_BYTES_LOW, 0, 31, AN8855_NUM_PORTS, 0x200) },
+	{ MT7530_MIB_RX_BYTES_HIGH, REG_FIELD_ID(AN8855_PORT_MIB_RX_BYTES_HIGH, 0, 31, AN8855_NUM_PORTS, 0x200) },
+	{ MT7530_MIB_RX_CTRL_DROP, REG_FIELD_ID(AN8855_PORT_MIB_RX_CTRL_DROP, 0, 31, AN8855_NUM_PORTS, 0x200) },
+	{ MT7530_MIB_RX_INGRESS_DROP, REG_FIELD_ID(AN8855_PORT_MIB_RX_INGRESS_DROP, 0, 31, AN8855_NUM_PORTS, 0x200) },
+	{ MT7530_MIB_RX_ARL_DROP, REG_FIELD_ID(AN8855_PORT_MIB_RX_ARL_DROP, 0, 31, AN8855_NUM_PORTS, 0x200) },
+	{ AN8855_MIB_FLOW_CONTROL_DROP, REG_FIELD_ID(AN8855_PORT_MIB_FLOW_CONTROL_DROP, 0, 31, AN8855_NUM_PORTS, 0x200) },
+	{ AN8855_MIB_WRED_DROP, REG_FIELD_ID(AN8855_PORT_MIB_WRED_DROP, 0, 31, AN8855_NUM_PORTS, 0x200) },
+	{ AN8855_MIB_MIRROR_DROP, REG_FIELD_ID(AN8855_PORT_MIB_MIRROR_DROP, 0, 31, AN8855_NUM_PORTS, 0x200) },
+	{ AN8855_MIB_RX_BAD_PKT_BYTES_LOW, REG_FIELD_ID(AN8855_PORT_MIB_RX_BAD_PKT_BYTES_LOW, 0, 31, AN8855_NUM_PORTS, 0x200) },
+	{ AN8855_MIB_RX_BAD_PKT_BYTES_HIGH, REG_FIELD_ID(AN8855_PORT_MIB_RX_BAD_PKT_BYTES_HIGH, 0, 31, AN8855_NUM_PORTS, 0x200) },
+	{ AN8855_MIB_RXS_FLOW_SAMPLING_PKT_DROP, REG_FIELD_ID(AN8855_PORT_MIB_RXS_FLOW_SAMPLING_PKT_DROP, 0, 31, AN8855_NUM_PORTS, 0x200) },
+	{ AN8855_MIB_RXS_FLOW_TOTAL_PKT_DROP, REG_FIELD_ID(AN8855_PORT_MIB_RXS_FLOW_TOTAL_PKT_DROP, 0, 31, AN8855_NUM_PORTS, 0x200) },
+	{ AN8855_MIB_PORT_CONTROL_DROP, REG_FIELD_ID(AN8855_PORT_MIB_PORT_CONTROL_DROP, 0, 31, AN8855_NUM_PORTS, 0x200) },
+};
+
+static const struct mt7530_mib_desc an8855_mib[] = {
+	MIB_DESC(MT7530_MIB_TX_DROP, -1, "TxDrop"),
+	MIB_DESC(MT7530_MIB_TX_CRC_ERR, -1, "TxCrcErr"),
+	MIB_DESC(MT7530_MIB_TX_COLLISION, -1, "TxCollision"),
+	MIB_DESC(AN8855_MIB_TX_OVERSIZE_DROP, -1, "TxOversizeDrop"),
+	MIB_DESC(AN8855_MIB_TX_BAD_PKT_BYTES_LOW,
+		 AN8855_MIB_TX_BAD_PKT_BYTES_HIGH, "TxBadPktBytes"),
+	MIB_DESC(MT7530_MIB_RX_DROP, -1, "RxDrop"),
+	MIB_DESC(MT7530_MIB_RX_FILTERING, -1, "RxFiltering"),
+	MIB_DESC(MT7530_MIB_RX_CRC_ERR, -1, "RxCrcErr"),
+	MIB_DESC(MT7530_MIB_RX_CTRL_DROP, -1, "RxCtrlDrop"),
+	MIB_DESC(MT7530_MIB_RX_INGRESS_DROP, -1, "RxIngressDrop"),
+	MIB_DESC(MT7530_MIB_RX_ARL_DROP, -1, "RxArlDrop"),
+	MIB_DESC(AN8855_MIB_FLOW_CONTROL_DROP, -1, "FlowControlDrop"),
+	MIB_DESC(AN8855_MIB_WRED_DROP, -1, "WredDrop"),
+	MIB_DESC(AN8855_MIB_MIRROR_DROP, -1, "MirrorDrop"),
+	MIB_DESC(AN8855_MIB_RX_BAD_PKT_BYTES_LOW,
+		 AN8855_MIB_RX_BAD_PKT_BYTES_HIGH, "RxBadPktBytes"),
+	MIB_DESC(AN8855_MIB_RXS_FLOW_SAMPLING_PKT_DROP, -1, "RxsFlowSamplingPktDrop"),
+	MIB_DESC(AN8855_MIB_RXS_FLOW_TOTAL_PKT_DROP, -1, "RxsFlowTotalPktDrop"),
+	MIB_DESC(AN8855_MIB_PORT_CONTROL_DROP, -1, "PortControlDrop"),
+};
+
+static void
+an8855_port_stp_state_set(struct dsa_switch *ds, int port, u8 state)
+{
+	struct dsa_port *dp = dsa_to_port(ds, port);
+	struct an8855_priv *priv = ds->priv;
+	bool learning = false;
+	int ret;
+
+	mt7530_lib_stp_state_set(&priv->lib_priv, port, state);
+
+	switch (state) {
+	case BR_STATE_LEARNING:
+	case BR_STATE_FORWARDING:
+		learning = dp->learning;
+		fallthrough;
+	default:
+		break;
+	}
+
+	ret = regmap_update_bits(priv->regmap, AN8855_PSC_P(port), AN8855_SA_DIS,
+				 learning ? 0 : AN8855_SA_DIS);
+	if (ret)
+		dev_err(priv->ds->dev, "failed to update learn reg: %d\n", ret);
+}
+
+static void an8855_port_fast_age(struct dsa_switch *ds, int port)
+{
+	struct an8855_priv *priv = ds->priv;
+	int ret;
+
+	mutex_lock(&priv->reg_mutex);
+
+	/* Set to clean Dynamic entry */
+	ret = regmap_write(priv->regmap, AN8855_ATA2, AN8855_ATA2_TYPE);
+	if (ret) {
+		dev_err(priv->ds->dev, "failed to update ATA2 reg: %d\n", ret);
+		goto exit;
+	}
+
+	/* Set Port */
+	ret = regmap_write(priv->regmap, AN8855_ATWD2,
+			   FIELD_PREP(AN8855_ATWD2_PORT, BIT(port)));
+	if (ret) {
+		dev_err(priv->ds->dev, "failed to update ATWD2 reg: %d\n", ret);
+		goto exit;
+	}
+
+	/* Flush Dynamic entry at port */
+	ret = mt7530_lib_fdb_cmd(&priv->lib_priv, MT7530_FDB_FLUSH,
+				 AN8855_FDB_MAT_MAC_TYPE_PORT, NULL);
+	if (ret)
+		dev_err(priv->ds->dev, "failed to send FDB cmd: %d\n", ret);
+
+exit:
+	mutex_unlock(&priv->reg_mutex);
+}
+
+static int an8855_port_pre_bridge_flags(struct dsa_switch *ds, int port,
+					struct switchdev_brport_flags flags,
+					struct netlink_ext_ack *extack)
+{
+	if (flags.mask & ~(BR_LEARNING | BR_FLOOD | BR_MCAST_FLOOD |
+			   BR_BCAST_FLOOD | BR_ISOLATED))
+		return -EINVAL;
+
+	return 0;
+}
+
+static int an8855_port_bridge_flags(struct dsa_switch *ds, int port,
+				    struct switchdev_brport_flags flags,
+				    struct netlink_ext_ack *extack)
+{
+	struct an8855_priv *priv = ds->priv;
+
+	return mt7530_lib_port_bridge_flags(&priv->lib_priv, port, flags,
+					    extack);
+}
+
+static int an8855_set_ageing_time(struct dsa_switch *ds, unsigned int msecs)
+{
+	struct an8855_priv *priv = ds->priv;
+	u32 age_count, age_unit, val;
+
+	/* Convert msec in AN8855_L2_AGING_MS_CONSTANT counter */
+	val = msecs / AN8855_L2_AGING_MS_CONSTANT;
+
+	/* Derive the count unit */
+	age_unit = DIV_ROUND_UP(val, FIELD_MAX(AN8855_AGE_CNT) + 1) - 1;
+	if (age_unit > FIELD_MAX(AN8855_AGE_UNIT))
+		age_unit = FIELD_MAX(AN8855_AGE_UNIT);
+
+	/* Get the count in unit, age_unit is always incremented by 1 internally */
+	age_count = DIV_ROUND_UP(val, age_unit + 1) - 1;
+
+	return regmap_update_bits(priv->regmap, AN8855_AAC,
+				  AN8855_AGE_CNT | AN8855_AGE_UNIT,
+				  FIELD_PREP(AN8855_AGE_CNT, age_count) |
+				  FIELD_PREP(AN8855_AGE_UNIT, age_unit));
+}
+
+static int an8855_port_bridge_join(struct dsa_switch *ds, int port,
+				   struct dsa_bridge bridge,
+				   bool *tx_fwd_offload,
+				   struct netlink_ext_ack *extack)
+{
+	struct an8855_priv *priv = ds->priv;
+
+	return mt7530_lib_port_bridge_join(&priv->lib_priv, port, bridge,
+					   tx_fwd_offload, extack);
+}
+
+static void an8855_port_bridge_leave(struct dsa_switch *ds, int port,
+				     struct dsa_bridge bridge)
+{
+	struct an8855_priv *priv = ds->priv;
+
+	return mt7530_lib_port_bridge_leave(&priv->lib_priv, port, bridge);
+}
+
+static int an8855_port_fdb_add(struct dsa_switch *ds, int port,
+			       const unsigned char *addr, u16 vid,
+			       struct dsa_db db)
+{
+	struct an8855_priv *priv = ds->priv;
+
+	return mt7530_lib_port_fdb_add(&priv->lib_priv, port, addr, vid, db);
+}
+
+static int an8855_port_fdb_del(struct dsa_switch *ds, int port,
+			       const unsigned char *addr, u16 vid,
+			       struct dsa_db db)
+{
+	struct an8855_priv *priv = ds->priv;
+
+	return mt7530_lib_port_fdb_del(&priv->lib_priv, port, addr, vid, db);
+}
+
+static int an8855_port_fdb_dump(struct dsa_switch *ds, int port,
+				dsa_fdb_dump_cb_t *cb, void *data)
+{
+	struct an8855_priv *priv = ds->priv;
+	int banks, count = 0;
+	u32 rsp;
+	int ret;
+	int i;
+
+	mutex_lock(&priv->reg_mutex);
+
+	/* Load search port */
+	ret = regmap_write(priv->regmap, AN8855_ATWD2,
+			   FIELD_PREP(AN8855_ATWD2_PORT, BIT(port)));
+	if (ret)
+		goto exit;
+	ret = mt7530_lib_fdb_cmd(&priv->lib_priv, MT7530_FDB_START,
+				 AN8855_FDB_MAT_MAC_PORT, &rsp);
+	if (ret < 0)
+		goto exit;
+
+	do {
+		/* From response get the number of banks to read, exit if 0 */
+		banks = FIELD_GET(AN8855_ATC_HIT, rsp);
+		if (!banks)
+			break;
+
+		/* Each banks have 4 entry */
+		for (i = 0; i < 4; i++) {
+			struct mt7530_fdb _fdb = {  };
+
+			count++;
+
+			/* Check if bank is present */
+			if (!(banks & BIT(i)))
+				continue;
+
+			/* Select bank entry index */
+			ret = regmap_write(priv->regmap, AN8855_ATRDS,
+					   FIELD_PREP(AN8855_ATRD_SEL, i));
+			if (ret)
+				break;
+			/* wait 1ms for the bank entry to be filled */
+			usleep_range(1000, 1500);
+			mt7530_lib_fdb_read(&priv->lib_priv, &_fdb);
+
+			ret = cb(_fdb.mac, _fdb.vid, _fdb.noarp, data);
+			if (ret < 0)
+				break;
+		}
+
+		/* Stop if reached max FDB number */
+		if (ret < 0 || count >= AN8855_NUM_FDB_RECORDS)
+			break;
+
+		/* Read next bank */
+		ret = mt7530_lib_fdb_cmd(&priv->lib_priv, MT7530_FDB_NEXT,
+					 AN8855_FDB_MAT_MAC_PORT, &rsp);
+		if (ret < 0)
+			break;
+	} while (true);
+
+exit:
+	mutex_unlock(&priv->reg_mutex);
+	return ret;
+}
+
+static int an8855_port_vlan_filtering(struct dsa_switch *ds, int port,
+				      bool vlan_filtering,
+				      struct netlink_ext_ack *extack)
+{
+	struct an8855_priv *priv = ds->priv;
+
+	return mt7530_lib_port_vlan_filtering(&priv->lib_priv, port,
+					      vlan_filtering,
+					      extack);
+}
+
+static int an8855_port_vlan_add(struct dsa_switch *ds, int port,
+				const struct switchdev_obj_port_vlan *vlan,
+				struct netlink_ext_ack *extack)
+{
+	struct an8855_priv *priv = ds->priv;
+
+	return mt7530_lib_port_vlan_add(&priv->lib_priv, port, vlan, extack);
+}
+
+static int an8855_port_vlan_del(struct dsa_switch *ds, int port,
+				const struct switchdev_obj_port_vlan *vlan)
+{
+	struct an8855_priv *priv = ds->priv;
+
+	return mt7530_lib_port_vlan_del(&priv->lib_priv, port, vlan);
+}
+
+static int an8855_port_mdb_add(struct dsa_switch *ds, int port,
+			       const struct switchdev_obj_port_mdb *mdb,
+			       struct dsa_db db)
+{
+	struct an8855_priv *priv = ds->priv;
+
+	return mt7530_lib_port_mdb_add(&priv->lib_priv, port, mdb, db);
+}
+
+static int an8855_port_mdb_del(struct dsa_switch *ds, int port,
+			       const struct switchdev_obj_port_mdb *mdb,
+			       struct dsa_db db)
+{
+	struct an8855_priv *priv = ds->priv;
+
+	return mt7530_lib_port_mdb_del(&priv->lib_priv, port, mdb, db);
+}
+
+static int an8855_port_change_mtu(struct dsa_switch *ds, int port,
+				  int new_mtu)
+{
+	struct an8855_priv *priv = ds->priv;
+
+	return mt7530_lib_port_change_mtu(&priv->lib_priv, port, new_mtu);
+}
+
+static int an8855_port_max_mtu(struct dsa_switch *ds, int port)
+{
+	return AN8855_MAX_MTU;
+}
+
+static void an8855_get_strings(struct dsa_switch *ds, int port,
+			       u32 stringset, uint8_t *data)
+{
+	int i;
+
+	if (stringset != ETH_SS_STATS)
+		return;
+
+	for (i = 0; i < ARRAY_SIZE(an8855_mib); i++)
+		ethtool_puts(&data, an8855_mib[i].name);
+}
+
+static void an8855_get_ethtool_stats(struct dsa_switch *ds, int port,
+				     uint64_t *data)
+{
+	struct an8855_priv *priv = ds->priv;
+	const struct mt7530_mib_desc *mib;
+	struct mt7530_lib_priv *lib_priv;
+	int i;
+
+	lib_priv = &priv->lib_priv;
+	for (i = 0; i < ARRAY_SIZE(an8855_mib); i++) {
+		struct regmap_field *high = NULL;
+
+		mib = &an8855_mib[i];
+		if (mib->field_high != -1)
+			high = lib_priv->fields[mib->field_high];
+
+		mt7530_lib_read_port_stats(lib_priv->fields[mib->field_low],
+					   high, port, data + i);
+	}
+}
+
+static int an8855_get_sset_count(struct dsa_switch *ds, int port,
+				 int sset)
+{
+	if (sset != ETH_SS_STATS)
+		return -EOPNOTSUPP;
+
+	return ARRAY_SIZE(an8855_mib);
+}
+
+static void an8855_get_eth_mac_stats(struct dsa_switch *ds, int port,
+				     struct ethtool_eth_mac_stats *mac_stats)
+{
+	struct an8855_priv *priv = ds->priv;
+
+	return mt7530_lib_get_eth_mac_stats(&priv->lib_priv, port, mac_stats);
+}
+
+static const struct ethtool_rmon_hist_range an8855_rmon_ranges[] = {
+	{ 0, 64 },
+	{ 65, 127 },
+	{ 128, 255 },
+	{ 256, 511 },
+	{ 512, 1023 },
+	{ 1024, 1518 },
+	{ 1519, AN8855_MAX_MTU },
+	{}
+};
+
+static const struct mt7530_rmon_hist an8855_rmon_hist_info = {
+	.ranges_fields = (unsigned int []){
+		MT7530_MIB_RX_PKT_SZ_64,
+		MT7530_MIB_RX_PKT_SZ_65_TO_127,
+		MT7530_MIB_RX_PKT_SZ_128_TO_255,
+		MT7530_MIB_RX_PKT_SZ_256_TO_511,
+		MT7530_MIB_RX_PKT_SZ_512_TO_1023,
+		AN8855_MIB_RX_PKT_SZ_1024_TO_1518,
+		AN8855_MIB_RX_PKT_SZ_1519_TO_MAX,
+	},
+	.ranges_tx_fields = (unsigned int []){
+		MT7530_MIB_TX_PKT_SZ_64,
+		MT7530_MIB_TX_PKT_SZ_65_TO_127,
+		MT7530_MIB_TX_PKT_SZ_128_TO_255,
+		MT7530_MIB_TX_PKT_SZ_256_TO_511,
+		MT7530_MIB_TX_PKT_SZ_512_TO_1023,
+		AN8855_MIB_TX_PKT_SZ_1024_TO_1518,
+		AN8855_MIB_TX_PKT_SZ_1519_TO_MAX,
+	},
+	.ranges = an8855_rmon_ranges,
+	.num_ranges = ARRAY_SIZE(an8855_rmon_ranges) - 1,
+};
+
+static void an8855_get_rmon_stats(struct dsa_switch *ds, int port,
+				  struct ethtool_rmon_stats *rmon_stats,
+				  const struct ethtool_rmon_hist_range **ranges)
+{
+	struct an8855_priv *priv = ds->priv;
+
+	return mt7530_lib_get_rmon_stats(&priv->lib_priv, port, rmon_stats, ranges,
+					 &an8855_rmon_hist_info);
+}
+
+static void an8855_get_eth_ctrl_stats(struct dsa_switch *ds, int port,
+				      struct ethtool_eth_ctrl_stats *ctrl_stats)
+{
+	struct an8855_priv *priv = ds->priv;
+
+	mt7530_lib_get_eth_ctrl_stats(&priv->lib_priv, port, ctrl_stats);
+}
+
+static int an8855_port_mirror_add(struct dsa_switch *ds, int port,
+				  struct dsa_mall_mirror_tc_entry *mirror,
+				  bool ingress,
+				  struct netlink_ext_ack *extack)
+{
+	struct an8855_priv *priv = ds->priv;
+
+	return mt7530_lib_port_mirror_add(&priv->lib_priv, port, mirror, ingress, extack);
+}
+
+static void an8855_port_mirror_del(struct dsa_switch *ds, int port,
+				   struct dsa_mall_mirror_tc_entry *mirror)
+{
+	struct an8855_priv *priv = ds->priv;
+
+	mt7530_lib_port_mirror_del(&priv->lib_priv, port, mirror);
+}
+
+static int an8855_port_enable(struct dsa_switch *ds, int port,
+			      struct phy_device *phy)
+{
+	struct an8855_priv *priv = ds->priv;
+	int ret;
+
+	mutex_lock(&priv->reg_mutex);
+	priv->ports[port].enable = true;
+	ret = regmap_set_bits(priv->regmap, AN8855_PMCR_P(port),
+			      AN8855_PMCR_TX_EN | AN8855_PMCR_RX_EN);
+	mutex_unlock(&priv->reg_mutex);
+
+	return ret;
+}
+
+static void an8855_port_disable(struct dsa_switch *ds, int port)
+{
+	struct an8855_priv *priv = ds->priv;
+	int ret;
+
+	mutex_lock(&priv->reg_mutex);
+	priv->ports[port].enable = false;
+	ret = regmap_clear_bits(priv->regmap, AN8855_PMCR_P(port),
+				AN8855_PMCR_TX_EN | AN8855_PMCR_RX_EN);
+	mutex_unlock(&priv->reg_mutex);
+	if (ret)
+		dev_err(priv->ds->dev, "failed to disable port: %d\n", ret);
+}
+
+static int an8855_set_mac_eee(struct dsa_switch *ds, int port,
+			      struct ethtool_keee *e)
+{
+	if (e->tx_lpi_timer > 0xFFF)
+		return -EINVAL;
+
+	return 0;
+}
+
+static enum dsa_tag_protocol an8855_get_tag_protocol(struct dsa_switch *ds,
+						     int port,
+						     enum dsa_tag_protocol mp)
+{
+	return DSA_TAG_PROTO_AIROHA;
+}
+
+static int an8855_setup(struct dsa_switch *ds)
+{
+	struct an8855_priv *priv = ds->priv;
+	struct dsa_port *dp;
+	int ret;
+
+	/* Enable and reset MIB counters */
+	mt7530_lib_mib_reset(&priv->lib_priv);
+
+	dsa_switch_for_each_user_port(dp, ds) {
+		/* Disable MAC by default on all user ports */
+		an8855_port_disable(ds, dp->index);
+
+		/* Individual user ports get connected to CPU port only */
+		ret = regmap_write(priv->regmap, AN8855_PORTMATRIX_P(dp->index),
+				   FIELD_PREP(AN8855_PORTMATRIX_MASK, BIT(AN8855_CPU_PORT)));
+		if (ret)
+			return ret;
+
+		/* Disable Broadcast Forward on user ports */
+		ret = regmap_clear_bits(priv->regmap, AN8855_BCF, BIT(dp->index));
+		if (ret)
+			return ret;
+
+		/* Disable Unknown Unicast Forward on user ports */
+		ret = regmap_clear_bits(priv->regmap, AN8855_UNUF, BIT(dp->index));
+		if (ret)
+			return ret;
+
+		/* Disable Unknown Multicast Forward on user ports */
+		ret = regmap_clear_bits(priv->regmap, AN8855_UNMF, BIT(dp->index));
+		if (ret)
+			return ret;
+
+		ret = regmap_clear_bits(priv->regmap, AN8855_UNIPMF, BIT(dp->index));
+		if (ret)
+			return ret;
+
+		/* Set default PVID to on all user ports */
+		mt7530_port_set_pvid(&priv->lib_priv, dp->index, AN8855_PORT_VID_DEFAULT);
+	}
+
+	/* Enable Airoha header mode on the cpu port */
+	ret = regmap_write(priv->regmap, AN8855_PVC_P(AN8855_CPU_PORT),
+			   AN8855_PORT_SPEC_REPLACE_MODE | AN8855_PORT_SPEC_TAG);
+	if (ret)
+		return ret;
+
+	/* Unknown multicast frame forwarding to the cpu port */
+	ret = regmap_write(priv->regmap, AN8855_UNMF, BIT(AN8855_CPU_PORT));
+	if (ret)
+		return ret;
+
+	/* Set CPU port number */
+	ret = regmap_update_bits(priv->regmap, AN8855_MFC,
+				 AN8855_CPU_EN | AN8855_CPU_PORT_IDX,
+				 AN8855_CPU_EN |
+				 FIELD_PREP(AN8855_CPU_PORT_IDX, AN8855_CPU_PORT));
+	if (ret)
+		return ret;
+
+	/* CPU port gets connected to all user ports of
+	 * the switch.
+	 */
+	ret = regmap_write(priv->regmap, AN8855_PORTMATRIX_P(AN8855_CPU_PORT),
+			   FIELD_PREP(AN8855_PORTMATRIX_MASK, dsa_user_ports(ds)));
+	if (ret)
+		return ret;
+
+	/* CPU port is set to fallback mode to let untagged
+	 * frames pass through.
+	 */
+	ret = regmap_update_bits(priv->regmap, AN8855_PCR_P(AN8855_CPU_PORT),
+				 AN8855_PORT_VLAN,
+				 FIELD_PREP(AN8855_PORT_VLAN, AN8855_PORT_FALLBACK_MODE));
+	if (ret)
+		return ret;
+
+	/* Enable Broadcast Forward on CPU port */
+	ret = regmap_set_bits(priv->regmap, AN8855_BCF, BIT(AN8855_CPU_PORT));
+	if (ret)
+		return ret;
+
+	/* Enable Unknown Unicast Forward on CPU port */
+	ret = regmap_set_bits(priv->regmap, AN8855_UNUF, BIT(AN8855_CPU_PORT));
+	if (ret)
+		return ret;
+
+	/* Enable Unknown Multicast Forward on CPU port */
+	ret = regmap_set_bits(priv->regmap, AN8855_UNMF, BIT(AN8855_CPU_PORT));
+	if (ret)
+		return ret;
+
+	ret = regmap_set_bits(priv->regmap, AN8855_UNIPMF, BIT(AN8855_CPU_PORT));
+	if (ret)
+		return ret;
+
+	/* Setup Trap special frame to CPU rules */
+	mt7530_lib_trap_frames(&priv->lib_priv);
+
+	dsa_switch_for_each_port(dp, ds) {
+		/* Disable Learning on all ports.
+		 * Learning on CPU is disabled for fdb isolation and handled by
+		 * assisted_learning_on_cpu_port.
+		 */
+		ret = regmap_set_bits(priv->regmap, AN8855_PSC_P(dp->index),
+				      AN8855_SA_DIS);
+		if (ret)
+			return ret;
+
+		/* Enable consistent egress tag (for VLAN unware VLAN-passthrough) */
+		ret = regmap_update_bits(priv->regmap, AN8855_PVC_P(dp->index),
+					 AN8855_PVC_EG_TAG,
+					 FIELD_PREP(AN8855_PVC_EG_TAG, AN8855_VLAN_EG_CONSISTENT));
+		if (ret)
+			return ret;
+	}
+
+	/* Setup VLAN for Default PVID */
+	ret = mt7530_lib_setup_vlan0(&priv->lib_priv);
+	if (ret)
+		return ret;
+
+	ret = regmap_clear_bits(priv->regmap, AN8855_CKGCR,
+				AN8855_CKG_LNKDN_GLB_STOP | AN8855_CKG_LNKDN_PORT_STOP);
+	if (ret)
+		return ret;
+
+	/* Flush the FDB table */
+	ret = mt7530_lib_fdb_cmd(&priv->lib_priv, MT7530_FDB_FLUSH,
+				 AN8855_FDB_MAT_ALL, NULL);
+	if (ret < 0)
+		return ret;
+
+	/* Set min a max ageing value supported */
+	ds->ageing_time_min = AN8855_L2_AGING_MS_CONSTANT;
+	ds->ageing_time_max = FIELD_MAX(AN8855_AGE_CNT) *
+			      FIELD_MAX(AN8855_AGE_UNIT) *
+			      AN8855_L2_AGING_MS_CONSTANT;
+
+	/* User reported problem with WiFi roaming and
+	 * ethernet port. Enabling assisted learning fix
+	 * the issue.
+	 */
+	ds->assisted_learning_on_cpu_port = true;
+
+	return 0;
+}
+
+static struct phylink_pcs *an8855_phylink_mac_select_pcs(struct phylink_config *config,
+							 phy_interface_t interface)
+{
+	struct dsa_port *dp = dsa_phylink_to_port(config);
+	struct an8855_priv *priv = dp->ds->priv;
+
+	switch (interface) {
+	case PHY_INTERFACE_MODE_SGMII:
+	case PHY_INTERFACE_MODE_2500BASEX:
+		return &priv->pcs;
+	default:
+		return NULL;
+	}
+}
+
+static void an8855_phylink_mac_config(struct phylink_config *config,
+				      unsigned int mode,
+				      const struct phylink_link_state *state)
+{
+	struct dsa_port *dp = dsa_phylink_to_port(config);
+	struct dsa_switch *ds = dp->ds;
+	struct an8855_priv *priv;
+	int port = dp->index;
+
+	priv = ds->priv;
+
+	/* Nothing to configure for internal ports */
+	if (port != 5)
+		return;
+
+	mutex_lock(&priv->reg_mutex);
+	regmap_update_bits(priv->regmap, AN8855_PMCR_P(port),
+			   AN8855_PMCR_IFG_XMIT | AN8855_PMCR_MAC_MODE |
+			   AN8855_PMCR_BACKOFF_EN | AN8855_PMCR_BACKPR_EN,
+			   FIELD_PREP(AN8855_PMCR_IFG_XMIT, 0x1) |
+			   AN8855_PMCR_MAC_MODE | AN8855_PMCR_BACKOFF_EN |
+			   AN8855_PMCR_BACKPR_EN);
+	mutex_unlock(&priv->reg_mutex);
+}
+
+static void an8855_phylink_get_caps(struct dsa_switch *ds, int port,
+				    struct phylink_config *config)
+{
+	struct an8855_priv *priv = ds->priv;
+	u32 reg = 0;
+	int ret;
+
+	switch (port) {
+	case 0:
+	case 1:
+	case 2:
+	case 3:
+	case 4:
+		__set_bit(PHY_INTERFACE_MODE_GMII,
+			  config->supported_interfaces);
+		__set_bit(PHY_INTERFACE_MODE_INTERNAL,
+			  config->supported_interfaces);
+		break;
+	case 5:
+		phy_interface_set_rgmii(config->supported_interfaces);
+		__set_bit(PHY_INTERFACE_MODE_SGMII,
+			  config->supported_interfaces);
+		__set_bit(PHY_INTERFACE_MODE_2500BASEX,
+			  config->supported_interfaces);
+		break;
+	}
+
+	config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE |
+				   MAC_10 | MAC_100 | MAC_1000FD | MAC_2500FD;
+
+	ret = regmap_read(priv->regmap, AN8855_CKGCR, &reg);
+	if (ret)
+		dev_err(ds->dev, "failed to read EEE LPI timer\n");
+
+	memcpy(config->lpi_interfaces, config->supported_interfaces,
+	       sizeof(config->lpi_interfaces));
+	config->lpi_capabilities = MAC_100FD | MAC_1000FD;
+	/* Global LPI TXIDLE Threshold, default 60ms (unit 2us) */
+	config->lpi_timer_default = FIELD_GET(AN8855_LPI_TXIDLE_THD_MASK, reg) *
+				    AN8855_TX_LPI_UNIT;
+
+	config->eee_enabled_default = true;
+}
+
+static void an8855_phylink_mac_link_down(struct phylink_config *config,
+					 unsigned int mode,
+					 phy_interface_t interface)
+{
+	struct dsa_port *dp = dsa_phylink_to_port(config);
+	struct an8855_priv *priv = dp->ds->priv;
+
+	mutex_lock(&priv->reg_mutex);
+
+	/* With autoneg just disable TX/RX else also force link down */
+	if (phylink_autoneg_inband(mode)) {
+		regmap_clear_bits(priv->regmap, AN8855_PMCR_P(dp->index),
+				  AN8855_PMCR_TX_EN | AN8855_PMCR_RX_EN);
+	} else {
+		regmap_update_bits(priv->regmap, AN8855_PMCR_P(dp->index),
+				   AN8855_PMCR_TX_EN | AN8855_PMCR_RX_EN |
+				   AN8855_PMCR_FORCE_MODE | AN8855_PMCR_FORCE_LNK,
+				   AN8855_PMCR_FORCE_MODE);
+	}
+
+	mutex_unlock(&priv->reg_mutex);
+}
+
+static void an8855_phylink_mac_link_up(struct phylink_config *config,
+				       struct phy_device *phydev, unsigned int mode,
+				       phy_interface_t interface, int speed,
+				       int duplex, bool tx_pause, bool rx_pause)
+{
+	struct dsa_port *dp = dsa_phylink_to_port(config);
+	struct an8855_priv *priv = dp->ds->priv;
+	int port = dp->index;
+	u32 reg = 0;
+
+	mutex_lock(&priv->reg_mutex);
+
+	regmap_read(priv->regmap, AN8855_PMCR_P(port), &reg);
+	if (phylink_autoneg_inband(mode)) {
+		reg &= ~AN8855_PMCR_FORCE_MODE;
+	} else {
+		reg |= AN8855_PMCR_FORCE_MODE | AN8855_PMCR_FORCE_LNK;
+
+		reg &= ~AN8855_PMCR_FORCE_SPEED;
+		switch (speed) {
+		case SPEED_10:
+			reg |= AN8855_PMCR_FORCE_SPEED_10;
+			break;
+		case SPEED_100:
+			reg |= AN8855_PMCR_FORCE_SPEED_100;
+			break;
+		case SPEED_1000:
+			reg |= AN8855_PMCR_FORCE_SPEED_1000;
+			break;
+		case SPEED_2500:
+			reg |= AN8855_PMCR_FORCE_SPEED_2500;
+			break;
+		case SPEED_5000:
+			dev_err(priv->ds->dev, "Missing support for 5G speed. Aborting...\n");
+			goto exit;
+		}
+
+		reg &= ~AN8855_PMCR_FORCE_FDX;
+		if (duplex == DUPLEX_FULL)
+			reg |= AN8855_PMCR_FORCE_FDX;
+
+		reg &= ~AN8855_PMCR_RX_FC_EN;
+		if (rx_pause || dsa_port_is_cpu(dp))
+			reg |= AN8855_PMCR_RX_FC_EN;
+
+		reg &= ~AN8855_PMCR_TX_FC_EN;
+		if (tx_pause || dsa_port_is_cpu(dp))
+			reg |= AN8855_PMCR_TX_FC_EN;
+	}
+
+	reg |= AN8855_PMCR_TX_EN | AN8855_PMCR_RX_EN;
+
+	regmap_write(priv->regmap, AN8855_PMCR_P(port), reg);
+
+exit:
+	mutex_unlock(&priv->reg_mutex);
+}
+
+static void an8855_phylink_mac_disable_tx_lpi(struct phylink_config *config)
+{
+	struct dsa_port *dp = dsa_phylink_to_port(config);
+	struct an8855_priv *priv = dp->ds->priv;
+	int port = dp->index;
+	int ret;
+
+	mutex_lock(&priv->reg_mutex);
+	ret = regmap_clear_bits(priv->regmap, AN8855_PMCR_P(port),
+				AN8855_PMCR_FORCE_EEE1G |
+				AN8855_PMCR_FORCE_EEE100);
+	mutex_unlock(&priv->reg_mutex);
+	if (ret)
+		dev_err(dp->ds->dev, "failed to disable EEE for port %d\n",
+			port);
+
+	ret = regmap_clear_bits(priv->regmap, AN8855_PMEEECR_P(port),
+				AN8855_LPI_MODE_EN);
+	if (ret)
+		dev_err(dp->ds->dev, "failed to disable LPI for port %d\n",
+			port);
+}
+
+static int an8855_phylink_mac_enable_tx_lpi(struct phylink_config *config,
+					    u32 timer, bool tx_clock_stop)
+{
+	struct an8855_priv *priv;
+	struct dsa_switch *ds;
+	struct dsa_port *dp;
+	int port;
+	u32 val;
+	int ret;
+
+	dp = dsa_phylink_to_port(config);
+	port = dp->index;
+	ds = dp->ds;
+	priv = ds->priv;
+
+	/* TX LPI timer is global, find the highest timer
+	 * across all port.
+	 * If requested timer is 0, set to enter LPI immediately
+	 * for the single port.
+	 */
+	if (timer) {
+		int i;
+
+		/* Save requested timer and search the highest one */
+		mutex_lock(&priv->reg_mutex);
+		priv->tx_lpi_timer_ports[dp->index] = timer;
+		for (i = 0; i < AN8855_NUM_PORTS; i++) {
+			if (!priv->ports[i].enable)
+				continue;
+
+			if (i == dp->index)
+				continue;
+
+			if (timer < priv->tx_lpi_timer_ports[i])
+				timer = priv->tx_lpi_timer_ports[i];
+		}
+
+		timer /= AN8855_TX_LPI_UNIT;
+		if (FIELD_FIT(AN8855_LPI_TXIDLE_THD_MASK, timer))
+			val = FIELD_PREP(AN8855_LPI_TXIDLE_THD_MASK, timer);
+		else
+			val = AN8855_LPI_TXIDLE_THD_MASK;
+
+		ret = regmap_update_bits(priv->regmap, AN8855_CKGCR,
+					 AN8855_LPI_TXIDLE_THD_MASK, val);
+		mutex_unlock(&priv->reg_mutex);
+		if (ret) {
+			dev_err(dp->ds->dev, "failed to set global LPI timer\n");
+			return ret;
+		}
+	} else {
+		ret = regmap_set_bits(priv->regmap, AN8855_PMEEECR_P(port),
+				      AN8855_LPI_MODE_EN);
+		if (ret) {
+			dev_err(dp->ds->dev, "failed to enable LPI for port %d\n",
+				port);
+			return ret;
+		}
+	}
+
+	mutex_lock(&priv->reg_mutex);
+	ret = regmap_set_bits(priv->regmap, AN8855_PMCR_P(port),
+			      AN8855_PMCR_FORCE_EEE1G |
+			      AN8855_PMCR_FORCE_EEE100);
+	mutex_unlock(&priv->reg_mutex);
+	if (ret)
+		dev_err(dp->ds->dev, "failed to enable EEE for port %d\n",
+			port);
+
+	return ret;
+}
+
+static unsigned int an8855_pcs_inband_caps(struct phylink_pcs *pcs,
+					   phy_interface_t interface)
+{
+	/* SGMII can be configured to use inband with AN result */
+	if (interface == PHY_INTERFACE_MODE_SGMII)
+		return LINK_INBAND_DISABLE | LINK_INBAND_ENABLE;
+
+	/* inband is not supported in 2500-baseX and must be disabled */
+	return LINK_INBAND_DISABLE;
+}
+
+static void an8855_pcs_get_state(struct phylink_pcs *pcs, unsigned int neg_mode,
+				 struct phylink_link_state *state)
+{
+	struct an8855_priv *priv = container_of(pcs, struct an8855_priv, pcs);
+	u32 val;
+	int ret;
+
+	ret = regmap_read(priv->regmap, AN8855_PMSR_P(AN8855_CPU_PORT), &val);
+	if (ret < 0) {
+		state->link = false;
+		return;
+	}
+
+	state->link = !!(val & AN8855_PMSR_LNK);
+	state->an_complete = state->link;
+	state->duplex = (val & AN8855_PMSR_DPX) ? DUPLEX_FULL :
+						  DUPLEX_HALF;
+
+	switch (val & AN8855_PMSR_SPEED) {
+	case AN8855_PMSR_SPEED_10:
+		state->speed = SPEED_10;
+		break;
+	case AN8855_PMSR_SPEED_100:
+		state->speed = SPEED_100;
+		break;
+	case AN8855_PMSR_SPEED_1000:
+		state->speed = SPEED_1000;
+		break;
+	case AN8855_PMSR_SPEED_2500:
+		state->speed = SPEED_2500;
+		break;
+	case AN8855_PMSR_SPEED_5000:
+		dev_err(priv->ds->dev, "Switch doesn't support 5G speed. Setting Unknown.\n");
+		fallthrough;
+	default:
+		state->speed = SPEED_UNKNOWN;
+		break;
+	}
+
+	if (val & AN8855_PMSR_RX_FC)
+		state->pause |= MLO_PAUSE_RX;
+	if (val & AN8855_PMSR_TX_FC)
+		state->pause |= MLO_PAUSE_TX;
+}
+
+static int an8855_pcs_config(struct phylink_pcs *pcs, unsigned int neg_mode,
+			     phy_interface_t interface,
+			     const unsigned long *advertising,
+			     bool permit_pause_to_mac)
+{
+	struct an8855_priv *priv = container_of(pcs, struct an8855_priv, pcs);
+	u32 val;
+	int ret;
+
+	/* TX FIR - improve TX EYE */
+	ret = regmap_update_bits(priv->regmap, AN8855_INTF_CTRL_10,
+				 AN8855_RG_DA_QP_TX_FIR_C2_SEL |
+				 AN8855_RG_DA_QP_TX_FIR_C2_FORCE |
+				 AN8855_RG_DA_QP_TX_FIR_C1_SEL |
+				 AN8855_RG_DA_QP_TX_FIR_C1_FORCE,
+				 AN8855_RG_DA_QP_TX_FIR_C2_SEL |
+				 FIELD_PREP(AN8855_RG_DA_QP_TX_FIR_C2_FORCE, 0x4) |
+				 AN8855_RG_DA_QP_TX_FIR_C1_SEL |
+				 FIELD_PREP(AN8855_RG_DA_QP_TX_FIR_C1_FORCE, 0x0));
+	if (ret)
+		return ret;
+
+	if (interface == PHY_INTERFACE_MODE_2500BASEX)
+		val = 0x0;
+	else
+		val = 0xd;
+	ret = regmap_update_bits(priv->regmap, AN8855_INTF_CTRL_11,
+				 AN8855_RG_DA_QP_TX_FIR_C0B_SEL |
+				 AN8855_RG_DA_QP_TX_FIR_C0B_FORCE,
+				 AN8855_RG_DA_QP_TX_FIR_C0B_SEL |
+				 FIELD_PREP(AN8855_RG_DA_QP_TX_FIR_C0B_FORCE, val));
+	if (ret)
+		return ret;
+
+	/* RX CDR - improve RX Jitter Tolerance */
+	if (interface == PHY_INTERFACE_MODE_2500BASEX)
+		val = 0x5;
+	else
+		val = 0x6;
+	ret = regmap_update_bits(priv->regmap, AN8855_RG_QP_CDR_LPF_BOT_LIM,
+				 AN8855_RG_QP_CDR_LPF_KP_GAIN |
+				 AN8855_RG_QP_CDR_LPF_KI_GAIN,
+				 FIELD_PREP(AN8855_RG_QP_CDR_LPF_KP_GAIN, val) |
+				 FIELD_PREP(AN8855_RG_QP_CDR_LPF_KI_GAIN, val));
+	if (ret)
+		return ret;
+
+	/* PLL */
+	if (interface == PHY_INTERFACE_MODE_2500BASEX)
+		val = 0x1;
+	else
+		val = 0x0;
+	ret = regmap_update_bits(priv->regmap, AN8855_QP_DIG_MODE_CTRL_1,
+				 AN8855_RG_TPHY_SPEED,
+				 FIELD_PREP(AN8855_RG_TPHY_SPEED, val));
+	if (ret)
+		return ret;
+
+	/* PLL - LPF */
+	ret = regmap_update_bits(priv->regmap, AN8855_PLL_CTRL_2,
+				 AN8855_RG_DA_QP_PLL_RICO_SEL_INTF |
+				 AN8855_RG_DA_QP_PLL_FBKSEL_INTF |
+				 AN8855_RG_DA_QP_PLL_BR_INTF |
+				 AN8855_RG_DA_QP_PLL_BPD_INTF |
+				 AN8855_RG_DA_QP_PLL_BPA_INTF |
+				 AN8855_RG_DA_QP_PLL_BC_INTF,
+				 AN8855_RG_DA_QP_PLL_RICO_SEL_INTF |
+				 FIELD_PREP(AN8855_RG_DA_QP_PLL_FBKSEL_INTF, 0x0) |
+				 FIELD_PREP(AN8855_RG_DA_QP_PLL_BR_INTF, 0x3) |
+				 FIELD_PREP(AN8855_RG_DA_QP_PLL_BPD_INTF, 0x0) |
+				 FIELD_PREP(AN8855_RG_DA_QP_PLL_BPA_INTF, 0x5) |
+				 FIELD_PREP(AN8855_RG_DA_QP_PLL_BC_INTF, 0x1));
+	if (ret)
+		return ret;
+
+	/* PLL - ICO */
+	ret = regmap_set_bits(priv->regmap, AN8855_PLL_CTRL_4,
+			      AN8855_RG_DA_QP_PLL_ICOLP_EN_INTF);
+	if (ret)
+		return ret;
+	ret = regmap_clear_bits(priv->regmap, AN8855_PLL_CTRL_2,
+				AN8855_RG_DA_QP_PLL_ICOIQ_EN_INTF);
+	if (ret)
+		return ret;
+
+	/* PLL - CHP */
+	if (interface == PHY_INTERFACE_MODE_2500BASEX)
+		val = 0x6;
+	else
+		val = 0x4;
+	ret = regmap_update_bits(priv->regmap, AN8855_PLL_CTRL_2,
+				 AN8855_RG_DA_QP_PLL_IR_INTF,
+				 FIELD_PREP(AN8855_RG_DA_QP_PLL_IR_INTF, val));
+	if (ret)
+		return ret;
+
+	/* PLL - PFD */
+	ret = regmap_update_bits(priv->regmap, AN8855_PLL_CTRL_2,
+				 AN8855_RG_DA_QP_PLL_PFD_OFFSET_EN_INTRF |
+				 AN8855_RG_DA_QP_PLL_PFD_OFFSET_INTF |
+				 AN8855_RG_DA_QP_PLL_KBAND_PREDIV_INTF,
+				 FIELD_PREP(AN8855_RG_DA_QP_PLL_PFD_OFFSET_INTF, 0x1) |
+				 FIELD_PREP(AN8855_RG_DA_QP_PLL_KBAND_PREDIV_INTF, 0x1));
+	if (ret)
+		return ret;
+
+	/* PLL - POSTDIV */
+	ret = regmap_update_bits(priv->regmap, AN8855_PLL_CTRL_2,
+				 AN8855_RG_DA_QP_PLL_POSTDIV_EN_INTF |
+				 AN8855_RG_DA_QP_PLL_PHY_CK_EN_INTF |
+				 AN8855_RG_DA_QP_PLL_PCK_SEL_INTF,
+				 AN8855_RG_DA_QP_PLL_PCK_SEL_INTF);
+	if (ret)
+		return ret;
+
+	/* PLL - SDM */
+	ret = regmap_update_bits(priv->regmap, AN8855_PLL_CTRL_2,
+				 AN8855_RG_DA_QP_PLL_SDM_HREN_INTF,
+				 FIELD_PREP(AN8855_RG_DA_QP_PLL_SDM_HREN_INTF, 0x0));
+	if (ret)
+		return ret;
+	ret = regmap_clear_bits(priv->regmap, AN8855_PLL_CTRL_2,
+				AN8855_RG_DA_QP_PLL_SDM_IFM_INTF);
+	if (ret)
+		return ret;
+
+	ret = regmap_update_bits(priv->regmap, AN8855_SS_LCPLL_PWCTL_SETTING_2,
+				 AN8855_RG_NCPO_ANA_MSB,
+				 FIELD_PREP(AN8855_RG_NCPO_ANA_MSB, 0x1));
+	if (ret)
+		return ret;
+
+	if (interface == PHY_INTERFACE_MODE_2500BASEX)
+		val = 0x7a000000;
+	else
+		val = 0x48000000;
+	ret = regmap_write(priv->regmap, AN8855_SS_LCPLL_TDC_FLT_2,
+			   FIELD_PREP(AN8855_RG_LCPLL_NCPO_VALUE, val));
+	if (ret)
+		return ret;
+	ret = regmap_write(priv->regmap, AN8855_SS_LCPLL_TDC_PCW_1,
+			   FIELD_PREP(AN8855_RG_LCPLL_PON_HRDDS_PCW_NCPO_GPON, val));
+	if (ret)
+		return ret;
+
+	ret = regmap_clear_bits(priv->regmap, AN8855_SS_LCPLL_TDC_FLT_5,
+				AN8855_RG_LCPLL_NCPO_CHG);
+	if (ret)
+		return ret;
+	ret = regmap_clear_bits(priv->regmap, AN8855_PLL_CK_CTRL_0,
+				AN8855_RG_DA_QP_PLL_SDM_DI_EN_INTF);
+	if (ret)
+		return ret;
+
+	/* PLL - SS */
+	ret = regmap_update_bits(priv->regmap, AN8855_PLL_CTRL_3,
+				 AN8855_RG_DA_QP_PLL_SSC_DELTA_INTF,
+				 FIELD_PREP(AN8855_RG_DA_QP_PLL_SSC_DELTA_INTF, 0x0));
+	if (ret)
+		return ret;
+	ret = regmap_update_bits(priv->regmap, AN8855_PLL_CTRL_4,
+				 AN8855_RG_DA_QP_PLL_SSC_DIR_DLY_INTF,
+				 FIELD_PREP(AN8855_RG_DA_QP_PLL_SSC_DIR_DLY_INTF, 0x0));
+	if (ret)
+		return ret;
+	ret = regmap_update_bits(priv->regmap, AN8855_PLL_CTRL_3,
+				 AN8855_RG_DA_QP_PLL_SSC_PERIOD_INTF,
+				 FIELD_PREP(AN8855_RG_DA_QP_PLL_SSC_PERIOD_INTF, 0x0));
+	if (ret)
+		return ret;
+
+	/* PLL - TDC */
+	ret = regmap_clear_bits(priv->regmap, AN8855_PLL_CK_CTRL_0,
+				AN8855_RG_DA_QP_PLL_TDC_TXCK_SEL_INTF);
+	if (ret)
+		return ret;
+
+	ret = regmap_set_bits(priv->regmap, AN8855_RG_QP_PLL_SDM_ORD,
+			      AN8855_RG_QP_PLL_SSC_TRI_EN);
+	if (ret)
+		return ret;
+	ret = regmap_set_bits(priv->regmap, AN8855_RG_QP_PLL_SDM_ORD,
+			      AN8855_RG_QP_PLL_SSC_PHASE_INI);
+	if (ret)
+		return ret;
+
+	ret = regmap_update_bits(priv->regmap, AN8855_RG_QP_RX_DAC_EN,
+				 AN8855_RG_QP_SIGDET_HF,
+				 FIELD_PREP(AN8855_RG_QP_SIGDET_HF, 0x2));
+	if (ret)
+		return ret;
+
+	/* TCL Disable (only for Co-SIM) */
+	ret = regmap_clear_bits(priv->regmap, AN8855_PON_RXFEDIG_CTRL_0,
+				AN8855_RG_QP_EQ_RX500M_CK_SEL);
+	if (ret)
+		return ret;
+
+	/* TX Init */
+	if (interface == PHY_INTERFACE_MODE_2500BASEX)
+		val = 0x4;
+	else
+		val = 0x0;
+	ret = regmap_update_bits(priv->regmap, AN8855_RG_QP_TX_MODE,
+				 AN8855_RG_QP_TX_RESERVE |
+				 AN8855_RG_QP_TX_MODE_16B_EN,
+				 FIELD_PREP(AN8855_RG_QP_TX_RESERVE, val));
+	if (ret)
+		return ret;
+
+	/* RX Control/Init */
+	ret = regmap_set_bits(priv->regmap, AN8855_RG_QP_RXAFE_RESERVE,
+			      AN8855_RG_QP_CDR_PD_10B_EN);
+	if (ret)
+		return ret;
+
+	if (interface == PHY_INTERFACE_MODE_2500BASEX)
+		val = 0x1;
+	else
+		val = 0x2;
+	ret = regmap_update_bits(priv->regmap, AN8855_RG_QP_CDR_LPF_MJV_LIM,
+				 AN8855_RG_QP_CDR_LPF_RATIO,
+				 FIELD_PREP(AN8855_RG_QP_CDR_LPF_RATIO, val));
+	if (ret)
+		return ret;
+
+	ret = regmap_update_bits(priv->regmap, AN8855_RG_QP_CDR_LPF_SETVALUE,
+				 AN8855_RG_QP_CDR_PR_BUF_IN_SR |
+				 AN8855_RG_QP_CDR_PR_BETA_SEL,
+				 FIELD_PREP(AN8855_RG_QP_CDR_PR_BUF_IN_SR, 0x6) |
+				 FIELD_PREP(AN8855_RG_QP_CDR_PR_BETA_SEL, 0x1));
+	if (ret)
+		return ret;
+
+	if (interface == PHY_INTERFACE_MODE_2500BASEX)
+		val = 0xf;
+	else
+		val = 0xc;
+	ret = regmap_update_bits(priv->regmap, AN8855_RG_QP_CDR_PR_CKREF_DIV1,
+				 AN8855_RG_QP_CDR_PR_DAC_BAND,
+				 FIELD_PREP(AN8855_RG_QP_CDR_PR_DAC_BAND, val));
+	if (ret)
+		return ret;
+
+	ret = regmap_update_bits(priv->regmap, AN8855_RG_QP_CDR_PR_KBAND_DIV_PCIE,
+				 AN8855_RG_QP_CDR_PR_KBAND_PCIE_MODE |
+				 AN8855_RG_QP_CDR_PR_KBAND_DIV_PCIE_MASK,
+				 FIELD_PREP(AN8855_RG_QP_CDR_PR_KBAND_DIV_PCIE_MASK, 0x19));
+	if (ret)
+		return ret;
+
+	ret = regmap_update_bits(priv->regmap, AN8855_RG_QP_CDR_FORCE_IBANDLPF_R_OFF,
+				 AN8855_RG_QP_CDR_PHYCK_SEL |
+				 AN8855_RG_QP_CDR_PHYCK_RSTB |
+				 AN8855_RG_QP_CDR_PHYCK_DIV,
+				 FIELD_PREP(AN8855_RG_QP_CDR_PHYCK_SEL, 0x2) |
+				 FIELD_PREP(AN8855_RG_QP_CDR_PHYCK_DIV, 0x21));
+	if (ret)
+		return ret;
+
+	ret = regmap_clear_bits(priv->regmap, AN8855_RG_QP_CDR_PR_KBAND_DIV_PCIE,
+				AN8855_RG_QP_CDR_PR_XFICK_EN);
+	if (ret)
+		return ret;
+
+	ret = regmap_update_bits(priv->regmap, AN8855_RG_QP_CDR_PR_CKREF_DIV1,
+				 AN8855_RG_QP_CDR_PR_KBAND_DIV,
+				 FIELD_PREP(AN8855_RG_QP_CDR_PR_KBAND_DIV, 0x4));
+	if (ret)
+		return ret;
+
+	ret = regmap_update_bits(priv->regmap, AN8855_RX_CTRL_26,
+				 AN8855_RG_QP_EQ_RETRAIN_ONLY_EN |
+				 AN8855_RG_LINK_NE_EN |
+				 AN8855_RG_LINK_ERRO_EN,
+				 AN8855_RG_QP_EQ_RETRAIN_ONLY_EN |
+				 AN8855_RG_LINK_ERRO_EN);
+	if (ret)
+		return ret;
+
+	ret = regmap_update_bits(priv->regmap, AN8855_RX_DLY_0,
+				 AN8855_RG_QP_RX_SAOSC_EN_H_DLY |
+				 AN8855_RG_QP_RX_PI_CAL_EN_H_DLY,
+				 FIELD_PREP(AN8855_RG_QP_RX_SAOSC_EN_H_DLY, 0x3f) |
+				 FIELD_PREP(AN8855_RG_QP_RX_PI_CAL_EN_H_DLY, 0x6f));
+	if (ret)
+		return ret;
+
+	ret = regmap_update_bits(priv->regmap, AN8855_RX_CTRL_42,
+				 AN8855_RG_QP_EQ_EN_DLY,
+				 FIELD_PREP(AN8855_RG_QP_EQ_EN_DLY, 0x150));
+	if (ret)
+		return ret;
+
+	ret = regmap_update_bits(priv->regmap, AN8855_RX_CTRL_2,
+				 AN8855_RG_QP_RX_EQ_EN_H_DLY,
+				 FIELD_PREP(AN8855_RG_QP_RX_EQ_EN_H_DLY, 0x150));
+	if (ret)
+		return ret;
+
+	ret = regmap_update_bits(priv->regmap, AN8855_PON_RXFEDIG_CTRL_9,
+				 AN8855_RG_QP_EQ_LEQOSC_DLYCNT,
+				 FIELD_PREP(AN8855_RG_QP_EQ_LEQOSC_DLYCNT, 0x1));
+	if (ret)
+		return ret;
+
+	ret = regmap_update_bits(priv->regmap, AN8855_RX_CTRL_8,
+				 AN8855_RG_DA_QP_SAOSC_DONE_TIME |
+				 AN8855_RG_DA_QP_LEQOS_EN_TIME,
+				 FIELD_PREP(AN8855_RG_DA_QP_SAOSC_DONE_TIME, 0x200) |
+				 FIELD_PREP(AN8855_RG_DA_QP_LEQOS_EN_TIME, 0xfff));
+	if (ret)
+		return ret;
+
+	/* Frequency meter */
+	if (interface == PHY_INTERFACE_MODE_2500BASEX)
+		val = 0x10;
+	else
+		val = 0x28;
+	ret = regmap_update_bits(priv->regmap, AN8855_RX_CTRL_5,
+				 AN8855_RG_FREDET_CHK_CYCLE,
+				 FIELD_PREP(AN8855_RG_FREDET_CHK_CYCLE, val));
+	if (ret)
+		return ret;
+
+	ret = regmap_update_bits(priv->regmap, AN8855_RX_CTRL_6,
+				 AN8855_RG_FREDET_GOLDEN_CYCLE,
+				 FIELD_PREP(AN8855_RG_FREDET_GOLDEN_CYCLE, 0x64));
+	if (ret)
+		return ret;
+
+	ret = regmap_update_bits(priv->regmap, AN8855_RX_CTRL_7,
+				 AN8855_RG_FREDET_TOLERATE_CYCLE,
+				 FIELD_PREP(AN8855_RG_FREDET_TOLERATE_CYCLE, 0x2710));
+	if (ret)
+		return ret;
+
+	ret = regmap_set_bits(priv->regmap, AN8855_PLL_CTRL_0,
+			      AN8855_RG_PHYA_AUTO_INIT);
+	if (ret)
+		return ret;
+
+	/* PCS Init */
+	if (interface == PHY_INTERFACE_MODE_SGMII &&
+	    neg_mode == PHYLINK_PCS_NEG_INBAND_DISABLED) {
+		ret = regmap_clear_bits(priv->regmap, AN8855_QP_DIG_MODE_CTRL_0,
+					AN8855_RG_SGMII_MODE | AN8855_RG_SGMII_AN_EN);
+		if (ret)
+			return ret;
+	}
+
+	ret = regmap_clear_bits(priv->regmap, AN8855_RG_HSGMII_PCS_CTROL_1,
+				AN8855_RG_TBI_10B_MODE);
+	if (ret)
+		return ret;
+
+	if (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED) {
+		/* Set AN Ability - Interrupt */
+		ret = regmap_set_bits(priv->regmap, AN8855_SGMII_REG_AN_FORCE_CL37,
+				      AN8855_RG_FORCE_AN_DONE);
+		if (ret)
+			return ret;
+
+		ret = regmap_update_bits(priv->regmap, AN8855_SGMII_REG_AN_13,
+					 AN8855_SGMII_REMOTE_FAULT_DIS |
+					 AN8855_SGMII_IF_MODE,
+					 AN8855_SGMII_REMOTE_FAULT_DIS |
+					 FIELD_PREP(AN8855_SGMII_IF_MODE, 0xb));
+		if (ret)
+			return ret;
+	}
+
+	/* Rate Adaption - GMII path config. */
+	if (interface == PHY_INTERFACE_MODE_2500BASEX) {
+		ret = regmap_clear_bits(priv->regmap, AN8855_RATE_ADP_P0_CTRL_0,
+					AN8855_RG_P0_DIS_MII_MODE);
+		if (ret)
+			return ret;
+	} else {
+		if (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED) {
+			ret = regmap_set_bits(priv->regmap, AN8855_MII_RA_AN_ENABLE,
+					      AN8855_RG_P0_RA_AN_EN);
+			if (ret)
+				return ret;
+		} else {
+			ret = regmap_update_bits(priv->regmap, AN8855_RG_AN_SGMII_MODE_FORCE,
+						 AN8855_RG_FORCE_CUR_SGMII_MODE |
+						 AN8855_RG_FORCE_CUR_SGMII_SEL,
+						 AN8855_RG_FORCE_CUR_SGMII_SEL);
+			if (ret)
+				return ret;
+
+			ret = regmap_clear_bits(priv->regmap, AN8855_RATE_ADP_P0_CTRL_0,
+						AN8855_RG_P0_MII_RA_RX_EN |
+						AN8855_RG_P0_MII_RA_TX_EN |
+						AN8855_RG_P0_MII_RA_RX_MODE |
+						AN8855_RG_P0_MII_RA_TX_MODE);
+			if (ret)
+				return ret;
+		}
+
+		ret = regmap_set_bits(priv->regmap, AN8855_RATE_ADP_P0_CTRL_0,
+				      AN8855_RG_P0_MII_MODE);
+		if (ret)
+			return ret;
+	}
+
+	ret = regmap_set_bits(priv->regmap, AN8855_RG_RATE_ADAPT_CTRL_0,
+			      AN8855_RG_RATE_ADAPT_RX_BYPASS |
+			      AN8855_RG_RATE_ADAPT_TX_BYPASS |
+			      AN8855_RG_RATE_ADAPT_RX_EN |
+			      AN8855_RG_RATE_ADAPT_TX_EN);
+	if (ret)
+		return ret;
+
+	/* Disable AN if not in autoneg */
+	ret = regmap_update_bits(priv->regmap, AN8855_SGMII_REG_AN0, BMCR_ANENABLE,
+				 neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED ? BMCR_ANENABLE :
+									      0);
+	if (ret)
+		return ret;
+
+	if (interface == PHY_INTERFACE_MODE_SGMII) {
+		/* Follow SDK init flow with restarting AN after AN enable */
+		if (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED) {
+			ret = regmap_set_bits(priv->regmap, AN8855_SGMII_REG_AN0,
+					      BMCR_ANRESTART);
+			if (ret)
+				return ret;
+		} else {
+			ret = regmap_set_bits(priv->regmap, AN8855_PHY_RX_FORCE_CTRL_0,
+					      AN8855_RG_FORCE_TXC_SEL);
+			if (ret)
+				return ret;
+		}
+	}
+
+	/* Force Speed with fixed-link or 2500base-x as doesn't support aneg */
+	if (interface == PHY_INTERFACE_MODE_2500BASEX ||
+	    neg_mode != PHYLINK_PCS_NEG_INBAND_ENABLED) {
+		if (interface == PHY_INTERFACE_MODE_2500BASEX)
+			val = AN8855_RG_LINK_MODE_P0_SPEED_2500;
+		else
+			val = AN8855_RG_LINK_MODE_P0_SPEED_1000;
+		ret = regmap_update_bits(priv->regmap, AN8855_SGMII_STS_CTRL_0,
+					 AN8855_RG_LINK_MODE_P0 |
+					 AN8855_RG_FORCE_SPD_MODE_P0,
+					 val | AN8855_RG_FORCE_SPD_MODE_P0);
+		if (ret)
+			return ret;
+	}
+
+	/* bypass flow control to MAC */
+	ret = regmap_write(priv->regmap, AN8855_MSG_RX_LIK_STS_0,
+			   AN8855_RG_DPX_STS_P3 | AN8855_RG_DPX_STS_P2 |
+			   AN8855_RG_DPX_STS_P1 | AN8855_RG_TXFC_STS_P0 |
+			   AN8855_RG_RXFC_STS_P0 | AN8855_RG_DPX_STS_P0);
+	if (ret)
+		return ret;
+	ret = regmap_write(priv->regmap, AN8855_MSG_RX_LIK_STS_2,
+			   AN8855_RG_RXFC_AN_BYPASS_P3 |
+			   AN8855_RG_RXFC_AN_BYPASS_P2 |
+			   AN8855_RG_RXFC_AN_BYPASS_P1 |
+			   AN8855_RG_TXFC_AN_BYPASS_P3 |
+			   AN8855_RG_TXFC_AN_BYPASS_P2 |
+			   AN8855_RG_TXFC_AN_BYPASS_P1 |
+			   AN8855_RG_DPX_AN_BYPASS_P3 |
+			   AN8855_RG_DPX_AN_BYPASS_P2 |
+			   AN8855_RG_DPX_AN_BYPASS_P1 |
+			   AN8855_RG_DPX_AN_BYPASS_P0);
+	if (ret)
+		return ret;
+
+	return 0;
+}
+
+static void an8855_pcs_an_restart(struct phylink_pcs *pcs)
+{
+}
+
+static const struct phylink_pcs_ops an8855_pcs_ops = {
+	.pcs_inband_caps = an8855_pcs_inband_caps,
+	.pcs_get_state = an8855_pcs_get_state,
+	.pcs_config = an8855_pcs_config,
+	.pcs_an_restart = an8855_pcs_an_restart,
+};
+
+static const struct phylink_mac_ops an8855_phylink_mac_ops = {
+	.mac_select_pcs	= an8855_phylink_mac_select_pcs,
+	.mac_config	= an8855_phylink_mac_config,
+	.mac_link_down	= an8855_phylink_mac_link_down,
+	.mac_link_up	= an8855_phylink_mac_link_up,
+	.mac_disable_tx_lpi = an8855_phylink_mac_disable_tx_lpi,
+	.mac_enable_tx_lpi = an8855_phylink_mac_enable_tx_lpi,
+};
+
+static const struct dsa_switch_ops an8855_switch_ops = {
+	.get_tag_protocol = an8855_get_tag_protocol,
+	.setup = an8855_setup,
+	.phylink_get_caps = an8855_phylink_get_caps,
+	.get_strings = an8855_get_strings,
+	.get_ethtool_stats = an8855_get_ethtool_stats,
+	.get_sset_count = an8855_get_sset_count,
+	.get_eth_mac_stats = an8855_get_eth_mac_stats,
+	.get_eth_ctrl_stats = an8855_get_eth_ctrl_stats,
+	.get_rmon_stats = an8855_get_rmon_stats,
+	.port_enable = an8855_port_enable,
+	.port_disable = an8855_port_disable,
+	.set_ageing_time = an8855_set_ageing_time,
+	.port_bridge_join = an8855_port_bridge_join,
+	.port_bridge_leave = an8855_port_bridge_leave,
+	.port_fast_age = an8855_port_fast_age,
+	.port_stp_state_set = an8855_port_stp_state_set,
+	.port_pre_bridge_flags = an8855_port_pre_bridge_flags,
+	.port_bridge_flags = an8855_port_bridge_flags,
+	.port_vlan_filtering = an8855_port_vlan_filtering,
+	.port_vlan_add = an8855_port_vlan_add,
+	.port_vlan_del = an8855_port_vlan_del,
+	.port_fdb_add = an8855_port_fdb_add,
+	.port_fdb_del = an8855_port_fdb_del,
+	.port_fdb_dump = an8855_port_fdb_dump,
+	.port_mdb_add = an8855_port_mdb_add,
+	.port_mdb_del = an8855_port_mdb_del,
+	.port_change_mtu = an8855_port_change_mtu,
+	.port_max_mtu = an8855_port_max_mtu,
+	.port_mirror_add = an8855_port_mirror_add,
+	.port_mirror_del = an8855_port_mirror_del,
+	.support_eee = dsa_supports_eee,
+	.set_mac_eee = an8855_set_mac_eee,
+};
+
+static int an8855_setup_lib_priv(struct an8855_priv *priv)
+{
+	struct mt7530_lib_priv *lib_priv = &priv->lib_priv;
+	int i;
+
+	lib_priv->dev = priv->ds->dev;
+	lib_priv->ds = priv->ds;
+	lib_priv->regmap = priv->regmap;
+	lib_priv->ports = priv->ports;
+	lib_priv->reg_mutex = &priv->reg_mutex;
+
+	for (i = 0; i < ARRAY_SIZE(an8855_fields); i++) {
+		const struct mt7530_reg_field *reg_field;
+		struct regmap_field *field;
+
+		reg_field = &an8855_fields[i];
+		field = devm_regmap_field_alloc(priv->ds->dev, priv->regmap,
+						reg_field->field);
+		if (IS_ERR(field))
+			return PTR_ERR(field);
+
+		lib_priv->fields[reg_field->id] = field;
+	}
+
+	return 0;
+}
+
+static int an8855_switch_probe(struct platform_device *pdev)
+{
+	struct an8855_priv *priv;
+	int ret;
+
+	priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
+	if (!priv)
+		return -ENOMEM;
+
+	/* Get regmap from MFD */
+	priv->regmap = dev_get_regmap(pdev->dev.parent, NULL);
+	if (!priv->regmap)
+		return -ENOENT;
+
+	priv->ds = devm_kzalloc(&pdev->dev, sizeof(*priv->ds), GFP_KERNEL);
+	if (!priv->ds)
+		return -ENOMEM;
+
+	priv->ds->dev = &pdev->dev;
+	priv->ds->num_ports = AN8855_NUM_PORTS;
+	priv->ds->priv = priv;
+	priv->ds->ops = &an8855_switch_ops;
+	ret = devm_mutex_init(&pdev->dev, &priv->reg_mutex);
+	if (ret)
+		return ret;
+	priv->ds->phylink_mac_ops = &an8855_phylink_mac_ops;
+
+	priv->pcs.ops = &an8855_pcs_ops;
+	priv->pcs.poll = true;
+
+	ret = an8855_setup_lib_priv(priv);
+	if (ret)
+		return ret;
+
+	dev_set_drvdata(&pdev->dev, priv);
+
+	return dsa_register_switch(priv->ds);
+}
+
+static void an8855_switch_remove(struct platform_device *pdev)
+{
+	struct an8855_priv *priv = dev_get_drvdata(&pdev->dev);
+
+	if (!priv)
+		return;
+
+	dsa_unregister_switch(priv->ds);
+
+	dev_set_drvdata(&pdev->dev, NULL);
+}
+
+static void an8855_switch_shutdown(struct platform_device *pdev)
+{
+	struct an8855_priv *priv = dev_get_drvdata(&pdev->dev);
+
+	if (!priv)
+		return;
+
+	dsa_switch_shutdown(priv->ds);
+
+	dev_set_drvdata(&pdev->dev, NULL);
+}
+
+static const struct of_device_id an8855_switch_of_match[] = {
+	{ .compatible = "airoha,an8855-switch" },
+	{ /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, an8855_switch_of_match);
+
+static struct platform_driver an8855_switch_driver = {
+	.probe = an8855_switch_probe,
+	.remove = an8855_switch_remove,
+	.shutdown = an8855_switch_shutdown,
+	.driver = {
+		.name = "an8855-switch",
+		.of_match_table = an8855_switch_of_match,
+	},
+};
+module_platform_driver(an8855_switch_driver);
+
+MODULE_AUTHOR("Min Yao <min.yao@airoha.com>");
+MODULE_AUTHOR("Christian Marangi <ansuelsmth@gmail.com>");
+MODULE_DESCRIPTION("Driver for Airoha AN8855 Switch");
+MODULE_LICENSE("GPL");
diff --git a/drivers/net/dsa/an8855.h b/drivers/net/dsa/an8855.h
new file mode 100644
index 000000000000..85003e568450
--- /dev/null
+++ b/drivers/net/dsa/an8855.h
@@ -0,0 +1,755 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (C) 2023 Min Yao <min.yao@airoha.com>
+ * Copyright (C) 2024 Christian Marangi <ansuelsmth@gmail.com>
+ */
+
+#ifndef __AN8855_H
+#define __AN8855_H
+
+#include <linux/bitfield.h>
+
+#include "mt7530-lib.h"
+
+#define AN8855_NUM_PORTS		6
+#define AN8855_CPU_PORT			5
+#define AN8855_NUM_FDB_RECORDS		2048
+#define AN8855_GPHY_SMI_ADDR_DEFAULT	1
+#define AN8855_PORT_VID_DEFAULT		0
+
+#define MTK_TAG_LEN			4
+#define AN8855_MAX_MTU			(15360 - ETH_HLEN - ETH_FCS_LEN - MTK_TAG_LEN)
+
+#define AN8855_L2_AGING_MS_CONSTANT	1024
+
+#define AN8855_TX_LPI_UNIT		2 /* us */
+
+/*	AN8855_SCU			0x10000000 */
+#define AN8855_RG_GPIO_LED_MODE		0x10000054
+#define AN8855_RG_GPIO_LED_SEL(i)	(0x10000000 + (0x0058 + ((i) * 4)))
+#define AN8855_RG_INTB_MODE		0x10000080
+#define AN8855_RG_RGMII_TXCK_C		0x100001d0
+
+#define AN8855_PKG_SEL			0x10000094
+#define   AN8855_PAG_SEL_AN8855H	0x2
+
+#define AN8855_RG_GPIO_L_INV		0x10000010
+#define AN8855_RG_GPIO_CTRL		0x1000a300
+#define AN8855_RG_GPIO_DATA		0x1000a304
+#define AN8855_RG_GPIO_OE		0x1000a314
+
+/* Register for system reset */
+#define AN8855_RST_CTRL			0x100050c0
+#define   AN8855_SYS_CTRL_SYS_RST	BIT(31)
+
+#define AN8855_INT_MASK			0x100050f0
+#define   AN8855_INT_SYS		BIT(15)
+
+#define AN8855_RG_CLK_CPU_ICG		0x10005034
+#define   AN8855_MCU_ENABLE		BIT(3)
+
+#define AN8855_RG_TIMER_CTL		0x1000a100
+#define   AN8855_WDOG_ENABLE		BIT(25)
+
+#define AN8855_RG_GDMP_RAM		0x10010000
+
+/* Registers to mac forward control for unknown frames */
+#define AN8855_MFC			0x10200010
+#define   AN8855_CPU_EN			BIT(15)
+#define   AN8855_CPU_PORT_IDX		GENMASK(12, 8)
+
+#define AN8855_PAC			0x10200024
+#define   AN8855_TAG_PAE_MANG_FR	BIT(30)
+#define   AN8855_TAG_PAE_BPDU_FR	BIT(28)
+#define   AN8855_TAG_PAE_EG_TAG		GENMASK(27, 25)
+#define   AN8855_TAG_PAE_LKY_VLAN	BIT(24)
+#define   AN8855_TAG_PAE_PRI_HIGH	BIT(23)
+#define   AN8855_TAG_PAE_MIR		GENMASK(20, 19)
+#define   AN8855_TAG_PAE_PORT_FW	GENMASK(18, 16)
+#define   AN8855_PAE_MANG_FR		BIT(14)
+#define   AN8855_PAE_BPDU_FR		BIT(12)
+#define   AN8855_PAE_EG_TAG		GENMASK(11, 9)
+#define   AN8855_PAE_LKY_VLAN		BIT(8)
+#define   AN8855_PAE_PRI_HIGH		BIT(7)
+#define   AN8855_PAE_MIR		GENMASK(4, 3)
+#define   AN8855_PAE_PORT_FW		GENMASK(2, 0)
+
+#define AN8855_RGAC1			0x10200028
+#define   AN8855_R02_MANG_FR		BIT(30)
+#define   AN8855_R02_BPDU_FR		BIT(28)
+#define   AN8855_R02_EG_TAG		GENMASK(27, 25)
+#define   AN8855_R02_LKY_VLAN		BIT(24)
+#define   AN8855_R02_PRI_HIGH		BIT(23)
+#define   AN8855_R02_MIR		GENMASK(20, 19)
+#define   AN8855_R02_PORT_FW		GENMASK(18, 16)
+#define   AN8855_R01_MANG_FR		BIT(14)
+#define   AN8855_R01_BPDU_FR		BIT(12)
+#define   AN8855_R01_EG_TAG		GENMASK(11, 9)
+#define   AN8855_R01_LKY_VLAN		BIT(8)
+#define   AN8855_R01_PRI_HIGH		BIT(7)
+#define   AN8855_R01_MIR		GENMASK(4, 3)
+#define   AN8855_R01_PORT_FW		GENMASK(2, 0)
+
+#define AN8855_RGAC2			0x1020002c
+#define   AN8855_R0E_MANG_FR		BIT(30)
+#define   AN8855_R0E_BPDU_FR		BIT(28)
+#define   AN8855_R0E_EG_TAG		GENMASK(27, 25)
+#define   AN8855_R0E_LKY_VLAN		BIT(24)
+#define   AN8855_R0E_PRI_HIGH		BIT(23)
+#define   AN8855_R0E_MIR		GENMASK(20, 19)
+#define   AN8855_R0E_PORT_FW		GENMASK(18, 16)
+#define   AN8855_R03_MANG_FR		BIT(14)
+#define   AN8855_R03_BPDU_FR		BIT(12)
+#define   AN8855_R03_EG_TAG		GENMASK(11, 9)
+#define   AN8855_R03_LKY_VLAN		BIT(8)
+#define   AN8855_R03_PRI_HIGH		BIT(7)
+#define   AN8855_R03_MIR		GENMASK(4, 3)
+#define   AN8855_R03_PORT_FW		GENMASK(2, 0)
+
+#define AN8855_AAC			0x102000a0
+#define   AN8855_MAC_AUTO_FLUSH		BIT(28)
+/* Control Address Table Age time.
+ * (AN8855_AGE_CNT + 1) * ( AN8855_AGE_UNIT + 1 ) * AN8855_L2_AGING_MS_CONSTANT
+ */
+#define   AN8855_AGE_CNT		GENMASK(20, 12)
+/* Value in seconds. Value is always incremented of 1 */
+#define   AN8855_AGE_UNIT		GENMASK(10, 0)
+
+/* Registers for ARL Unknown Unicast Forward control */
+#define AN8855_UNUF			0x102000b4
+
+/* Registers for ARL Unknown Multicast Forward control */
+#define AN8855_UNMF			0x102000b8
+
+/* Registers for ARL Broadcast forward control */
+#define AN8855_BCF			0x102000bc
+
+/* Registers for port address age disable */
+#define AN8855_AGDIS			0x102000c0
+
+/* Registers for mirror port control */
+#define AN8855_MIR			0x102000cc
+#define   AN8855_MIRROR_EN		BIT(7)
+#define   AN8855_MIRROR_PORT		GENMASK(4, 0)
+
+/* Registers for BPDU and PAE frame control*/
+#define AN8855_BPC			0x102000d0
+#define   AN8855_BPDU_MANG_FR		BIT(14)
+#define   AN8855_BPDU_BPDU_FR		BIT(12)
+#define   AN8855_BPDU_EG_TAG		GENMASK(11, 9)
+#define   AN8855_BPDU_LKY_VLAN		BIT(8)
+#define   AN8855_BPDU_PRI_HIGH		BIT(7)
+#define   AN8855_BPDU_MIR		GENMASK(4, 3)
+#define   AN8855_BPDU_PORT_FW		GENMASK(2, 0)
+
+/* Registers for IP Unknown Multicast Forward control */
+#define AN8855_UNIPMF			0x102000dc
+
+enum an8855_bpdu_port_fw {
+	AN8855_BPDU_FOLLOW_MFC = 0,
+	AN8855_BPDU_CPU_EXCLUDE = 4,
+	AN8855_BPDU_CPU_INCLUDE = 5,
+	AN8855_BPDU_CPU_ONLY = 6,
+	AN8855_BPDU_DROP = 7,
+};
+
+/* Register for address table control */
+#define AN8855_ATC			0x10200300
+#define   AN8855_ATC_BUSY		BIT(31)
+#define   AN8855_ATC_HASH		GENMASK(24, 16)
+#define   AN8855_ATC_HIT		GENMASK(15, 12)
+#define   AN8855_ATC_MAT_MASK		GENMASK(11, 7)
+#define   AN8855_ATC_MAT(x)		FIELD_PREP(AN8855_ATC_MAT_MASK, x)
+#define   AN8855_ATC_SAT		GENMASK(5, 4)
+#define   AN8855_ATC_CMD		GENMASK(2, 0)
+
+enum an8855_fdb_mat_cmds {
+	AN8855_FDB_MAT_ALL = 0,
+	AN8855_FDB_MAT_MAC, /* All MAC address */
+	AN8855_FDB_MAT_DYNAMIC_MAC, /* All Dynamic MAC address */
+	AN8855_FDB_MAT_STATIC_MAC, /* All Static Mac Address */
+	AN8855_FDB_MAT_DIP, /* All DIP/GA address */
+	AN8855_FDB_MAT_DIP_IPV4, /* All DIP/GA IPv4 address */
+	AN8855_FDB_MAT_DIP_IPV6, /* All DIP/GA IPv6 address */
+	AN8855_FDB_MAT_DIP_SIP, /* All DIP_SIP address */
+	AN8855_FDB_MAT_DIP_SIP_IPV4, /* All DIP_SIP IPv4 address */
+	AN8855_FDB_MAT_DIP_SIP_IPV6, /* All DIP_SIP IPv6 address */
+	AN8855_FDB_MAT_MAC_CVID, /* All MAC address with CVID */
+	AN8855_FDB_MAT_MAC_FID, /* All MAC address with Filter ID */
+	AN8855_FDB_MAT_MAC_PORT, /* All MAC address with port */
+	AN8855_FDB_MAT_DIP_SIP_DIP_IPV4, /* All DIP_SIP address with DIP_IPV4 */
+	AN8855_FDB_MAT_DIP_SIP_SIP_IPV4, /* All DIP_SIP address with SIP_IPV4 */
+	AN8855_FDB_MAT_DIP_SIP_DIP_IPV6, /* All DIP_SIP address with DIP_IPV6 */
+	AN8855_FDB_MAT_DIP_SIP_SIP_IPV6, /* All DIP_SIP address with SIP_IPV6 */
+	/* All MAC address with MAC type (dynamic or static) with CVID */
+	AN8855_FDB_MAT_MAC_TYPE_CVID,
+	/* All MAC address with MAC type (dynamic or static) with Filter ID */
+	AN8855_FDB_MAT_MAC_TYPE_FID,
+	/* All MAC address with MAC type (dynamic or static) with port */
+	AN8855_FDB_MAT_MAC_TYPE_PORT,
+};
+
+/* Registers for address table access */
+#define AN8855_ATA1			0x10200304
+#define   AN8855_ATA1_MAC0		GENMASK(31, 24)
+#define   AN8855_ATA1_MAC1		GENMASK(23, 16)
+#define   AN8855_ATA1_MAC2		GENMASK(15, 8)
+#define   AN8855_ATA1_MAC3		GENMASK(7, 0)
+#define AN8855_ATA2			0x10200308
+#define   AN8855_ATA2_MAC4		GENMASK(31, 24)
+#define   AN8855_ATA2_MAC5		GENMASK(23, 16)
+#define   AN8855_ATA2_UNAUTH		BIT(10)
+#define   AN8855_ATA2_TYPE		BIT(9) /* 1: dynamic, 0: static */
+#define   AN8855_ATA2_AGE		GENMASK(8, 0)
+
+/* Register for address table write data */
+#define AN8855_ATWD			0x10200324
+#define   AN8855_ATWD_FID		GENMASK(31, 28)
+#define   AN8855_ATWD_VID		GENMASK(27, 16)
+#define   AN8855_ATWD_IVL		BIT(15)
+#define   AN8855_ATWD_EG_TAG		GENMASK(14, 12)
+#define   AN8855_ATWD_SA_MIR		GENMASK(9, 8)
+#define   AN8855_ATWD_SA_FWD		GENMASK(7, 5)
+#define   AN8855_ATWD_UPRI		GENMASK(4, 2)
+#define   AN8855_ATWD_LEAKY		BIT(1)
+#define   AN8855_ATWD_VLD_MASK		BIT(0) /* vid LOAD */
+#define AN8855_ATWD2			0x10200328
+#define   AN8855_ATWD2_PORT		GENMASK(7, 0)
+
+/* Registers for table search read address */
+#define AN8855_ATRDS			0x10200330
+#define   AN8855_ATRD_SEL		GENMASK(1, 0)
+#define AN8855_ATRD0			0x10200334
+#define   AN8855_ATRD0_FID		GENMASK(28, 25)
+#define   AN8855_ATRD0_VID		GENMASK(21, 10)
+#define   AN8855_ATRD0_IVL		BIT(9)
+#define   AN8855_ATRD0_TYPE		GENMASK(4, 3)
+#define   AN8855_ATRD0_ARP		GENMASK(2, 1)
+#define   AN8855_ATRD0_LIVE		BIT(0)
+#define AN8855_ATRD1			0x10200338
+#define   AN8855_ATRD1_MAC4		GENMASK(31, 24)
+#define   AN8855_ATRD1_MAC5		GENMASK(23, 16)
+#define   AN8855_ATRD1_AGING		GENMASK(11, 3)
+#define AN8855_ATRD2			0x1020033c
+#define   AN8855_ATRD2_MAC0		GENMASK(31, 24)
+#define   AN8855_ATRD2_MAC1		GENMASK(23, 16)
+#define   AN8855_ATRD2_MAC2		GENMASK(15, 8)
+#define   AN8855_ATRD2_MAC3		GENMASK(7, 0)
+#define AN8855_ATRD3			0x10200340
+#define   AN8855_ATRD3_PORTMASK		GENMASK(7, 0)
+
+enum an8855_fdb_type {
+	AN8855_MAC_TB_TY_MAC = 0,
+	AN8855_MAC_TB_TY_DIP = 1,
+	AN8855_MAC_TB_TY_DIP_SIP = 2,
+};
+
+/* Register for vlan table control */
+#define AN8855_VTCR			0x10200600
+#define   AN8855_VTCR_BUSY		BIT(31)
+#define   AN8855_VTCR_FUNC		GENMASK(15, 12)
+#define   AN8855_VTCR_VID		GENMASK(11, 0)
+
+enum an8855_vlan_cmd {
+	/* Read/Write the specified VID entry from VAWD register based
+	 * on VID.
+	 */
+	AN8855_VTCR_RD_VID = 0,
+	AN8855_VTCR_WR_VID = 1,
+};
+
+/* Register for setup vlan write data */
+#define AN8855_VAWD0			0x10200604
+/* VLAN Member Control */
+#define   AN8855_VA0_PORT		GENMASK(31, 26)
+/* Egress Tag Control */
+#define   AN8855_VA0_ETAG		GENMASK(23, 12)
+#define   AN8855_VA0_ETAG_PORT		GENMASK(13, 12)
+#define   AN8855_VA0_ETAG_PORT_SHIFT(port) ((port) * 2)
+#define   AN8855_VA0_ETAG_PORT_MASK(port) (AN8855_VA0_ETAG_PORT << \
+						AN8855_VA0_ETAG_PORT_SHIFT(port))
+#define   AN8855_VA0_ETAG_PORT_VAL(port, val) (FIELD_PREP(AN8855_VA0_ETAG_PORT, (val)) << \
+						AN8855_VA0_ETAG_PORT_SHIFT(port))
+#define   AN8855_VA0_EG_CON		BIT(11)
+#define   AN8855_VA0_VTAG_EN		BIT(10) /* Per VLAN Egress Tag Control */
+#define   AN8855_VA0_IVL_MAC		BIT(5) /* Independent VLAN Learning */
+#define	  AN8855_VA0_FID		GENMASK(4, 1)
+#define   AN8855_VA0_VLAN_VALID		BIT(0) /* VLAN Entry Valid */
+#define AN8855_VAWD1			0x10200608
+#define   AN8855_VA1_PORT_STAG		BIT(1)
+
+enum an8855_fid {
+	AN8855_FID_STANDALONE = 0,
+	AN8855_FID_BRIDGED = 1,
+};
+
+/* Same register field of VAWD0 */
+#define AN8855_VARD0			0x10200618
+
+enum an8855_vlan_egress_attr {
+	AN8855_VLAN_EGRESS_UNTAG = 0,
+	AN8855_VLAN_EGRESS_TAG = 2,
+	AN8855_VLAN_EGRESS_STACK = 3,
+};
+
+/* Register for port STP state control */
+#define AN8855_SSP			0x10208000
+#define AN8855_SSP_P(x)			(AN8855_SSP + ((x) * 0x200))
+/* Up to 16 FID supported, each with the same mask */
+#define	  AN8855_FID_PST		GENMASK(1, 0)
+#define   AN8855_FID_PST_SHIFT(fid)	(2 * (fid))
+#define   AN8855_FID_PST_MASK(fid)	(AN8855_FID_PST << \
+						AN8855_FID_PST_SHIFT(fid))
+#define   AN8855_FID_PST_VAL(fid, val)	(FIELD_PREP(AN8855_FID_PST, (val)) << \
+						AN8855_FID_PST_SHIFT(fid))
+
+enum an8855_stp_state {
+	AN8855_STP_DISABLED = 0,
+	AN8855_STP_BLOCKING = 1,
+	AN8855_STP_LISTENING = AN8855_STP_BLOCKING,
+	AN8855_STP_LEARNING = 2,
+	AN8855_STP_FORWARDING = 3
+};
+
+/* Register for port control */
+#define AN8855_PCR			0x10208004
+#define AN8855_PCR_P(x)			(AN8855_PCR + ((x) * 0x200))
+#define   AN8855_EG_TAG			GENMASK(29, 28)
+#define   AN8855_PORT_PRI		GENMASK(26, 24)
+#define   AN8855_PORT_TX_MIR		BIT(20)
+#define   AN8855_PORT_RX_MIR		BIT(16)
+#define   AN8855_PORT_VLAN		GENMASK(1, 0)
+
+enum an8855_port_mode {
+	/* Port Matrix Mode: Frames are forwarded by the PCR_MATRIX members. */
+	AN8855_PORT_MATRIX_MODE = 0,
+
+	/* Fallback Mode: Forward received frames with ingress ports that do
+	 * not belong to the VLAN member. Frames whose VID is not listed on
+	 * the VLAN table are forwarded by the PCR_MATRIX members.
+	 */
+	AN8855_PORT_FALLBACK_MODE = 1,
+
+	/* Check Mode: Forward received frames whose ingress do not
+	 * belong to the VLAN member. Discard frames if VID ismiddes on the
+	 * VLAN table.
+	 */
+	AN8855_PORT_CHECK_MODE = 2,
+
+	/* Security Mode: Discard any frame due to ingress membership
+	 * violation or VID missed on the VLAN table.
+	 */
+	AN8855_PORT_SECURITY_MODE = 3,
+};
+
+/* Register for port security control */
+#define AN8855_PSC			0x1020800c
+#define AN8855_PSC_P(x)			(AN8855_PSC + ((x) * 0x200))
+#define   AN8855_SA_DIS			BIT(4)
+
+/* Register for port vlan control */
+#define AN8855_PVC			0x10208010
+#define AN8855_PVC_P(x)			(AN8855_PVC + ((x) * 0x200))
+#define   AN8855_PORT_SPEC_REPLACE_MODE	BIT(11)
+#define   AN8855_PVC_EG_TAG		GENMASK(10, 8)
+#define   AN8855_VLAN_ATTR		GENMASK(7, 6)
+#define   AN8855_PORT_SPEC_TAG		BIT(5)
+#define   AN8855_ACC_FRM		GENMASK(1, 0)
+
+enum an8855_vlan_port_eg_tag {
+	AN8855_VLAN_EG_DISABLED = 0,
+	AN8855_VLAN_EG_CONSISTENT = 1,
+	AN8855_VLAN_EG_UNTAGGED = 4,
+	AN8855_VLAN_EG_SWAP = 5,
+	AN8855_VLAN_EG_TAGGED = 6,
+	AN8855_VLAN_EG_STACK = 7,
+};
+
+enum an8855_vlan_port_attr {
+	AN8855_VLAN_USER = 0,
+	AN8855_VLAN_STACK = 1,
+	AN8855_VLAN_TRANSPARENT = 3,
+};
+
+enum an8855_vlan_port_acc_frm {
+	AN8855_VLAN_ACC_ALL = 0,
+	AN8855_VLAN_ACC_TAGGED = 1,
+	AN8855_VLAN_ACC_UNTAGGED = 2,
+};
+
+#define AN8855_PPBV1			0x10208014
+#define AN8855_PPBV1_P(x)		(AN8855_PPBV1 + ((x) * 0x200))
+#define   AN8855_PPBV_G0_PORT_VID	GENMASK(11, 0)
+
+#define AN8855_PORTMATRIX		0x10208044
+#define AN8855_PORTMATRIX_P(x)		(AN8855_PORTMATRIX + ((x) * 0x200))
+#define   AN8855_PORTMATRIX_MASK	GENMASK(5, 0)
+/* Port matrix without the CPU port that should never be removed */
+#define   AN8855_USER_PORTMATRIX	GENMASK(4, 0)
+
+/* Register for port PVID */
+#define AN8855_PVID			0x10208048
+#define AN8855_PVID_P(x)		(AN8855_PVID + ((x) * 0x200))
+#define   AN8855_G0_PORT_VID		GENMASK(11, 0)
+
+/* Register for port MAC control register */
+#define AN8855_PMCR_P(x)		(0x10210000 + ((x) * 0x200))
+#define   AN8855_PMCR_FORCE_MODE	BIT(31)
+#define   AN8855_PMCR_FORCE_SPEED	GENMASK(30, 28)
+#define   AN8855_PMCR_FORCE_SPEED_5000	FIELD_PREP_CONST(AN8855_PMCR_FORCE_SPEED, 0x4)
+#define   AN8855_PMCR_FORCE_SPEED_2500	FIELD_PREP_CONST(AN8855_PMCR_FORCE_SPEED, 0x3)
+#define   AN8855_PMCR_FORCE_SPEED_1000	FIELD_PREP_CONST(AN8855_PMCR_FORCE_SPEED, 0x2)
+#define   AN8855_PMCR_FORCE_SPEED_100	FIELD_PREP_CONST(AN8855_PMCR_FORCE_SPEED, 0x1)
+#define   AN8855_PMCR_FORCE_SPEED_10	FIELD_PREP_CONST(AN8855_PMCR_FORCE_SPEED, 0x0)
+#define   AN8855_PMCR_FORCE_FDX		BIT(25)
+#define   AN8855_PMCR_FORCE_LNK		BIT(24)
+#define   AN8855_PMCR_IFG_XMIT		GENMASK(21, 20)
+#define   AN8855_PMCR_EXT_PHY		BIT(19)
+#define   AN8855_PMCR_MAC_MODE		BIT(18)
+#define   AN8855_PMCR_TX_EN		BIT(16)
+#define   AN8855_PMCR_RX_EN		BIT(15)
+#define   AN8855_PMCR_BACKOFF_EN	BIT(12)
+#define   AN8855_PMCR_BACKPR_EN		BIT(11)
+#define   AN8855_PMCR_FORCE_EEE5G	BIT(9)
+#define   AN8855_PMCR_FORCE_EEE2P5G	BIT(8)
+#define   AN8855_PMCR_FORCE_EEE1G	BIT(7)
+#define   AN8855_PMCR_FORCE_EEE100	BIT(6)
+#define   AN8855_PMCR_RX_FC_EN		BIT(5)
+#define   AN8855_PMCR_TX_FC_EN		BIT(4)
+
+#define AN8855_PMSR_P(x)		(0x10210010 + (x) * 0x200)
+#define   AN8855_PMSR_SPEED		GENMASK(30, 28)
+#define   AN8855_PMSR_SPEED_5000	FIELD_PREP_CONST(AN8855_PMSR_SPEED, 0x4)
+#define   AN8855_PMSR_SPEED_2500	FIELD_PREP_CONST(AN8855_PMSR_SPEED, 0x3)
+#define   AN8855_PMSR_SPEED_1000	FIELD_PREP_CONST(AN8855_PMSR_SPEED, 0x2)
+#define   AN8855_PMSR_SPEED_100		FIELD_PREP_CONST(AN8855_PMSR_SPEED, 0x1)
+#define   AN8855_PMSR_SPEED_10		FIELD_PREP_CONST(AN8855_PMSR_SPEED, 0x0)
+#define   AN8855_PMSR_DPX		BIT(25)
+#define   AN8855_PMSR_LNK		BIT(24)
+#define   AN8855_PMSR_EEE1G		BIT(7)
+#define   AN8855_PMSR_EEE100M		BIT(6)
+#define   AN8855_PMSR_RX_FC		BIT(5)
+#define   AN8855_PMSR_TX_FC		BIT(4)
+
+#define AN8855_PMEEECR_P(x)		(0x10210004 + (x) * 0x200)
+#define   AN8855_LPI_MODE_EN		BIT(31)
+#define   AN8855_WAKEUP_TIME_2500	GENMASK(23, 16)
+#define   AN8855_WAKEUP_TIME_1000	GENMASK(15, 8)
+#define   AN8855_WAKEUP_TIME_100	GENMASK(7, 0)
+#define AN8855_PMEEECR2_P(x)		(0x10210008 + (x) * 0x200)
+#define   AN8855_WAKEUP_TIME_5000	GENMASK(7, 0)
+
+#define AN8855_GMACCR			0x10213e00
+#define   AN8855_MAX_RX_JUMBO		GENMASK(7, 4)
+/* 2K for 0x0, 0x1, 0x2 */
+#define   AN8855_MAX_RX_JUMBO_2K	FIELD_PREP_CONST(AN8855_MAX_RX_JUMBO, 0x0)
+#define   AN8855_MAX_RX_JUMBO_3K	FIELD_PREP_CONST(AN8855_MAX_RX_JUMBO, 0x3)
+#define   AN8855_MAX_RX_JUMBO_4K	FIELD_PREP_CONST(AN8855_MAX_RX_JUMBO, 0x4)
+#define   AN8855_MAX_RX_JUMBO_5K	FIELD_PREP_CONST(AN8855_MAX_RX_JUMBO, 0x5)
+#define   AN8855_MAX_RX_JUMBO_6K	FIELD_PREP_CONST(AN8855_MAX_RX_JUMBO, 0x6)
+#define   AN8855_MAX_RX_JUMBO_7K	FIELD_PREP_CONST(AN8855_MAX_RX_JUMBO, 0x7)
+#define   AN8855_MAX_RX_JUMBO_8K	FIELD_PREP_CONST(AN8855_MAX_RX_JUMBO, 0x8)
+#define   AN8855_MAX_RX_JUMBO_9K	FIELD_PREP_CONST(AN8855_MAX_RX_JUMBO, 0x9)
+#define   AN8855_MAX_RX_JUMBO_12K	FIELD_PREP_CONST(AN8855_MAX_RX_JUMBO, 0xa)
+#define   AN8855_MAX_RX_JUMBO_15K	FIELD_PREP_CONST(AN8855_MAX_RX_JUMBO, 0xb)
+#define   AN8855_MAX_RX_JUMBO_16K	FIELD_PREP_CONST(AN8855_MAX_RX_JUMBO, 0xc)
+#define   AN8855_MAX_RX_PKT_LEN		GENMASK(1, 0)
+#define   AN8855_MAX_RX_PKT_1518_1522	FIELD_PREP_CONST(AN8855_MAX_RX_PKT_LEN, 0x0)
+#define   AN8855_MAX_RX_PKT_1536	FIELD_PREP_CONST(AN8855_MAX_RX_PKT_LEN, 0x1)
+#define   AN8855_MAX_RX_PKT_1552	FIELD_PREP_CONST(AN8855_MAX_RX_PKT_LEN, 0x2)
+#define   AN8855_MAX_RX_PKT_JUMBO	FIELD_PREP_CONST(AN8855_MAX_RX_PKT_LEN, 0x3)
+
+#define AN8855_CKGCR			0x10213e1c
+#define   AN8855_LPI_TXIDLE_THD_MASK	GENMASK(31, 14)
+#define   AN8855_CKG_LNKDN_PORT_STOP	BIT(1)
+#define   AN8855_CKG_LNKDN_GLB_STOP	BIT(0)
+
+/* Register for MIB */
+#define AN8855_MIB_COUNTER		0x10214000
+#define AN8855_PORT_MIB_COUNTER(x)	(AN8855_MIB_COUNTER + (x) * 0x200)
+/* Each define is an offset of AN8855_PORT_MIB_COUNTER */
+#define   AN8855_PORT_MIB_TX_DROP	(AN8855_MIB_COUNTER + 0x00)
+#define   AN8855_PORT_MIB_TX_CRC_ERR	(AN8855_MIB_COUNTER + 0x04)
+#define   AN8855_PORT_MIB_TX_UNICAST	(AN8855_MIB_COUNTER + 0x08)
+#define   AN8855_PORT_MIB_TX_MULTICAST	(AN8855_MIB_COUNTER + 0x0c)
+#define   AN8855_PORT_MIB_TX_BROADCAST	(AN8855_MIB_COUNTER + 0x10)
+#define   AN8855_PORT_MIB_TX_COLLISION	(AN8855_MIB_COUNTER + 0x14)
+#define   AN8855_PORT_MIB_TX_SINGLE_COLLISION (AN8855_MIB_COUNTER + 0x18)
+#define   AN8855_PORT_MIB_TX_MULTIPLE_COLLISION (AN8855_MIB_COUNTER + 0x1c)
+#define   AN8855_PORT_MIB_TX_DEFERRED	(AN8855_MIB_COUNTER + 0x20)
+#define   AN8855_PORT_MIB_TX_LATE_COLLISION (AN8855_MIB_COUNTER + 0x24)
+#define   AN8855_PORT_MIB_TX_EXCESSIVE_COLLISION (AN8855_MIB_COUNTER + 0x28)
+#define   AN8855_PORT_MIB_TX_PAUSE	(AN8855_MIB_COUNTER + 0x2c)
+#define   AN8855_PORT_MIB_TX_PKT_SZ_64	(AN8855_MIB_COUNTER + 0x30)
+#define   AN8855_PORT_MIB_TX_PKT_SZ_65_TO_127 (AN8855_MIB_COUNTER + 0x34)
+#define   AN8855_PORT_MIB_TX_PKT_SZ_128_TO_255 (AN8855_MIB_COUNTER + 0x38)
+#define   AN8855_PORT_MIB_TX_PKT_SZ_256_TO_511 (AN8855_MIB_COUNTER + 0x3c)
+#define   AN8855_PORT_MIB_TX_PKT_SZ_512_TO_1023 (AN8855_MIB_COUNTER + 0x40)
+#define   AN8855_PORT_MIB_TX_PKT_SZ_1024_TO_1518 (AN8855_MIB_COUNTER + 0x44)
+#define   AN8855_PORT_MIB_TX_PKT_SZ_1519_TO_MAX (AN8855_MIB_COUNTER + 0x48)
+#define   AN8855_PORT_MIB_TX_BYTES_LOW	(AN8855_MIB_COUNTER + 0x4c) /* 64 bytes */
+#define   AN8855_PORT_MIB_TX_BYTES_HIGH	(AN8855_MIB_COUNTER + 0x50)
+#define   AN8855_PORT_MIB_TX_OVERSIZE_DROP (AN8855_MIB_COUNTER + 0x54)
+#define   AN8855_PORT_MIB_TX_BAD_PKT_BYTES_LOW (AN8855_MIB_COUNTER + 0x58) /* 64 bytes */
+#define   AN8855_PORT_MIB_TX_BAD_PKT_BYTES_HIGH (AN8855_MIB_COUNTER + 0x5c)
+#define   AN8855_PORT_MIB_RX_DROP	(AN8855_MIB_COUNTER + 0x80)
+#define   AN8855_PORT_MIB_RX_FILTERING	(AN8855_MIB_COUNTER + 0x84)
+#define   AN8855_PORT_MIB_RX_UNICAST	(AN8855_MIB_COUNTER + 0x88)
+#define   AN8855_PORT_MIB_RX_MULTICAST	(AN8855_MIB_COUNTER + 0x8c)
+#define   AN8855_PORT_MIB_RX_BROADCAST	(AN8855_MIB_COUNTER + 0x90)
+#define   AN8855_PORT_MIB_RX_ALIGN_ERR	(AN8855_MIB_COUNTER + 0x94)
+#define   AN8855_PORT_MIB_RX_CRC_ERR	(AN8855_MIB_COUNTER + 0x98)
+#define   AN8855_PORT_MIB_RX_UNDER_SIZE_ERR (AN8855_MIB_COUNTER + 0x9c)
+#define   AN8855_PORT_MIB_RX_FRAG_ERR	(AN8855_MIB_COUNTER + 0xa0)
+#define   AN8855_PORT_MIB_RX_OVER_SZ_ERR (AN8855_MIB_COUNTER + 0xa4)
+#define   AN8855_PORT_MIB_RX_JABBER_ERR	(AN8855_MIB_COUNTER + 0xa8)
+#define   AN8855_PORT_MIB_RX_PAUSE	(AN8855_MIB_COUNTER + 0xac)
+#define   AN8855_PORT_MIB_RX_PKT_SZ_64	(AN8855_MIB_COUNTER + 0xb0)
+#define   AN8855_PORT_MIB_RX_PKT_SZ_65_TO_127 (AN8855_MIB_COUNTER + 0xb4)
+#define   AN8855_PORT_MIB_RX_PKT_SZ_128_TO_255 (AN8855_MIB_COUNTER + 0xb8)
+#define   AN8855_PORT_MIB_RX_PKT_SZ_256_TO_511 (AN8855_MIB_COUNTER + 0xbc)
+#define   AN8855_PORT_MIB_RX_PKT_SZ_512_TO_1023 (AN8855_MIB_COUNTER + 0xc0)
+#define   AN8855_PORT_MIB_RX_PKT_SZ_1024_TO_1518 (AN8855_MIB_COUNTER + 0xc4)
+#define   AN8855_PORT_MIB_RX_PKT_SZ_1519_TO_MAX (AN8855_MIB_COUNTER + 0xc8)
+#define   AN8855_PORT_MIB_RX_BYTES_LOW	(AN8855_MIB_COUNTER + 0xcc) /* 64 bytes */
+#define   AN8855_PORT_MIB_RX_BYTES_HIGH	(AN8855_MIB_COUNTER + 0xd0)
+#define   AN8855_PORT_MIB_RX_CTRL_DROP	(AN8855_MIB_COUNTER + 0xd4)
+#define   AN8855_PORT_MIB_RX_INGRESS_DROP (AN8855_MIB_COUNTER + 0xd8)
+#define   AN8855_PORT_MIB_RX_ARL_DROP	(AN8855_MIB_COUNTER + 0xdc)
+#define   AN8855_PORT_MIB_FLOW_CONTROL_DROP (AN8855_MIB_COUNTER + 0xe0)
+#define   AN8855_PORT_MIB_WRED_DROP	(AN8855_MIB_COUNTER + 0xe4)
+#define   AN8855_PORT_MIB_MIRROR_DROP	(AN8855_MIB_COUNTER + 0xe8)
+#define   AN8855_PORT_MIB_RX_BAD_PKT_BYTES_LOW (AN8855_MIB_COUNTER + 0xec) /* 64 bytes */
+#define   AN8855_PORT_MIB_RX_BAD_PKT_BYTES_HIGH (AN8855_MIB_COUNTER + 0xf0)
+#define   AN8855_PORT_MIB_RXS_FLOW_SAMPLING_PKT_DROP (AN8855_MIB_COUNTER + 0xf4)
+#define   AN8855_PORT_MIB_RXS_FLOW_TOTAL_PKT_DROP (AN8855_MIB_COUNTER + 0xf8)
+#define   AN8855_PORT_MIB_PORT_CONTROL_DROP (AN8855_MIB_COUNTER + 0xfc)
+#define AN8855_MIB_CCR			0x10213e30
+#define   AN8855_CCR_MIB_ENABLE		BIT(31)
+#define   AN8855_CCR_RX_OCT_CNT_GOOD	BIT(7)
+#define   AN8855_CCR_RX_OCT_CNT_BAD	BIT(6)
+#define   AN8855_CCR_TX_OCT_CNT_GOOD	BIT(5)
+#define   AN8855_CCR_TX_OCT_CNT_BAD	BIT(4)
+#define   AN8855_CCR_RX_OCT_CNT_GOOD_2	BIT(3)
+#define   AN8855_CCR_RX_OCT_CNT_BAD_2	BIT(2)
+#define   AN8855_CCR_TX_OCT_CNT_GOOD_2	BIT(1)
+#define   AN8855_CCR_TX_OCT_CNT_BAD_2	BIT(0)
+#define   AN8855_CCR_MIB_ACTIVATE	(AN8855_CCR_MIB_ENABLE | \
+					 AN8855_CCR_RX_OCT_CNT_GOOD | \
+					 AN8855_CCR_RX_OCT_CNT_BAD | \
+					 AN8855_CCR_TX_OCT_CNT_GOOD | \
+					 AN8855_CCR_TX_OCT_CNT_BAD | \
+					 AN8855_CCR_RX_OCT_CNT_BAD_2 | \
+					 AN8855_CCR_TX_OCT_CNT_BAD_2)
+#define AN8855_MIB_CLR			0x10213e34
+#define   AN8855_MIB_PORT6_CLR		BIT(6)
+#define   AN8855_MIB_PORT5_CLR		BIT(5)
+#define   AN8855_MIB_PORT4_CLR		BIT(4)
+#define   AN8855_MIB_PORT3_CLR		BIT(3)
+#define   AN8855_MIB_PORT2_CLR		BIT(2)
+#define   AN8855_MIB_PORT1_CLR		BIT(1)
+#define   AN8855_MIB_PORT0_CLR		BIT(0)
+
+/* HSGMII/SGMII Configuration register */
+/*	AN8855_HSGMII_AN_CSR_BASE	0x10220000 */
+#define AN8855_SGMII_REG_AN0		0x10220000
+/*        AN8855_SGMII_AN_ENABLE	BMCR_ANENABLE */
+/*        AN8855_SGMII_AN_RESTART	BMCR_ANRESTART */
+#define AN8855_SGMII_REG_AN_13		0x10220034
+#define   AN8855_SGMII_REMOTE_FAULT_DIS	BIT(8)
+#define   AN8855_SGMII_IF_MODE		GENMASK(5, 0)
+#define AN8855_SGMII_REG_AN_FORCE_CL37	0x10220060
+#define   AN8855_RG_FORCE_AN_DONE	BIT(0)
+
+/*	AN8855_HSGMII_CSR_PCS_BASE	0x10220000 */
+#define AN8855_RG_HSGMII_PCS_CTROL_1	0x10220a00
+#define   AN8855_RG_TBI_10B_MODE	BIT(30)
+#define AN8855_RG_AN_SGMII_MODE_FORCE	0x10220a24
+#define   AN8855_RG_FORCE_CUR_SGMII_MODE GENMASK(5, 4)
+#define   AN8855_RG_FORCE_CUR_SGMII_SEL	BIT(0)
+
+/*	AN8855_MULTI_SGMII_CSR_BASE	0x10224000 */
+#define AN8855_SGMII_STS_CTRL_0		0x10224018
+#define   AN8855_RG_LINK_MODE_P0	GENMASK(5, 4)
+#define   AN8855_RG_LINK_MODE_P0_SPEED_2500 FIELD_PREP_CONST(AN8855_RG_LINK_MODE_P0, 0x3)
+#define   AN8855_RG_LINK_MODE_P0_SPEED_1000 FIELD_PREP_CONST(AN8855_RG_LINK_MODE_P0, 0x2)
+#define   AN8855_RG_LINK_MODE_P0_SPEED_100 FIELD_PREP_CONST(AN8855_RG_LINK_MODE_P0, 0x1)
+#define   AN8855_RG_LINK_MODE_P0_SPEED_10 FIELD_PREP_CONST(AN8855_RG_LINK_MODE_P0, 0x0)
+#define   AN8855_RG_FORCE_SPD_MODE_P0	BIT(2)
+#define AN8855_MSG_RX_CTRL_0		0x10224100
+#define AN8855_MSG_RX_LIK_STS_0		0x10224514
+#define   AN8855_RG_DPX_STS_P3		BIT(24)
+#define   AN8855_RG_DPX_STS_P2		BIT(16)
+#define   AN8855_RG_EEE1G_STS_P1	BIT(12)
+#define   AN8855_RG_DPX_STS_P1		BIT(8)
+#define   AN8855_RG_TXFC_STS_P0		BIT(2)
+#define   AN8855_RG_RXFC_STS_P0		BIT(1)
+#define   AN8855_RG_DPX_STS_P0		BIT(0)
+#define AN8855_MSG_RX_LIK_STS_2		0x1022451c
+#define   AN8855_RG_RXFC_AN_BYPASS_P3	BIT(11)
+#define   AN8855_RG_RXFC_AN_BYPASS_P2	BIT(10)
+#define   AN8855_RG_RXFC_AN_BYPASS_P1	BIT(9)
+#define   AN8855_RG_TXFC_AN_BYPASS_P3	BIT(7)
+#define   AN8855_RG_TXFC_AN_BYPASS_P2	BIT(6)
+#define   AN8855_RG_TXFC_AN_BYPASS_P1	BIT(5)
+#define   AN8855_RG_DPX_AN_BYPASS_P3	BIT(3)
+#define   AN8855_RG_DPX_AN_BYPASS_P2	BIT(2)
+#define   AN8855_RG_DPX_AN_BYPASS_P1	BIT(1)
+#define   AN8855_RG_DPX_AN_BYPASS_P0	BIT(0)
+#define AN8855_PHY_RX_FORCE_CTRL_0	0x10224520
+#define   AN8855_RG_FORCE_TXC_SEL	BIT(4)
+
+/*	AN8855_XFI_CSR_PCS_BASE		0x10225000 */
+#define AN8855_RG_USXGMII_AN_CONTROL_0	0x10225bf8
+
+/*	AN8855_MULTI_PHY_RA_CSR_BASE	0x10226000 */
+#define AN8855_RG_RATE_ADAPT_CTRL_0	0x10226000
+#define   AN8855_RG_RATE_ADAPT_RX_BYPASS BIT(27)
+#define   AN8855_RG_RATE_ADAPT_TX_BYPASS BIT(26)
+#define   AN8855_RG_RATE_ADAPT_RX_EN	BIT(4)
+#define   AN8855_RG_RATE_ADAPT_TX_EN	BIT(0)
+#define AN8855_RATE_ADP_P0_CTRL_0	0x10226100
+#define   AN8855_RG_P0_DIS_MII_MODE	BIT(31)
+#define   AN8855_RG_P0_MII_MODE		BIT(28)
+#define   AN8855_RG_P0_MII_RA_RX_EN	BIT(3)
+#define   AN8855_RG_P0_MII_RA_TX_EN	BIT(2)
+#define   AN8855_RG_P0_MII_RA_RX_MODE	BIT(1)
+#define   AN8855_RG_P0_MII_RA_TX_MODE	BIT(0)
+#define AN8855_MII_RA_AN_ENABLE		0x10226300
+#define   AN8855_RG_P0_RA_AN_EN		BIT(0)
+
+/*	AN8855_QP_DIG_CSR_BASE		0x1022a000 */
+#define AN8855_QP_CK_RST_CTRL_4		0x1022a310
+#define AN8855_QP_DIG_MODE_CTRL_0	0x1022a324
+#define   AN8855_RG_SGMII_MODE		GENMASK(5, 4)
+#define   AN8855_RG_SGMII_AN_EN		BIT(0)
+#define AN8855_QP_DIG_MODE_CTRL_1	0x1022a330
+#define   AN8855_RG_TPHY_SPEED		GENMASK(3, 2)
+
+/*	AN8855_SERDES_WRAPPER_BASE	0x1022c000 */
+#define AN8855_USGMII_CTRL_0		0x1022c000
+
+/*	AN8855_QP_PMA_TOP_BASE		0x1022e000 */
+#define AN8855_PON_RXFEDIG_CTRL_0	0x1022e100
+#define   AN8855_RG_QP_EQ_RX500M_CK_SEL	BIT(12)
+#define AN8855_PON_RXFEDIG_CTRL_9	0x1022e124
+#define   AN8855_RG_QP_EQ_LEQOSC_DLYCNT	GENMASK(2, 0)
+
+#define AN8855_SS_LCPLL_PWCTL_SETTING_2	0x1022e208
+#define   AN8855_RG_NCPO_ANA_MSB	GENMASK(17, 16)
+#define AN8855_SS_LCPLL_TDC_FLT_2	0x1022e230
+#define   AN8855_RG_LCPLL_NCPO_VALUE	GENMASK(30, 0)
+#define AN8855_SS_LCPLL_TDC_FLT_5	0x1022e23c
+#define   AN8855_RG_LCPLL_NCPO_CHG	BIT(24)
+#define AN8855_SS_LCPLL_TDC_PCW_1	0x1022e248
+#define  AN8855_RG_LCPLL_PON_HRDDS_PCW_NCPO_GPON GENMASK(30, 0)
+#define AN8855_INTF_CTRL_8		0x1022e320
+#define AN8855_INTF_CTRL_9		0x1022e324
+#define AN8855_INTF_CTRL_10		0x1022e328
+#define   AN8855_RG_DA_QP_TX_FIR_C2_SEL	BIT(29)
+#define   AN8855_RG_DA_QP_TX_FIR_C2_FORCE GENMASK(28, 24)
+#define   AN8855_RG_DA_QP_TX_FIR_C1_SEL	BIT(21)
+#define   AN8855_RG_DA_QP_TX_FIR_C1_FORCE GENMASK(20, 16)
+#define AN8855_INTF_CTRL_11		0x1022e32c
+#define   AN8855_RG_DA_QP_TX_FIR_C0B_SEL BIT(6)
+#define   AN8855_RG_DA_QP_TX_FIR_C0B_FORCE GENMASK(5, 0)
+#define AN8855_PLL_CTRL_0		0x1022e400
+#define   AN8855_RG_PHYA_AUTO_INIT	BIT(0)
+#define AN8855_PLL_CTRL_2		0x1022e408
+#define   AN8855_RG_DA_QP_PLL_SDM_IFM_INTF BIT(30)
+#define   AN8855_RG_DA_QP_PLL_RICO_SEL_INTF BIT(29)
+#define   AN8855_RG_DA_QP_PLL_POSTDIV_EN_INTF BIT(28)
+#define   AN8855_RG_DA_QP_PLL_PHY_CK_EN_INTF BIT(27)
+#define   AN8855_RG_DA_QP_PLL_PFD_OFFSET_EN_INTRF BIT(26)
+#define   AN8855_RG_DA_QP_PLL_PFD_OFFSET_INTF GENMASK(25, 24)
+#define   AN8855_RG_DA_QP_PLL_PCK_SEL_INTF BIT(22)
+#define   AN8855_RG_DA_QP_PLL_KBAND_PREDIV_INTF GENMASK(21, 20)
+#define   AN8855_RG_DA_QP_PLL_IR_INTF	GENMASK(19, 16)
+#define   AN8855_RG_DA_QP_PLL_ICOIQ_EN_INTF BIT(14)
+#define   AN8855_RG_DA_QP_PLL_FBKSEL_INTF GENMASK(13, 12)
+#define   AN8855_RG_DA_QP_PLL_BR_INTF	GENMASK(10, 8)
+#define   AN8855_RG_DA_QP_PLL_BPD_INTF	GENMASK(7, 6)
+#define   AN8855_RG_DA_QP_PLL_BPA_INTF	GENMASK(4, 2)
+#define   AN8855_RG_DA_QP_PLL_BC_INTF	GENMASK(1, 0)
+#define AN8855_PLL_CTRL_3		0x1022e40c
+#define   AN8855_RG_DA_QP_PLL_SSC_PERIOD_INTF GENMASK(31, 16)
+#define   AN8855_RG_DA_QP_PLL_SSC_DELTA_INTF GENMASK(15, 0)
+#define AN8855_PLL_CTRL_4		0x1022e410
+#define   AN8855_RG_DA_QP_PLL_SDM_HREN_INTF GENMASK(4, 3)
+#define   AN8855_RG_DA_QP_PLL_ICOLP_EN_INTF BIT(2)
+#define   AN8855_RG_DA_QP_PLL_SSC_DIR_DLY_INTF GENMASK(1, 0)
+#define AN8855_PLL_CK_CTRL_0		0x1022e414
+#define   AN8855_RG_DA_QP_PLL_TDC_TXCK_SEL_INTF BIT(9)
+#define   AN8855_RG_DA_QP_PLL_SDM_DI_EN_INTF BIT(8)
+#define AN8855_RX_DLY_0			0x1022e614
+#define   AN8855_RG_QP_RX_SAOSC_EN_H_DLY GENMASK(13, 8)
+#define   AN8855_RG_QP_RX_PI_CAL_EN_H_DLY GENMASK(7, 0)
+#define AN8855_RX_CTRL_2		0x1022e630
+#define   AN8855_RG_QP_RX_EQ_EN_H_DLY	GENMASK(28, 16)
+#define AN8855_RX_CTRL_5		0x1022e63c
+#define   AN8855_RG_FREDET_CHK_CYCLE	GENMASK(29, 10)
+#define AN8855_RX_CTRL_6		0x1022e640
+#define   AN8855_RG_FREDET_GOLDEN_CYCLE	GENMASK(19, 0)
+#define AN8855_RX_CTRL_7		0x1022e644
+#define   AN8855_RG_FREDET_TOLERATE_CYCLE GENMASK(19, 0)
+#define AN8855_RX_CTRL_8		0x1022e648
+#define   AN8855_RG_DA_QP_SAOSC_DONE_TIME GENMASK(27, 16)
+#define   AN8855_RG_DA_QP_LEQOS_EN_TIME	GENMASK(14, 0)
+#define AN8855_RX_CTRL_26		0x1022e690
+#define   AN8855_RG_QP_EQ_RETRAIN_ONLY_EN BIT(26)
+#define   AN8855_RG_LINK_NE_EN		BIT(24)
+#define   AN8855_RG_LINK_ERRO_EN	BIT(23)
+#define AN8855_RX_CTRL_42		0x1022e6d0
+#define   AN8855_RG_QP_EQ_EN_DLY	GENMASK(12, 0)
+
+/*	AN8855_QP_ANA_CSR_BASE		0x1022f000 */
+#define AN8855_RG_QP_RX_DAC_EN		0x1022f000
+#define   AN8855_RG_QP_SIGDET_HF	GENMASK(17, 16)
+#define AN8855_RG_QP_RXAFE_RESERVE	0x1022f004
+#define   AN8855_RG_QP_CDR_PD_10B_EN	BIT(11)
+#define AN8855_RG_QP_CDR_LPF_BOT_LIM	0x1022f008
+#define   AN8855_RG_QP_CDR_LPF_KP_GAIN	GENMASK(26, 24)
+#define   AN8855_RG_QP_CDR_LPF_KI_GAIN	GENMASK(22, 20)
+#define AN8855_RG_QP_CDR_LPF_MJV_LIM	0x1022f00c
+#define   AN8855_RG_QP_CDR_LPF_RATIO	GENMASK(5, 4)
+#define AN8855_RG_QP_CDR_LPF_SETVALUE	0x1022f014
+#define   AN8855_RG_QP_CDR_PR_BUF_IN_SR	GENMASK(31, 29)
+#define   AN8855_RG_QP_CDR_PR_BETA_SEL	GENMASK(28, 25)
+#define AN8855_RG_QP_CDR_PR_CKREF_DIV1	0x1022f018
+#define   AN8855_RG_QP_CDR_PR_KBAND_DIV	GENMASK(26, 24)
+#define   AN8855_RG_QP_CDR_PR_DAC_BAND	GENMASK(12, 8)
+#define AN8855_RG_QP_CDR_PR_KBAND_DIV_PCIE 0x1022f01c
+#define   AN8855_RG_QP_CDR_PR_XFICK_EN	BIT(30)
+#define   AN8855_RG_QP_CDR_PR_KBAND_PCIE_MODE BIT(6)
+#define   AN8855_RG_QP_CDR_PR_KBAND_DIV_PCIE_MASK GENMASK(5, 0)
+#define AN8855_RG_QP_CDR_FORCE_IBANDLPF_R_OFF 0x1022f020
+#define   AN8855_RG_QP_CDR_PHYCK_SEL	GENMASK(17, 16)
+#define   AN8855_RG_QP_CDR_PHYCK_RSTB	BIT(13)
+#define   AN8855_RG_QP_CDR_PHYCK_DIV	GENMASK(12, 6)
+#define AN8855_RG_QP_TX_MODE		0x1022f028
+#define   AN8855_RG_QP_TX_RESERVE	GENMASK(31, 16)
+#define   AN8855_RG_QP_TX_MODE_16B_EN	BIT(0)
+#define AN8855_RG_QP_PLL_IPLL_DIG_PWR_SEL 0x1022f03c
+#define AN8855_RG_QP_PLL_SDM_ORD	0x1022f040
+#define   AN8855_RG_QP_PLL_SSC_PHASE_INI BIT(4)
+#define   AN8855_RG_QP_PLL_SSC_TRI_EN	BIT(3)
+
+/*	AN8855_ETHER_SYS_BASE		0x1028c800 */
+#define AN8855_RG_GPHY_AFE_PWD		0x1028c840
+#define AN8855_RG_GPHY_SMI_ADDR		0x1028c848
+
+struct an8855_priv {
+	struct dsa_switch *ds;
+	struct regmap *regmap;
+	/* Protect ATU or VLAN table access */
+	struct mutex reg_mutex;
+
+	struct phylink_pcs pcs;
+
+	struct mt7530_port ports[AN8855_NUM_PORTS];
+	u32 tx_lpi_timer_ports[AN8855_NUM_PORTS];
+
+	struct mt7530_lib_priv lib_priv;
+};
+
+#endif /* __AN8855_H */
diff --git a/drivers/net/dsa/mt7530-lib.c b/drivers/net/dsa/mt7530-lib.c
index 098dd45d3ee9..cf474faf8ed6 100644
--- a/drivers/net/dsa/mt7530-lib.c
+++ b/drivers/net/dsa/mt7530-lib.c
@@ -423,9 +423,11 @@ int mt7530_lib_fdb_cmd(struct mt7530_lib_priv *priv, enum mt7530_fdb_cmd cmd,
 		return ret;
 	}
 
-	regmap_field_read(priv->fields[MT7530_ATC_INVALID], &val);
-	if (cmd == MT7530_FDB_READ && val)
-		return -EINVAL;
+	if (priv->fields[MT7530_ATC_INVALID]) {
+		regmap_field_read(priv->fields[MT7530_ATC_INVALID], &val);
+		if (cmd == MT7530_FDB_READ && val)
+			return -EINVAL;
+	}
 
 	if (rsp)
 		regmap_field_read(priv->fields[__MT7530_ATC], rsp);
@@ -442,6 +444,8 @@ static void mt7530_lib_fdb_write(struct mt7530_lib_priv *priv, u16 vid,
 	regmap_field_write(priv->fields[__MT7530_ATWD1], 0);
 	regmap_field_write(priv->fields[__MT7530_ATWD2], 0);
 	regmap_field_write(priv->fields[__MT7530_ATWD3], 0);
+	if (priv->fields[__MT7530_ATWD4])
+		regmap_field_write(priv->fields[__MT7530_ATWD4], 0);
 
 	regmap_field_write(priv->fields[MT7530_ATWD_CVID], vid);
 	regmap_field_write(priv->fields[MT7530_ATWD_IVL], 1);
@@ -452,7 +456,17 @@ static void mt7530_lib_fdb_write(struct mt7530_lib_priv *priv, u16 vid,
 	 * be aged out and STATIC_EMP specified as erasing an
 	 * entry
 	 */
-	regmap_field_write(priv->fields[MT7530_ATWD_ENT_STATUS], type);
+	if (priv->fields[MT7530_ATWD_ENT_STATUS])
+		regmap_field_write(priv->fields[MT7530_ATWD_ENT_STATUS], type);
+	if (priv->fields[AN8855_ATWD_TYPE]) {
+		/* Default to static entry (0) */
+		regmap_field_write(priv->fields[AN8855_ATWD_TYPE], 0);
+	}
+	if (priv->fields[AN8855_ATWD_VLD]) {
+		/* Load entry if STATIC_ENT */
+		regmap_field_write(priv->fields[AN8855_ATWD_VLD],
+				   type == STATIC_ENT);
+	}
 	regmap_field_write(priv->fields[MT7530_ATWD_MAC_BYTE_5], mac[5]);
 	regmap_field_write(priv->fields[MT7530_ATWD_MAC_BYTE_4], mac[4]);
 	regmap_field_write(priv->fields[MT7530_ATWD_MAC_BYTE_3], mac[3]);
@@ -483,8 +497,14 @@ void mt7530_lib_fdb_read(struct mt7530_lib_priv *priv, struct mt7530_fdb *fdb)
 	fdb->mac[1] = val;
 	regmap_field_read(priv->fields[MT7530_ATRD_MAC_BYTE_0], &val);
 	fdb->mac[0] = val;
-	regmap_field_read(priv->fields[MT7530_ATRD_ENT_STATUS], &val);
-	fdb->noarp = val == STATIC_ENT;
+	if (priv->fields[MT7530_ATWD_ENT_STATUS]) {
+		regmap_field_read(priv->fields[MT7530_ATRD_ENT_STATUS], &val);
+		fdb->noarp = val == STATIC_ENT;
+	}
+	if (priv->fields[AN8855_ATRD_ARP]) {
+		regmap_field_read(priv->fields[AN8855_ATRD_ARP], &val);
+		fdb->noarp = !!val;
+	}
 }
 EXPORT_SYMBOL_GPL(mt7530_lib_fdb_read);
 
@@ -787,6 +807,17 @@ void mt7530_lib_port_bridge_leave(struct mt7530_lib_priv *priv, int port,
 }
 EXPORT_SYMBOL_GPL(mt7530_lib_port_bridge_leave);
 
+void mt7530_port_set_pvid(struct mt7530_lib_priv *priv, int port,
+			  u16 pvid)
+{
+	regmap_fields_write(priv->fields[MT7530_PPBV1_G0_PORT_VID],
+			    port, pvid);
+	if (priv->fields[AN8855_PVID_G0_PORT_VID])
+		regmap_fields_write(priv->fields[AN8855_PVID_G0_PORT_VID],
+				    port, pvid);
+}
+EXPORT_SYMBOL_GPL(mt7530_port_set_pvid);
+
 static void mt7530_port_set_vlan_unaware(struct mt7530_lib_priv *priv, int port)
 {
 	struct dsa_switch *ds = priv->ds;
@@ -807,8 +838,7 @@ static void mt7530_port_set_vlan_unaware(struct mt7530_lib_priv *priv, int port)
 	regmap_fields_write(priv->fields[MT7530_PVC_ACC_FRM],
 			    port, MT7530_VLAN_ACC_ALL);
 
-	regmap_fields_write(priv->fields[MT7530_PPBV1_G0_PORT_VID],
-			    port, G0_PORT_VID_DEF);
+	mt7530_port_set_pvid(priv, port, G0_PORT_VID_DEF);
 
 	for (i = 0; i < priv->ds->num_ports; i++) {
 		if (i == port)
@@ -840,8 +870,7 @@ static void mt7530_port_set_vlan_aware(struct mt7530_lib_priv *priv, int port)
 	if (dsa_is_user_port(ds, port)) {
 		regmap_fields_write(priv->fields[MT7530_PCR_PORT_VLAN],
 				    port, MT7530_PORT_SECURITY_MODE);
-		regmap_fields_write(priv->fields[MT7530_PPBV1_G0_PORT_VID],
-				    port, priv->ports[port].pvid);
+		mt7530_port_set_pvid(priv, port, priv->ports[port].pvid);
 
 		/* Only accept tagged frames if PVID is not set */
 		if (!priv->ports[port].pvid)
@@ -919,10 +948,12 @@ static int mt7530_vlan_cmd(struct mt7530_lib_priv *priv, enum mt7530_vlan_cmd cm
 		return ret;
 	}
 
-	regmap_field_read(priv->fields[MT7530_VTCR_INVALID], &val);
-	if (val) {
-		dev_err(priv->dev, "read VTCR invalid\n");
-		return -EINVAL;
+	if (priv->fields[MT7530_VTCR_INVALID]) {
+		regmap_field_read(priv->fields[MT7530_VTCR_INVALID], &val);
+		if (val) {
+			dev_err(priv->dev, "read VTCR invalid\n");
+			return -EINVAL;
+		}
 	}
 
 	return 0;
@@ -1044,8 +1075,7 @@ int mt7530_lib_port_vlan_add(struct mt7530_lib_priv *priv, int port,
 
 		/* Only configure PVID if VLAN filtering is enabled */
 		if (dsa_port_is_vlan_filtering(dsa_to_port(ds, port)))
-			regmap_fields_write(priv->fields[MT7530_PPBV1_G0_PORT_VID],
-					    port, vlan->vid);
+			mt7530_port_set_pvid(priv, port, vlan->vid);
 	} else if (vlan->vid && priv->ports[port].pvid == vlan->vid) {
 		/* This VLAN is overwritten without PVID, so unset it */
 		priv->ports[port].pvid = G0_PORT_VID_DEF;
@@ -1055,8 +1085,7 @@ int mt7530_lib_port_vlan_add(struct mt7530_lib_priv *priv, int port,
 			regmap_fields_write(priv->fields[MT7530_PVC_ACC_FRM],
 					    port, MT7530_VLAN_ACC_TAGGED);
 
-		regmap_fields_write(priv->fields[MT7530_PPBV1_G0_PORT_VID],
-				    port, G0_PORT_VID_DEF);
+		mt7530_port_set_pvid(priv, port, G0_PORT_VID_DEF);
 	}
 
 	mutex_unlock(priv->reg_mutex);
@@ -1093,8 +1122,7 @@ int mt7530_lib_port_vlan_del(struct mt7530_lib_priv *priv, int port,
 			regmap_fields_write(priv->fields[MT7530_PVC_ACC_FRM],
 					    port, MT7530_VLAN_ACC_TAGGED);
 
-		regmap_fields_write(priv->fields[MT7530_PPBV1_G0_PORT_VID],
-				    port, G0_PORT_VID_DEF);
+		mt7530_port_set_pvid(priv, port, G0_PORT_VID_DEF);
 	}
 
 	mutex_unlock(priv->reg_mutex);
diff --git a/drivers/net/dsa/mt7530-lib.h b/drivers/net/dsa/mt7530-lib.h
index da2ee781f7e6..1465eb49f4cb 100644
--- a/drivers/net/dsa/mt7530-lib.h
+++ b/drivers/net/dsa/mt7530-lib.h
@@ -159,6 +159,8 @@ enum mt7530_regmap_field {
 	MT7530_ATWD_AGE_TIMER,
 	MT7530_ATWD_PORT_MAP,
 	MT7530_ATWD_ENT_STATUS,
+	AN8855_ATWD_TYPE,
+	AN8855_ATWD_VLD,
 	MT7530_ATWD_MAC_BYTE_5,
 	MT7530_ATWD_MAC_BYTE_4,
 	MT7530_ATWD_MAC_BYTE_3,
@@ -169,11 +171,13 @@ enum mt7530_regmap_field {
 	__MT7530_ATWD1,
 	__MT7530_ATWD2,
 	__MT7530_ATWD3,
+	__MT7530_ATWD4,
 
 	MT7530_ATRD_CVID,
 	MT7530_ATRD_AGE_TIMER,
 	MT7530_ATRD_PORT_MAP,
 	MT7530_ATRD_ENT_STATUS,
+	AN8855_ATRD_ARP,
 	MT7530_ATRD_MAC_BYTE_5,
 	MT7530_ATRD_MAC_BYTE_4,
 	MT7530_ATRD_MAC_BYTE_3,
@@ -201,6 +205,7 @@ enum mt7530_regmap_field {
 	MT7530_PVC_ACC_FRM,
 
 	MT7530_PPBV1_G0_PORT_VID,
+	AN8855_PVID_G0_PORT_VID,
 
 	MT7530_GMACCR_MAX_RX_JUMBO,
 	MT7530_GMACCR_MAX_RX_PKT_LEN,
@@ -223,8 +228,13 @@ enum mt7530_regmap_field {
 	MT7530_MIB_TX_PKT_SZ_256_TO_511,
 	MT7530_MIB_TX_PKT_SZ_512_TO_1023,
 	MT7530_MIB_TX_PKT_SZ_1024_TO_MAX,
+	AN8855_MIB_TX_PKT_SZ_1024_TO_1518,
+	AN8855_MIB_TX_PKT_SZ_1519_TO_MAX,
 	MT7530_MIB_TX_BYTES_LOW,
 	MT7530_MIB_TX_BYTES_HIGH,
+	AN8855_MIB_TX_OVERSIZE_DROP,
+	AN8855_MIB_TX_BAD_PKT_BYTES_LOW,
+	AN8855_MIB_TX_BAD_PKT_BYTES_HIGH,
 	MT7530_MIB_RX_DROP,
 	MT7530_MIB_RX_FILTERING,
 	MT7530_MIB_RX_UNICAST,
@@ -243,11 +253,21 @@ enum mt7530_regmap_field {
 	MT7530_MIB_RX_PKT_SZ_256_TO_511,
 	MT7530_MIB_RX_PKT_SZ_512_TO_1023,
 	MT7530_MIB_RX_PKT_SZ_1024_TO_MAX,
+	AN8855_MIB_RX_PKT_SZ_1024_TO_1518,
+	AN8855_MIB_RX_PKT_SZ_1519_TO_MAX,
 	MT7530_MIB_RX_BYTES_LOW,
 	MT7530_MIB_RX_BYTES_HIGH,
 	MT7530_MIB_RX_CTRL_DROP,
 	MT7530_MIB_RX_INGRESS_DROP,
 	MT7530_MIB_RX_ARL_DROP,
+	AN8855_MIB_FLOW_CONTROL_DROP,
+	AN8855_MIB_WRED_DROP,
+	AN8855_MIB_MIRROR_DROP,
+	AN8855_MIB_RX_BAD_PKT_BYTES_LOW,
+	AN8855_MIB_RX_BAD_PKT_BYTES_HIGH,
+	AN8855_MIB_RXS_FLOW_SAMPLING_PKT_DROP,
+	AN8855_MIB_RXS_FLOW_TOTAL_PKT_DROP,
+	AN8855_MIB_PORT_CONTROL_DROP,
 
 	MT7530_FIELD_MAX,
 };
@@ -385,6 +405,8 @@ int mt7530_lib_port_vlan_add(struct mt7530_lib_priv *priv, int port,
 int mt7530_lib_port_vlan_del(struct mt7530_lib_priv *priv, int port,
 			     const struct switchdev_obj_port_vlan *vlan);
 
+void mt7530_port_set_pvid(struct mt7530_lib_priv *priv, int port,
+			  u16 pvid);
 int mt7530_lib_setup_vlan0(struct mt7530_lib_priv *priv);
 
 #endif /* __MT7530_LIB_H */
-- 
2.55.0

Re: [PATCH net-next v23 9/9] net: dsa: Add Airoha AN8855 5-Port Gigabit DSA Switch driver

[Andrew Lunn]

On Fri, Sep 25, 2026 at 08:24:31PM +0200, Christian Marangi wrote:
> Add Airoha AN8855 5-Port Gigabit DSA switch. Switch can support
> 10M, 100M, 1Gb, 2.5G and 5G Ethernet Speed but 5G is currently error out
> as it's not currently supported as requires additional configuration for
> the PCS.
> 
> Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>

Reviewed-by: Andrew Lunn <andrew@lunn.ch>

    Andrew

Re: [PATCH net-next v23 9/9] net: dsa: Add Airoha AN8855 5-Port Gigabit DSA Switch driver

[netdev-bot+sashiko]

Thank you for your contribution! Sashiko AI review found 15 potential
issue(s) to consider.

Critical: 0 · High: 3 · Medium: 6 · Low: 6

If you believe none of the issues are legitimate, please reply to each
issue of Medium severity or higher and explain why the AI is wrong.
If any of them are legitimate and you plan to respin, please let patchwork
know by including "pw-bot: cr" as a separate line at the end of your reply
(one such reply per series is enough).

- [High] The AN8855 port_enable/port_disable callbacks never write the
  hardware port matrix.
- [High] On AN8855, the shared VLAN read-modify-write path reads back
  from the write-data register instead of the read register.
- [High] net: dsa: NULL deref in mt7530_lib_fdb_read() due to mismatched
  field check
- [Medium] The jumbo frame length encoding is wrong for AN8855.
- [Medium] an8855_set_mac_eee() rejects any tx_lpi_timer > 0xFFF (4095
  us).
- [Medium] The link-local trap fields for AN8855 point at the wrong bits.
- [Medium] an8855_pcs_config() updates AN8855_RG_DA_QP_PLL_SDM_HREN_INTF,
  which the header defines as a PLL_CTRL_4 field (GENMASK(4,3)), but…
- [Medium] SGMII without in-band negotiation always forces the PCS to
  1000 Mb/s.
- [Medium] The new AN8855 driver adds private `ethtool -S` strings for
  counters that already have standard uAPIs.
- [Low] The COMPILE_TEST dependency lets NET_DSA_AN8855 be built with
  MFD_AIROHA_AN8855=n, but neither NET_DSA_AN8855 nor NET_DSA_MT7530_LIB…
- [Low] an8855_phylink_mac_link_up() ignores the return value of
  regmap_read(AN8855_PMCR_P(port), &reg).
- [Low] In an8855_phylink_mac_enable_tx_lpi(),
  priv->tx_lpi_timer_ports[port] is written only when a non-zero timer…
- [Low] an8855_port_fdb_dump() declares `u32 rsp` without initialising it
  and uses FIELD_GET(AN8855_ATC_HIT, rsp) after mt7530_lib_fdb_cmd()…
- [Low] an8855_pcs_config() does not restore the bits that belong to
  other modes, so the programmed PCS state depends on earlier…
- [Low] The last RMON histogram bucket is {1519, AN8855_MAX_MTU}, and
  AN8855_MAX_MTU is an L3 MTU (15360 - ETH_HLEN - ETH_FCS_LEN -…

--

net: dsa: Add Airoha AN8855 5-Port Gigabit DSA Switch driver

This adds a DSA driver for the switch inside the Airoha AN8855 chip. It
is built on the shared mt7530-lib helpers and has an in-driver PCS for
SGMII and 2500BASE-X on port 5. mt7530-lib gains optional AN8855
regmap fields (ATWD type/valid, ATRD ARP, PVID, extra MIB counters) and
a new mt7530_port_set_pvid() helper.

> diff --git a/drivers/net/dsa/Kconfig b/drivers/net/dsa/Kconfig
> index f13ac7e772002..1753578c8e037 100644
> --- a/drivers/net/dsa/Kconfig
> +++ b/drivers/net/dsa/Kconfig
> @@ -24,6 +24,16 @@ config NET_DSA_LOOP
>  	  This enables support for a fake mock-up switch chip which
>  	  exercises the DSA APIs.
>  
> +config NET_DSA_AN8855
> +	tristate "Airoha AN8855 Ethernet switch support"
> +	depends on MFD_AIROHA_AN8855 || COMPILE_TEST
> +	depends on NET_DSA
> +	select NET_DSA_MT7530_LIB
> +	select NET_DSA_TAG_AIROHA

[Severity: Low]
With COMPILE_TEST this symbol can be enabled while MFD_AIROHA_AN8855=n.
Neither NET_DSA_AN8855 nor NET_DSA_MT7530_LIB selects REGMAP, which is a
hidden symbol.

In include/linux/regmap.h, struct reg_field, REG_FIELD(), REG_FIELD_ID()
and devm_regmap_field_alloc() are only declared under #ifdef
CONFIG_REGMAP. mt7530-lib.h embeds the struct by value:

struct mt7530_reg_field {
	unsigned int id;
	const struct reg_field field;
};

Would a COMPILE_TEST randconfig with no other REGMAP selector fail to
build here? Should this select REGMAP?

> diff --git a/drivers/net/dsa/an8855.c b/drivers/net/dsa/an8855.c
> new file mode 100644
> index 0000000000000..428d7dd85dd80
> --- /dev/null
> +++ b/drivers/net/dsa/an8855.c
> @@ -0,0 +1,1740 @@

[ ... ]

> +static const struct mt7530_reg_field an8855_fields[] = {

[ ... ]

> +	{ MT7530_BPDU_EG_TAG, REG_FIELD(AN8855_BPC, 9, 11) },
> +	{ MT7530_BPDU_PORT_FW, REG_FIELD(AN8855_BPC, 0, 2) },
> +	{ MT7530_PAE_BPDU_FR, REG_FIELD(AN8855_PAC, 28, 28) },
> +	{ MT7530_PAE_EG_TAG, REG_FIELD(AN8855_PAC, 25, 27) },
> +	{ MT7530_PAE_PORT_FW, REG_FIELD(AN8855_PAC, 16, 18) },

[Severity: Medium]
Are these the intended PAC bits? an8855.h names bit 28, bits 27:25 and
bits 18:16 of AN8855_PAC as AN8855_TAG_PAE_BPDU_FR, AN8855_TAG_PAE_EG_TAG
and AN8855_TAG_PAE_PORT_FW. The plain PAE fields are defined elsewhere:

#define   AN8855_PAE_BPDU_FR		BIT(12)
#define   AN8855_PAE_EG_TAG		GENMASK(11, 9)
...
#define   AN8855_PAE_PORT_FW		GENMASK(2, 0)

mt7530_lib_trap_frames() never programs those fields. This looks like
the MT7530 layout carried over, since on MT7530 the PAE fields sit in
the upper half of BPC.

AN8855_BPC also has an AN8855_BPDU_BPDU_FR bit (BIT(12)), but no lib
field maps to it. So real BPDUs (01:80:C2:00:00:00) are never marked as
"regarded as BPDU", and the lib comment says only such frames bypass the
spanning-tree port state.

Depending on the AN8855 reset defaults, could EAPOL frames fail to reach
the CPU? Could BPDUs received on blocking or listening ports be dropped?

> +	{ MT7530_VAWD_IVL_MAC, REG_FIELD(AN8855_VAWD0, 5, 5) },
> +	{ MT7530_VAWD_EG_CON, REG_FIELD(AN8855_VAWD0, 11, 11) },
> +	{ MT7530_VAWD_VTAG_EN, REG_FIELD(AN8855_VAWD0, 10, 10) },
> +	{ MT7530_VAWD_PORT_MEM, REG_FIELD(AN8855_VAWD0, 26, 31) },
> +	{ MT7530_VAWD_FID, REG_FIELD(AN8855_VAWD0, 1, 4) },
> +	{ MT7530_VAWD_VLAN_VALID, REG_FIELD(AN8855_VAWD0, 0, 0) },
> +	{ __MT7530_VAWD1, REG_FIELD(AN8855_VAWD0, 0, 31) },
> +
> +	{ MT7530_VAWD_ETAG, REG_FIELD(AN8855_VAWD0, 12, 23) },
> +	{ __MT7530_VAWD2, REG_FIELD(AN8855_VAWD1, 0, 31) },

[Severity: High]
mt7530_hw_vlan_update() fetches an entry with RD_VID, then reads the
result through MT7530_VAWD_PORT_MEM:

	/* Fetch entry */
	mt7530_vlan_cmd(priv, MT7530_VTCR_RD_VID, vid);

	regmap_field_read(priv->fields[MT7530_VAWD_PORT_MEM], &val);
	entry->old_members = val;

Here every VAWD_* field points at AN8855_VAWD0, which is the write-data
register. an8855.h defines a separate read register, and no field maps
to it:

/* Same register field of VAWD0 */
#define AN8855_VARD0			0x10200618

If RD_VID results land in VARD0, the same way the ATU uses separate
ATWD/ATRD registers, several values would come from whatever was last
written to VAWD0:

  - old_members
  - the VLAN_VALID check in mt7530_hw_vlan_del()
  - the ETAG bits kept by regmap_field_update_bits()

mt7530_lib_setup_vlan0() leaves VAWD0 with all ports in PORT_MEM and
EG_CON set. Would every VLAN added through an8855_port_vlan_add() then
get all ports as members and inherit EG_CON? Would
an8855_port_vlan_del() ever actually remove a port?

Should the fetched entry be read from AN8855_VARD0 instead?

[ ... ]

> +static const struct mt7530_mib_desc an8855_mib[] = {
> +	MIB_DESC(MT7530_MIB_TX_DROP, -1, "TxDrop"),
> +	MIB_DESC(MT7530_MIB_TX_CRC_ERR, -1, "TxCrcErr"),
> +	MIB_DESC(MT7530_MIB_TX_COLLISION, -1, "TxCollision"),
> +	MIB_DESC(AN8855_MIB_TX_OVERSIZE_DROP, -1, "TxOversizeDrop"),
> +	MIB_DESC(AN8855_MIB_TX_BAD_PKT_BYTES_LOW,
> +		 AN8855_MIB_TX_BAD_PKT_BYTES_HIGH, "TxBadPktBytes"),
> +	MIB_DESC(MT7530_MIB_RX_DROP, -1, "RxDrop"),
> +	MIB_DESC(MT7530_MIB_RX_FILTERING, -1, "RxFiltering"),
> +	MIB_DESC(MT7530_MIB_RX_CRC_ERR, -1, "RxCrcErr"),

[Severity: Medium]
Some of these private ethtool -S strings already have standard uAPIs:

  - "RxCrcErr" matches ethtool_eth_mac_stats FrameCheckSequenceErrors
    and rtnl_link_stats64 rx_crc_errors.
  - "TxCollision" matches rtnl_link_stats64 collisions.

The driver implements get_eth_mac_stats through
mt7530_lib_get_eth_mac_stats(), but that helper never fills
FrameCheckSequenceErrors. The standard counter reads 0, and the value
only shows up in the private list.

Could these be reported through the standard interfaces instead?

[ ... ]

> +static int an8855_port_fdb_dump(struct dsa_switch *ds, int port,
> +				dsa_fdb_dump_cb_t *cb, void *data)
> +{
> +	struct an8855_priv *priv = ds->priv;
> +	int banks, count = 0;
> +	u32 rsp;
> +	int ret;
> +	int i;
> +
> +	mutex_lock(&priv->reg_mutex);
> +
> +	/* Load search port */
> +	ret = regmap_write(priv->regmap, AN8855_ATWD2,
> +			   FIELD_PREP(AN8855_ATWD2_PORT, BIT(port)));
> +	if (ret)
> +		goto exit;
> +	ret = mt7530_lib_fdb_cmd(&priv->lib_priv, MT7530_FDB_START,
> +				 AN8855_FDB_MAT_MAC_PORT, &rsp);
> +	if (ret < 0)
> +		goto exit;
> +
> +	do {
> +		/* From response get the number of banks to read, exit if 0 */
> +		banks = FIELD_GET(AN8855_ATC_HIT, rsp);

[Severity: Low]
rsp is not initialised. mt7530_lib_fdb_cmd() ignores the result of its
final read and returns success:

	if (rsp)
		regmap_field_read(priv->fields[__MT7530_ATC], rsp);

	return 0;

regmap_field_read() does not write *val on error. If that MDIO read
fails after a successful busy poll, is uninitialised stack data used as
the bank bitmap here? That could produce bogus dump entries or end the
dump early.

[ ... ]

> +static int an8855_port_change_mtu(struct dsa_switch *ds, int port,
> +				  int new_mtu)
> +{
> +	struct an8855_priv *priv = ds->priv;
> +
> +	return mt7530_lib_port_change_mtu(&priv->lib_priv, port, new_mtu);
> +}
> +
> +static int an8855_port_max_mtu(struct dsa_switch *ds, int port)
> +{
> +	return AN8855_MAX_MTU;
> +}

[Severity: Medium]
Does the jumbo size encoding match AN8855? For lengths above 1552,
mt7530_lib_port_change_mtu() uses a linear 1 KiB encoding:

		regmap_field_write(priv->fields[MT7530_GMACCR_MAX_RX_JUMBO],
				   DIV_ROUND_UP(length, 1024));

an8855.h documents a non-linear encoding:

#define   AN8855_MAX_RX_JUMBO_9K	FIELD_PREP_CONST(AN8855_MAX_RX_JUMBO, 0x9)
#define   AN8855_MAX_RX_JUMBO_12K	FIELD_PREP_CONST(AN8855_MAX_RX_JUMBO, 0xa)
#define   AN8855_MAX_RX_JUMBO_15K	FIELD_PREP_CONST(AN8855_MAX_RX_JUMBO, 0xb)
#define   AN8855_MAX_RX_JUMBO_16K	FIELD_PREP_CONST(AN8855_MAX_RX_JUMBO, 0xc)

This gives three problems:

  - With AN8855_MAX_MTU = 15338, the length is 15338 + 14 + 4 + 4 =
    15360, which programs 0xf. That value is not defined.
  - Lengths from 9217 to 12288 program 0xa..0xc. The hardware reads
    those as 12K/15K/16K, not 10K/11K/12K.
  - Anything above 12288 programs one of the undefined values
    0xd..0xf.

Does AN8855 need its own translation here?

[ ... ]

> +static const struct ethtool_rmon_hist_range an8855_rmon_ranges[] = {
> +	{ 0, 64 },
> +	{ 65, 127 },
> +	{ 128, 255 },
> +	{ 256, 511 },
> +	{ 512, 1023 },
> +	{ 1024, 1518 },
> +	{ 1519, AN8855_MAX_MTU },
> +	{}
> +};

[Severity: Low]
This isn't a bug, but AN8855_MAX_MTU is an L3 MTU while the other bounds
are frame lengths. The last bucket's reported upper bound ends up about
22 bytes below the largest frame the counter can count. mt7530.c and
rzn1_a5psw.c use the same convention.

[ ... ]

> +static int an8855_port_enable(struct dsa_switch *ds, int port,
> +			      struct phy_device *phy)
> +{
> +	struct an8855_priv *priv = ds->priv;
> +	int ret;
> +
> +	mutex_lock(&priv->reg_mutex);
> +	priv->ports[port].enable = true;
> +	ret = regmap_set_bits(priv->regmap, AN8855_PMCR_P(port),
> +			      AN8855_PMCR_TX_EN | AN8855_PMCR_RX_EN);
> +	mutex_unlock(&priv->reg_mutex);
> +
> +	return ret;
> +}
> +
> +static void an8855_port_disable(struct dsa_switch *ds, int port)
> +{
> +	struct an8855_priv *priv = ds->priv;
> +	int ret;
> +
> +	mutex_lock(&priv->reg_mutex);
> +	priv->ports[port].enable = false;
> +	ret = regmap_clear_bits(priv->regmap, AN8855_PMCR_P(port),
> +				AN8855_PMCR_TX_EN | AN8855_PMCR_RX_EN);
> +	mutex_unlock(&priv->reg_mutex);
> +	if (ret)
> +		dev_err(priv->ds->dev, "failed to disable port: %d\n", ret);
> +}

[Severity: High]
mt7530_update_port_member() only writes the port matrix to hardware for
ports that are currently enabled:

	p->pm = port_bitmap;
	if (priv->ports[port].enable)
		regmap_fields_write(priv->fields[MT7530_PCR_MATRIX],
				    port, port_bitmap);

The same check applies to other_p->enable. The helper relies on
port_enable to write ports[port].pm and on port_disable to clear the
matrix, which is what mt7530_port_enable() and mt7530_port_disable() do.
an8855_port_enable() and an8855_port_disable() only toggle the enable
flag and PMCR TX/RX_EN.

Take this sequence:

  ip link set lan1 master br0    (lan1 still down)
  ip link set lan1 up

Doesn't AN8855_PORTMATRIX_P(port) keep the BIT(AN8855_CPU_PORT) value
from an8855_setup()? Then the hardware never forwards lan1 frames to its
bridge siblings, and the software bridge won't either because
offload_fwd_mark is set.

The reverse case is a bridged port that goes down, leaves the bridge,
and comes back up standalone. Does its matrix still list the old bridge
members, so traffic leaks between the standalone port and the bridge?

Should these callbacks write priv->ports[port].pm to
AN8855_PORTMATRIX_P(port) on enable and clear it on disable, as mt7530
does?

> +static int an8855_set_mac_eee(struct dsa_switch *ds, int port,
> +			      struct ethtool_keee *e)
> +{
> +	if (e->tx_lpi_timer > 0xFFF)
> +		return -EINVAL;
> +
> +	return 0;
> +}

[Severity: Medium]
This limit matches mt753x_set_mac_eee(), but it rejects this driver's
own default. an8855_phylink_get_caps() sets:

	/* Global LPI TXIDLE Threshold, default 60ms (unit 2us) */
	config->lpi_timer_default = FIELD_GET(AN8855_LPI_TXIDLE_THD_MASK, reg) *
				    AN8855_TX_LPI_UNIT;

That is roughly 60000us, and phylink reports it through get_eee.
ethnl_set_eee() starts from the get_eee values and only changes the
attributes the user passes. dsa_user_set_eee() returns the
set_mac_eee() error before it calls phylink_ethtool_set_eee().

So will something like "ethtool --set-eee lan1 eee off" fail with
-EINVAL unless a small tx-timer is also given?

an8855_phylink_mac_enable_tx_lpi() already clamps to the 18-bit
AN8855_LPI_TXIDLE_THD_MASK field. Is the 0xFFF check needed at all?

[ ... ]

> +static void an8855_phylink_mac_link_up(struct phylink_config *config,
> +				       struct phy_device *phydev, unsigned int mode,
> +				       phy_interface_t interface, int speed,
> +				       int duplex, bool tx_pause, bool rx_pause)
> +{
> +	struct dsa_port *dp = dsa_phylink_to_port(config);
> +	struct an8855_priv *priv = dp->ds->priv;
> +	int port = dp->index;
> +	u32 reg = 0;
> +
> +	mutex_lock(&priv->reg_mutex);
> +
> +	regmap_read(priv->regmap, AN8855_PMCR_P(port), &reg);

[Severity: Low]
The regmap_read() return value is ignored here. If the read fails, reg
stays 0, and the later regmap_write(priv->regmap, AN8855_PMCR_P(port),
reg) overwrites the whole register. That write would clear:

  - MAC_MODE, IFG_XMIT, BACKOFF_EN and BACKPR_EN, set in
    an8855_phylink_mac_config()
  - the FORCE_EEE bits, set in an8855_phylink_mac_enable_tx_lpi()

Should the read error be checked, or regmap_update_bits() used instead?

[ ... ]

> +	if (timer) {
> +		int i;
> +
> +		/* Save requested timer and search the highest one */
> +		mutex_lock(&priv->reg_mutex);
> +		priv->tx_lpi_timer_ports[dp->index] = timer;
> +		for (i = 0; i < AN8855_NUM_PORTS; i++) {
> +			if (!priv->ports[i].enable)
> +				continue;
> +
> +			if (i == dp->index)
> +				continue;
> +
> +			if (timer < priv->tx_lpi_timer_ports[i])
> +				timer = priv->tx_lpi_timer_ports[i];
> +		}

[Severity: Low]
tx_lpi_timer_ports[] is only written when a non-zero timer is
requested. It is not reset in the timer == 0 branch or in
an8855_phylink_mac_disable_tx_lpi().

A port that has since disabled LPI, or switched to immediate LPI, still
counts in this maximum. Can the shared AN8855_CKGCR threshold therefore
stay higher than any active port asked for?

[ ... ]

> +	/* PLL - SDM */
> +	ret = regmap_update_bits(priv->regmap, AN8855_PLL_CTRL_2,
> +				 AN8855_RG_DA_QP_PLL_SDM_HREN_INTF,
> +				 FIELD_PREP(AN8855_RG_DA_QP_PLL_SDM_HREN_INTF, 0x0));
> +	if (ret)
> +		return ret;

[Severity: Medium]
Should this write go to AN8855_PLL_CTRL_4? The header defines this field
under PLL_CTRL_4:

#define AN8855_PLL_CTRL_4		0x1022e410
#define   AN8855_RG_DA_QP_PLL_SDM_HREN_INTF GENMASK(4, 3)

In PLL_CTRL_2, bits 4:3 belong to AN8855_RG_DA_QP_PLL_BPA_INTF
(GENMASK(4, 2)). The "PLL - LPF" step just above sets that field to
0x5, and this update turns it into 0x1. The PLL_CTRL_4 SDM_HREN bits
are never written.

The other PLL_CTRL_4 fields in an8855_pcs_config() (ICOLP_EN and
SSC_DIR_DLY) are written to PLL_CTRL_4.

[ ... ]

> +	/* PCS Init */
> +	if (interface == PHY_INTERFACE_MODE_SGMII &&
> +	    neg_mode == PHYLINK_PCS_NEG_INBAND_DISABLED) {
> +		ret = regmap_clear_bits(priv->regmap, AN8855_QP_DIG_MODE_CTRL_0,
> +					AN8855_RG_SGMII_MODE | AN8855_RG_SGMII_AN_EN);
> +		if (ret)
> +			return ret;
> +	}
> +
> +	ret = regmap_clear_bits(priv->regmap, AN8855_RG_HSGMII_PCS_CTROL_1,
> +				AN8855_RG_TBI_10B_MODE);
> +	if (ret)
> +		return ret;
> +
> +	if (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED) {
> +		/* Set AN Ability - Interrupt */
> +		ret = regmap_set_bits(priv->regmap, AN8855_SGMII_REG_AN_FORCE_CL37,
> +				      AN8855_RG_FORCE_AN_DONE);
> +		if (ret)
> +			return ret;

[Severity: Low]
Several bits in an8855_pcs_config() are set or cleared in only one
branch, and nothing restores them when the mode changes:

  - The SGMII in-band path sets RG_FORCE_AN_DONE and RG_P0_RA_AN_EN.
    It never clears FORCE_TXC_SEL or FORCE_SPD_MODE_P0.
  - The in-band path never sets RG_SGMII_MODE or RG_SGMII_AN_EN again
    after the block above has cleared them.
  - RG_P0_MII_MODE is set on the SGMII path and is not cleared on the
    2500BASE-X path.

If phylink reconfigures port 5 to another mode, or the bootloader left
a different setup, could these stale bits keep the link from coming up
or select the wrong rate adaptation?

[ ... ]

> +	/* Force Speed with fixed-link or 2500base-x as doesn't support aneg */
> +	if (interface == PHY_INTERFACE_MODE_2500BASEX ||
> +	    neg_mode != PHYLINK_PCS_NEG_INBAND_ENABLED) {
> +		if (interface == PHY_INTERFACE_MODE_2500BASEX)
> +			val = AN8855_RG_LINK_MODE_P0_SPEED_2500;
> +		else
> +			val = AN8855_RG_LINK_MODE_P0_SPEED_1000;

[Severity: Medium]
SGMII without in-band negotiation is always forced to 1000 here, and
an8855_pcs_ops has no .pcs_link_up to program the resolved speed.

an8855_phylink_get_caps() still advertises MAC_10 | MAC_100, and
an8855_phylink_mac_link_up() forces the MAC to 10 or 100. Take port 5
with phy-mode sgmii and a fixed-link of speed = <100>. Would the PCS
stay at 1000 while the MAC runs at 100?

The header defines AN8855_RG_LINK_MODE_P0_SPEED_100 and _10, but they
are never used.

Should there be a pcs_link_up callback that programs the speed?

[ ... ]

> diff --git a/drivers/net/dsa/mt7530-lib.c b/drivers/net/dsa/mt7530-lib.c
> --- a/drivers/net/dsa/mt7530-lib.c
> +++ b/drivers/net/dsa/mt7530-lib.c
> @@ -483,8 +497,14 @@ void mt7530_lib_fdb_read(struct mt7530_lib_priv *priv, struct mt7530_fdb *fdb)
>  	fdb->mac[1] = val;
>  	regmap_field_read(priv->fields[MT7530_ATRD_MAC_BYTE_0], &val);
>  	fdb->mac[0] = val;
> -	regmap_field_read(priv->fields[MT7530_ATRD_ENT_STATUS], &val);
> -	fdb->noarp = val == STATIC_ENT;
> +	if (priv->fields[MT7530_ATWD_ENT_STATUS]) {
> +		regmap_field_read(priv->fields[MT7530_ATRD_ENT_STATUS], &val);
> +		fdb->noarp = val == STATIC_ENT;
> +	}
> +	if (priv->fields[AN8855_ATRD_ARP]) {
> +		regmap_field_read(priv->fields[AN8855_ATRD_ARP], &val);
> +		fdb->noarp = !!val;
> +	}
>  }
>  EXPORT_SYMBOL_GPL(mt7530_lib_fdb_read);
>  

[Severity: High]
The guard here tests the write-data field MT7530_ATWD_ENT_STATUS,
but the read goes through MT7530_ATRD_ENT_STATUS.
regmap_field_read() dereferences field->regmap without checking the
field pointer. A mt7530-lib user that fills in the ATWD entry but
leaves out the ATRD one would oops here on every FDB dump that
reaches mt7530_lib_fdb_read().

With the users in this series, both fields appear to be populated
together for mt7530 and both are absent for an8855, so nothing
crashes today. The check is still protecting the wrong pointer.

The reverse case also goes wrong. A switch that provides only the
ATRD status field would silently skip it and never report noarp
from it.

Should this test priv->fields[MT7530_ATRD_ENT_STATUS] instead, so
the check matches the field that is actually read?

-- 
Sashiko AI review · https://netdev-ai.bots.linux.dev/sashiko/#/patchset/20260925182435.21207-1-ansuelsmth%40gmail.com

Re: [PATCH net-next v23 8/9] net: dsa: mt7530: generalize and move common function to lib module

[Andrew Lunn]

On Fri, Sep 25, 2026 at 08:24:30PM +0200, Christian Marangi wrote:
> In preparation of support of DSA Switch from Airoha, create a mt7530
> library module and move there all the common function.
> 
> Function are generalized to use the reg_field regmap API but still apply
> the same exact logic. Every function is renamed to mt7530_lib prefix to
> better identify it.
> 
> Minimum modification are needed to the register header and common enum and
> macro are moved to the mt7530 library header to permit reuse.
> 
> A library struct is introduced with everything required for the common
> functions.
> 
> The generalization and the introduction of reg_field regmap API have the
> side effect of permitting to clean the mirror functions that required
> special handling for MT7530 and MT7531 based switch that had different
> registers. This is done by declaring a common MT7530 reg_field and a
> specific one in the Switch match table.
> 
> No behaviour change is expected by this change as it's just a code move and
> reimplementation.
> 
> Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
> ---
>  drivers/net/dsa/Kconfig       |    4 +
>  drivers/net/dsa/Makefile      |    1 +
>  drivers/net/dsa/mt7530-lib.c  | 1128 +++++++++++++++++++++++++++
>  drivers/net/dsa/mt7530-lib.h  |  391 ++++++++++
>  drivers/net/dsa/mt7530-mdio.c |    4 +
>  drivers/net/dsa/mt7530-mmio.c |    4 +
>  drivers/net/dsa/mt7530.c      | 1368 ++++++++-------------------------
>  drivers/net/dsa/mt7530.h      |  256 ++----

The number of mt* file keep going up. Is it time to move it into a
subdirectory?

Reviewed-by: Andrew Lunn <andrew@lunn.ch>

    Andrew

Re: [PATCH net-next v23 8/9] net: dsa: mt7530: generalize and move common function to lib module

[Christian Marangi]

On Sun, Sep 27, 2026 at 09:02:09PM +0200, Andrew Lunn wrote:
> On Fri, Sep 25, 2026 at 08:24:30PM +0200, Christian Marangi wrote:
> > In preparation of support of DSA Switch from Airoha, create a mt7530
> > library module and move there all the common function.
> > 
> > Function are generalized to use the reg_field regmap API but still apply
> > the same exact logic. Every function is renamed to mt7530_lib prefix to
> > better identify it.
> > 
> > Minimum modification are needed to the register header and common enum and
> > macro are moved to the mt7530 library header to permit reuse.
> > 
> > A library struct is introduced with everything required for the common
> > functions.
> > 
> > The generalization and the introduction of reg_field regmap API have the
> > side effect of permitting to clean the mirror functions that required
> > special handling for MT7530 and MT7531 based switch that had different
> > registers. This is done by declaring a common MT7530 reg_field and a
> > specific one in the Switch match table.
> > 
> > No behaviour change is expected by this change as it's just a code move and
> > reimplementation.
> > 
> > Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
> > ---
> >  drivers/net/dsa/Kconfig       |    4 +
> >  drivers/net/dsa/Makefile      |    1 +
> >  drivers/net/dsa/mt7530-lib.c  | 1128 +++++++++++++++++++++++++++
> >  drivers/net/dsa/mt7530-lib.h  |  391 ++++++++++
> >  drivers/net/dsa/mt7530-mdio.c |    4 +
> >  drivers/net/dsa/mt7530-mmio.c |    4 +
> >  drivers/net/dsa/mt7530.c      | 1368 ++++++++-------------------------
> >  drivers/net/dsa/mt7530.h      |  256 ++----
> 
> The number of mt* file keep going up. Is it time to move it into a
> subdirectory?

The problem as always is that mediatek directory will also contain airoha
stuff...

> 
> Reviewed-by: Andrew Lunn <andrew@lunn.ch>
>

I would like to fix some trivial things pointed out by sashiko. Can I apply
those and keep the review tag? For this patch for example it's just the
typo for the multicast MIB.

For the other patch is also very trivial stuff. 

-- 
	Ansuel

Re: [PATCH net-next v23 8/9] net: dsa: mt7530: generalize and move common function to lib module

[Andrew Lunn]

On Sun, Sep 27, 2026 at 10:28:25PM +0200, Christian Marangi wrote:
> On Sun, Sep 27, 2026 at 09:02:09PM +0200, Andrew Lunn wrote:
> > On Fri, Sep 25, 2026 at 08:24:30PM +0200, Christian Marangi wrote:
> > > In preparation of support of DSA Switch from Airoha, create a mt7530
> > > library module and move there all the common function.
> > > 
> > > Function are generalized to use the reg_field regmap API but still apply
> > > the same exact logic. Every function is renamed to mt7530_lib prefix to
> > > better identify it.
> > > 
> > > Minimum modification are needed to the register header and common enum and
> > > macro are moved to the mt7530 library header to permit reuse.
> > > 
> > > A library struct is introduced with everything required for the common
> > > functions.
> > > 
> > > The generalization and the introduction of reg_field regmap API have the
> > > side effect of permitting to clean the mirror functions that required
> > > special handling for MT7530 and MT7531 based switch that had different
> > > registers. This is done by declaring a common MT7530 reg_field and a
> > > specific one in the Switch match table.
> > > 
> > > No behaviour change is expected by this change as it's just a code move and
> > > reimplementation.
> > > 
> > > Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
> > > ---
> > >  drivers/net/dsa/Kconfig       |    4 +
> > >  drivers/net/dsa/Makefile      |    1 +
> > >  drivers/net/dsa/mt7530-lib.c  | 1128 +++++++++++++++++++++++++++
> > >  drivers/net/dsa/mt7530-lib.h  |  391 ++++++++++
> > >  drivers/net/dsa/mt7530-mdio.c |    4 +
> > >  drivers/net/dsa/mt7530-mmio.c |    4 +
> > >  drivers/net/dsa/mt7530.c      | 1368 ++++++++-------------------------
> > >  drivers/net/dsa/mt7530.h      |  256 ++----
> > 
> > The number of mt* file keep going up. Is it time to move it into a
> > subdirectory?
> 
> The problem as always is that mediatek directory will also contain airoha
> stuff...

That is only a Marketing problem, and Mainline generally ignores
marketing. Companies get bought and sold all the time. We don't rename
anything because of that.

> I would like to fix some trivial things pointed out by sashiko. Can I apply
> those and keep the review tag? For this patch for example it's just the
> typo for the multicast MIB.
> 
> For the other patch is also very trivial stuff. 

Yes, not a problem. If you make major changes then drop it, but
trivial stuff is fine.

	Andrew

Re: [PATCH net-next v23 8/9] net: dsa: mt7530: generalize and move common function to lib module

[netdev-bot+sashiko]

Thank you for your contribution! Sashiko AI review found 7 potential
issue(s) to consider.

Critical: 0 · High: 1 · Medium: 3 · Low: 3 (4)

If you believe none of the issues are legitimate, please reply to each
issue of Medium severity or higher and explain why the AI is wrong.
If any of them are legitimate and you plan to respin, please let patchwork
know by including "pw-bot: cr" as a separate line at the end of your reply
(one such reply per series is enough).

- [High] A name collision between a macro and an enum constant puts the
  mirror-enable regmap field at the wrong index.
- [Medium] mt7530_read_port_stats64() no longer fills
  rtnl_link_stats64.multicast.
- [Medium] mt753x_table[ID_EN7528] now uses `.reg_fields =
  mt7531_fields`, so on EN7528 mirroring goes to MT7531_CFC (MIRROR_EN…
- [Medium] mt7530_lib_port_mdb_add(), mt7530_lib_port_mdb_del() and
  mt7530_hw_vlan_del() declare `u32 val;` without initializing it.
- [Low] mt7530_lib_fdb_cmd() and mt7530_vlan_cmd() ignore failures of
  their final status reads.
- [Low] Two comments were not updated to match the new code.
- [Low] Splitting whole-register accesses into regmap_field accesses
  multiplies register traffic for FDB and VLAN operations.

Pre-existing issues:
- [Low] This problem wasn't introduced by this patch, but
  mt7530_hw_vlan_update() ignores the results of the RD_VID command, the…
- [Low] This problem wasn't introduced by this patch, but
  mt7530_lib_port_mdb_add()/mt7530_lib_port_mdb_del() handle any failure…
- [Low] This problem wasn't introduced by this patch, but
  mt7530_lib_fdb_write() returns void and ignores every register write.
- [Low] This problem wasn't introduced by this patch, but
  mt7530_port_fdb_dump() returns 0 unconditionally.

--

net: dsa: mt7530: generalize and move common function to lib module

This commit adds a mt7530 library module to prepare for Airoha DSA switch
support, and moves the common MT7530 functions into it under a mt7530_lib
prefix. The functions now use the regmap reg_field API. There is one
common field table, plus per-chip mirror fields taken from the match table.
The commit message says no behaviour change is expected.

> diff --git a/drivers/net/dsa/mt7530-lib.c b/drivers/net/dsa/mt7530-lib.c
> new file mode 100644
> index 0000000000000..098dd45d3ee9f
> --- /dev/null
> +++ b/drivers/net/dsa/mt7530-lib.c

[ ... ]

> +int mt7530_lib_fdb_cmd(struct mt7530_lib_priv *priv, enum mt7530_fdb_cmd cmd,
> +		       u32 mat, u32 *rsp)
> +{

[ ... ]

> +	ret = regmap_field_read_poll_timeout(priv->fields[MT7530_ATC_BUSY],
> +					     val, !val, 20, 20000);
> +	if (ret < 0) {
> +		dev_err(priv->dev, "reset timeout\n");
> +		return ret;
> +	}
> +
> +	regmap_field_read(priv->fields[MT7530_ATC_INVALID], &val);
> +	if (cmd == MT7530_FDB_READ && val)
> +		return -EINVAL;
> +
> +	if (rsp)
> +		regmap_field_read(priv->fields[__MT7530_ATC], rsp);
> +
> +	return 0;
> +}

[Severity: Low]
The old mt7530_fdb_cmd() returned an error if the final regmap_read() of
MT7530_ATC failed. Both regmap_field_read() calls here ignore the return
value.

After a successful busy poll val is 0, and a failed read leaves it at 0.
That means an invalid entry would be reported as success.

A failed read of rsp leaves the previous command's ATC_SRCH_HIT and
ATC_SRCH_END bits in place. Could mt7530_port_fdb_dump() then process stale
search state and report duplicate entries (bounded by cnt)?

mt7530_vlan_cmd() does the same thing with MT7530_VTCR_INVALID. The last
patch in the series wraps these reads in NULL checks, but it still doesn't
check their return values.

Should these reads check their return values as the old code did?

> +
> +static void mt7530_lib_fdb_write(struct mt7530_lib_priv *priv, u16 vid,
> +				 u8 port_mask, const u8 *mac,
> +				 u8 aging, u8 type)
> +{
> +	/* Clear ATWD registers from previous access */
> +	regmap_field_write(priv->fields[__MT7530_ATWD1], 0);
> +	regmap_field_write(priv->fields[__MT7530_ATWD2], 0);
> +	regmap_field_write(priv->fields[__MT7530_ATWD3], 0);
> +
> +	regmap_field_write(priv->fields[MT7530_ATWD_CVID], vid);

[ ... ]

> +	regmap_field_write(priv->fields[MT7530_ATWD_MAC_BYTE_0], mac[0]);
> +}

[Severity: Low]
This isn't a bug introduced by this patch, but mt7530_lib_fdb_write()
returns void and ignores every register write, just like the old
mt7530_fdb_write().

mt7530_lib_port_fdb_add() and mt7530_lib_port_fdb_del() then issue
MT7530_FDB_WRITE even if writing the ATA/ATWD staging registers failed.

Could that write or delete an entry keyed on a partly programmed MAC/VID?

> +
> +void mt7530_lib_fdb_read(struct mt7530_lib_priv *priv, struct mt7530_fdb *fdb)
> +{
> +	u32 val = 0;
> +
> +	regmap_field_read(priv->fields[MT7530_ATRD_CVID], &val);
> +	fdb->vid = val;

[ ... ]

> +	regmap_field_read(priv->fields[MT7530_ATRD_ENT_STATUS], &val);
> +	fdb->noarp = val == STATIC_ENT;
> +}

[Severity: Low]
This isn't a bug, but splitting whole-register accesses into regmap fields
adds a lot of register traffic on the MDIO path, where the regmap has no
cache. Each field write is a read plus a write. Each 32-bit access over
MDIO is a page-select write plus two 16-bit transfers.

The register access counts before and after this patch:

- mt7530_lib_fdb_read(): 10 register reads instead of 3.
- mt7530_lib_fdb_write(): 3 clears plus 12 field read-modify-writes,
  instead of 3 writes.
- mt7530_lib_fdb_cmd(): 3 read-modify-writes, the poll and 2 more reads,
  instead of 1 write, the poll and 1 read.

mt7530_port_fdb_dump() repeats FDB_NEXT plus mt7530_lib_fdb_read() for up
to MT7530_NUM_FDB_RECORDS entries. It does this while holding reg_mutex and
the MDIO bus lock, with about 3x the old bus traffic.

Would it make sense to keep whole-register accesses for the ATA, ATWD,
ATRD and ATC registers?

[ ... ]

> +int mt7530_lib_port_mdb_add(struct mt7530_lib_priv *priv, int port,
> +			    const struct switchdev_obj_port_mdb *mdb,
> +			    struct dsa_db db)
> +{
> +	const u8 *addr = mdb->addr;
> +	u16 vid = mdb->vid;
> +	u8 port_mask = 0;
> +	u32 val;
> +	int ret;
> +
> +	mutex_lock(priv->reg_mutex);
> +
> +	mt7530_lib_fdb_write(priv, vid, 0, addr, 0, STATIC_EMP);
> +	if (!mt7530_lib_fdb_cmd(priv, MT7530_FDB_READ,
> +				ATC_MAT_MACTAB, NULL)) {
> +		regmap_field_read(priv->fields[MT7530_ATRD_PORT_MAP],
> +				  &val);
> +		port_mask = val;
> +	}

[Severity: Medium]
Can val be used uninitialized here? When regmap_read() fails,
regmap_field_read() returns early without writing *val.

The old code called regmap_read() directly on the caller's variable.
mt7530_regmap_read() in mt7530-mdio.c sets *val = 0 first, with the comment
"Callers do not check for errors, keep the value deterministic".
regmap_field_read() reads into its own local reg_val, so that zero no
longer reaches this caller.

On an MDIO read failure, stack garbage would become port_mask and be
written as a STATIC_ENT multicast port map.

mt7530_lib_port_mdb_del() has the same pattern. mt7530_hw_vlan_del() tests
an uninitialized val:

    regmap_field_read(priv->fields[MT7530_VAWD_VLAN_VALID], &val);
    if (!val) {

Should these val variables start at 0, or should the return values be
checked?

> +
> +	port_mask |= BIT(port);
> +	mt7530_lib_fdb_write(priv, vid, port_mask, addr, -1, STATIC_ENT);
> +	ret = mt7530_lib_fdb_cmd(priv, MT7530_FDB_WRITE,
> +				 ATC_MAT_MACTAB, NULL);

[Severity: Low]
This is a pre-existing issue, but any failure of MT7530_FDB_READ (I/O
error or timeout) is handled the same way as a missing entry. In that case
mt7530_lib_port_mdb_add() writes a mask containing only BIT(port), and
mt7530_lib_port_mdb_del() writes STATIC_EMP with a zero mask.

After a failed lookup, can this drop the multicast membership of the other
ports?

[ ... ]

> +static void mt7530_hw_vlan_update(struct mt7530_lib_priv *priv, u16 vid,
> +				  struct mt7530_hw_vlan_entry *entry,
> +				  mt7530_vlan_op vlan_op)
> +{
> +	u32 val = 0;
> +
> +	/* Fetch entry */
> +	mt7530_vlan_cmd(priv, MT7530_VTCR_RD_VID, vid);
> +
> +	regmap_field_read(priv->fields[MT7530_VAWD_PORT_MEM], &val);
> +	entry->old_members = val;
> +
> +	/* Manipulate entry */
> +	vlan_op(priv, entry);
> +
> +	/* Flush result to hardware */
> +	mt7530_vlan_cmd(priv, MT7530_VTCR_WR_VID, vid);
> +}

[Severity: Low]
This isn't a bug introduced by this patch, but mt7530_hw_vlan_update()
ignores the results of the RD_VID command, the PORT_MEM read and the final
WR_VID command. The old code did the same.

vlan_op() can run on stale VAWD data. mt7530_lib_port_vlan_add() and
mt7530_lib_port_vlan_del() then update the PVID state and return 0, even if
the VLAN table write failed.

Should the errors be passed back to the callers?

[ ... ]

> diff --git a/drivers/net/dsa/mt7530.c b/drivers/net/dsa/mt7530.c
> index 50e80585d5585..83cfbd8ee081f 100644
> --- a/drivers/net/dsa/mt7530.c
> +++ b/drivers/net/dsa/mt7530.c
> @@ -24,10 +24,163 @@
>  #include <net/pkt_cls.h>
>  
>  #include "mt7530.h"
> +#include "mt7530-lib.h"

[ ... ]

> +static const struct mt7530_reg_field mt7530_fields[] = {
> +	{ MT7530_MIRROR_EN, REG_FIELD(MT753X_MFC, 3, 3) },
> +	{ MT7530_MIRROR_PORT, REG_FIELD(MT753X_MFC, 0, 2) },
> +};
> +
> +static const struct mt7530_reg_field mt7531_fields[] = {
> +	{ MT7530_MIRROR_EN, REG_FIELD(MT7531_CFC, 19, 19) },
> +	{ MT7530_MIRROR_PORT, REG_FIELD(MT7531_CFC, 16, 18) },
> +};

[Severity: High]
Does MT7530_MIRROR_EN expand to the enum index here? mt7530.h includes
mt7530-lib.h, which declares:

    enum mt7530_regmap_field {
    	MT7530_MIRROR_EN,
    	...

After that include, mt7530.h still keeps the old register bit define:

    #define  MT7530_MIRROR_EN		BIT(3)

So in mt7530.c both tables get id = BIT(3) = 8, which is
MT7530_CCR_TX_OCT_CNT_GOOD in the enum. mt7530-lib.c only includes
mt7530-lib.h, so in the library MT7530_MIRROR_EN is 0.

mt7530_setup_lib_priv() fills in mt753x_fields first and the per-chip
table second. That overwrites fields[8] with the mirror enable field and
leaves fields[0] NULL, since priv comes from devm_kzalloc().

A tc matchall mirred rule then reaches:

mt753x_port_mirror_add()
  mt7530_lib_port_mirror_add()
    regmap_field_read(priv->fields[MT7530_MIRROR_EN], &val)

with a NULL field, and regmap_field_read() dereferences field->regmap.
mt7530_lib_port_mirror_del() also writes through the same NULL field.

mt7530_lib_mib_reset() is called from mt7530_setup() and
mt7531_setup_common(), and does:

    regmap_field_write(priv->fields[MT7530_CCR_TX_OCT_CNT_GOOD], 1);

This would now set the global mirror enable bit (MFC bit 3 or CFC bit 19)
on every setup, and MIB CCR bit 5 would never be set. The old code wrote
CCR_MIB_ACTIVATE, which included TX_OCT_CNT_GOOD.

mt7530.h and mt7530.c aren't changed later in the series, so this seems to
still be present at the end of it. Should the old MT7530_MIRROR_EN define
be removed or renamed?

[ ... ]

> @@ -35,15 +188,15 @@ static struct mt753x_pcs *pcs_to_mt753x_pcs(struct phylink_pcs *pcs)
>  
>  /* String, offset, and register size in bytes if different from 4 bytes */
>  static const struct mt7530_mib_desc mt7530_mib[] = {

[ ... ]

> +	MIB_DESC(MT7530_MIB_TX_DROP, -1, "TxDrop"),

[Severity: Low]
This isn't a bug, but this comment no longer matches the descriptor. The
descriptor now holds regmap field IDs (field_low, field_high, with -1
meaning no high word), not an offset and a size.

The same goes for this comment in mt7530.h:

    /* Each define is an offset of MT7530_PORT_MIB_COUNTER */

Each MT7530_PORT_MIB_* define now includes the MT7530_MIB_COUNTER base and
is used as an absolute port 0 address.

[ ... ]

> @@ -861,38 +833,40 @@ static void mt7530_read_port_stats64(struct mt7530_priv *priv, int port,
>  	 * To simulate a global frame counter, read Unicast and addition Multicast
>  	 * and Broadcast later
>  	 */
> -	mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_UNICAST, 1,
> -			       &storage->rx_packets);
> -	mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_MULTICAST, 1,
> -			       &storage->multicast);
> -	storage->rx_packets += storage->multicast;
> -	mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_BROADCAST, 1,
> -			       &data);
> +	mt7530_lib_read_port_stats(lib_priv->fields[MT7530_MIB_RX_UNICAST],
> +				   NULL, port, &storage->rx_packets);
> +	mt7530_lib_read_port_stats(lib_priv->fields[MT7530_MIB_RX_MULTICAST],
> +				   NULL, port, &data);
> +	storage->rx_packets += data;

[Severity: Medium]
The old code read the RX multicast counter into storage->multicast. The new
code reads it into the scratch variable data and only adds it to
rx_packets. Nothing else in mt7530*.c writes the multicast field now.

mt7530_stats_refresh() starts from a zeroed struct rtnl_link_stats64.
Won't ndo_get_stats64 then always report multicast as 0 on every user port?
The commit message says no behaviour change is expected.

[ ... ]

> @@ -1785,7 +1250,8 @@ mt7530_port_fdb_dump(struct dsa_switch *ds, int port,
>  		}
>  	} while (--cnt &&
>  		 !(rsp & ATC_SRCH_END) &&
> -		 !mt7530_fdb_cmd(priv, MT7530_FDB_NEXT, &rsp));
> +		 !mt7530_lib_fdb_cmd(&priv->lib_priv, MT7530_FDB_NEXT,
> +				     ATC_MAT_MACTAB, &rsp));
>  err:
>  	mutex_unlock(&priv->reg_mutex);
>  

[Severity: Low]
This is a pre-existing issue, but mt7530_port_fdb_dump() still returns 0
unconditionally after this label. A failed FDB_START jumps to err, and a
failed FDB_NEXT ends the loop without keeping its error.

Should the error be returned to dsa_port_fdb_dump(), so an incomplete dump
isn't reported as success?

[ ... ]

> @@ -3509,6 +2738,8 @@ const struct mt753x_info mt753x_table[] = {
>  	},
>  	[ID_AN7583] = {
>  		.id = ID_AN7583,
> +		.reg_fields = mt7531_fields,
> +		.num_reg_fields = ARRAY_SIZE(mt7531_fields),
>  		.pcs_ops = &mt7530_pcs_ops,

[ ... ]

> @@ -3519,6 +2750,8 @@ const struct mt753x_info mt753x_table[] = {
>  	},
>  	[ID_EN7528] = {
>  		.id = ID_EN7528,
> +		.reg_fields = mt7531_fields,
> +		.num_reg_fields = ARRAY_SIZE(mt7531_fields),
>  		.pcs_ops = &mt7530_pcs_ops,

[Severity: Medium]
Is it intended that EN7528 uses mt7531_fields? The MT753X_MIRROR_REG()
macro still in mt7530.h maps only MT7531, MT7988, EN7581 and AN7583 to
MT7531_CFC. Before this patch, EN7528 mirroring used MT753X_MFC with
enable BIT(3) and port GENMASK(2, 0).

Other code that this patch doesn't touch also treats EN7528 as MFC-based.
mt753x_conduit_state_change() groups it with MT7530 and MT7621, and
mt753x_cpu_port_enable() leaves it out of the MT7531_CFC CPU_PMAP chips.

On EN7528, mt7530_lib_port_mirror_add() would now do a read-modify-write
on bits 16..19 of register 0x4 instead of bits 0..3 of MFC. It would still
return success.

AN7583 changes as well. MT753X_MIRROR_EN() did not list ID_AN7583, so its
enable bit was BIT(3) in CFC, which overlaps CPU_PMAP. It is now BIT(19).
If that was an old bug being fixed, could the commit message say so?

The MT753X_MIRROR_* macros are now unused, and they contradict the new
tables for both chips.

-- 
Sashiko AI review · https://netdev-ai.bots.linux.dev/sashiko/#/patchset/20260925182435.21207-1-ansuelsmth%40gmail.com