* [PATCHv4 for soc 0/4] Enabling socfpga on hardware
@ 2013-02-04 20:12 dinguyen at altera.com
2013-02-04 20:12 ` [PATCHv4 for soc 1/4] arm: socfpga: Add new device tree source for actual socfpga HW dinguyen at altera.com
` (4 more replies)
0 siblings, 5 replies; 8+ messages in thread
From: dinguyen at altera.com @ 2013-02-04 20:12 UTC (permalink / raw)
To: linux-arm-kernel
From: Dinh Nguyen <dinguyen@altera.com>
V4:
- Check for cpu1start_addr is valid in socfpga_boot_secondary()
- Add Reviewed-by: Reviewed-by: Santosh Shilimkar <santosh.shilimkar@ti.com> for 3/4
V3:
- Addressed comments from Olof Johansson and Russell King
- Received Acked-by and Tested-by Stephen Warren
- Received Signed-off-by Pavel Machek
V2:
- Remove patch that adds clock entries in the socfpga.dtsi as this
should accompany a rework in drivers/clk and will done in a different
patch series.
- Removed I-cache invalidate from v7_invalidate_l1
- Defined cpu1-start-addr as a device tree entry
- Removed the need to use CONFIG_VMSPLIT_2G
Dinh Nguyen (4):
arm: socfpga: Add new device tree source for actual socfpga HW
arm: socfpga: Add entries to enable make dtbs socfpga
arm: Add v7_invalidate_l1 to cache-v7.S
arm: socfpga: Add SMP support for actual socfpga harware
.../bindings/arm/altera/socfpga-system.txt | 2 +
arch/arm/boot/dts/Makefile | 2 +
arch/arm/boot/dts/socfpga.dtsi | 22 +++----
arch/arm/boot/dts/socfpga_cyclone5.dts | 34 ++++++++++-
arch/arm/boot/dts/socfpga_vt.dts | 64 ++++++++++++++++++++
arch/arm/mach-imx/headsmp.S | 47 --------------
arch/arm/mach-shmobile/headsmp.S | 48 ---------------
arch/arm/mach-socfpga/core.h | 4 +-
arch/arm/mach-socfpga/headsmp.S | 16 +++--
arch/arm/mach-socfpga/platsmp.c | 19 +++---
arch/arm/mach-socfpga/socfpga.c | 7 ++-
arch/arm/mach-tegra/headsmp.S | 43 -------------
arch/arm/mm/cache-v7.S | 46 ++++++++++++++
13 files changed, 188 insertions(+), 166 deletions(-)
create mode 100644 arch/arm/boot/dts/socfpga_vt.dts
--
1.7.9.5
^ permalink raw reply [flat|nested] 8+ messages in thread* [PATCHv4 for soc 1/4] arm: socfpga: Add new device tree source for actual socfpga HW 2013-02-04 20:12 [PATCHv4 for soc 0/4] Enabling socfpga on hardware dinguyen at altera.com @ 2013-02-04 20:12 ` dinguyen at altera.com 2013-02-04 20:12 ` [PATCHv4 for soc 2/4] arm: socfpga: Add entries to enable make dtbs socfpga dinguyen at altera.com ` (3 subsequent siblings) 4 siblings, 0 replies; 8+ messages in thread From: dinguyen at altera.com @ 2013-02-04 20:12 UTC (permalink / raw) To: linux-arm-kernel From: Dinh Nguyen <dinguyen@altera.com> Up to this point, support for socfpga has only been on a virtual platform. Now that actual hardware is available, we add the appropriate device tree source files. Signed-off-by: Dinh Nguyen <dinguyen@altera.com> Tested-by: Pavel Machek <pavel@denx.de> Reviewed-by: Pavel Machek <pavel@denx.de> Cc: Russell King <linux@arm.linux.org.uk> Cc: Arnd Bergmann <arnd@arndb.de> Cc: Olof Johansson <olof@lixom.net> --- arch/arm/boot/dts/socfpga.dtsi | 22 ++++++------ arch/arm/boot/dts/socfpga_cyclone5.dts | 30 ++++++++++++++-- arch/arm/boot/dts/socfpga_vt.dts | 60 ++++++++++++++++++++++++++++++++ arch/arm/mach-socfpga/socfpga.c | 1 - 4 files changed, 98 insertions(+), 15 deletions(-) create mode 100644 arch/arm/boot/dts/socfpga_vt.dts diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi index 19aec42..936d230 100644 --- a/arch/arm/boot/dts/socfpga.dtsi +++ b/arch/arm/boot/dts/socfpga.dtsi @@ -25,6 +25,10 @@ ethernet0 = &gmac0; serial0 = &uart0; serial1 = &uart1; + timer0 = &timer0; + timer1 = &timer1; + timer2 = &timer2; + timer3 = &timer3; }; cpus { @@ -98,47 +102,41 @@ interrupts = <1 13 0xf04>; }; - timer0: timer at ffc08000 { + timer0: timer0 at ffc08000 { compatible = "snps,dw-apb-timer-sp"; interrupts = <0 167 4>; - clock-frequency = <200000000>; reg = <0xffc08000 0x1000>; }; - timer1: timer at ffc09000 { + timer1: timer1 at ffc09000 { compatible = "snps,dw-apb-timer-sp"; interrupts = <0 168 4>; - clock-frequency = <200000000>; reg = <0xffc09000 0x1000>; }; - timer2: timer at ffd00000 { + timer2: timer2 at ffd00000 { compatible = "snps,dw-apb-timer-osc"; interrupts = <0 169 4>; - clock-frequency = <200000000>; reg = <0xffd00000 0x1000>; }; - timer3: timer at ffd01000 { + timer3: timer3 at ffd01000 { compatible = "snps,dw-apb-timer-osc"; interrupts = <0 170 4>; - clock-frequency = <200000000>; reg = <0xffd01000 0x1000>; }; - uart0: uart at ffc02000 { + uart0: serial0 at ffc02000 { compatible = "snps,dw-apb-uart"; reg = <0xffc02000 0x1000>; - clock-frequency = <7372800>; interrupts = <0 162 4>; reg-shift = <2>; reg-io-width = <4>; }; - uart1: uart at ffc03000 { + uart1: serial1 at ffc03000 { compatible = "snps,dw-apb-uart"; reg = <0xffc03000 0x1000>; - clock-frequency = <7372800>; interrupts = <0 163 4>; reg-shift = <2>; reg-io-width = <4>; diff --git a/arch/arm/boot/dts/socfpga_cyclone5.dts b/arch/arm/boot/dts/socfpga_cyclone5.dts index ab7e4a9..7ad3cc6 100644 --- a/arch/arm/boot/dts/socfpga_cyclone5.dts +++ b/arch/arm/boot/dts/socfpga_cyclone5.dts @@ -20,7 +20,7 @@ / { model = "Altera SOCFPGA Cyclone V"; - compatible = "altr,socfpga-cyclone5"; + compatible = "altr,socfpga-cyclone5", "altr,socfpga"; chosen { bootargs = "console=ttyS0,57600"; @@ -29,6 +29,32 @@ memory { name = "memory"; device_type = "memory"; - reg = <0x0 0x10000000>; /* 256MB */ + reg = <0x0 0x40000000>; /* 1GB */ + }; + + soc { + timer0 at ffc08000 { + clock-frequency = <100000000>; + }; + + timer1 at ffc09000 { + clock-frequency = <100000000>; + }; + + timer2 at ffd00000 { + clock-frequency = <25000000>; + }; + + timer3 at ffd01000 { + clock-frequency = <25000000>; + }; + + serial0 at ffc02000 { + clock-frequency = <100000000>; + }; + + serial1 at ffc03000 { + clock-frequency = <100000000>; + }; }; }; diff --git a/arch/arm/boot/dts/socfpga_vt.dts b/arch/arm/boot/dts/socfpga_vt.dts new file mode 100644 index 0000000..a0c6c65 --- /dev/null +++ b/arch/arm/boot/dts/socfpga_vt.dts @@ -0,0 +1,60 @@ +/* + * Copyright (C) 2013 Altera Corporation <www.altera.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +/dts-v1/; +/include/ "socfpga.dtsi" + +/ { + model = "Altera SOCFPGA VT"; + compatible = "altr,socfpga-vt", "altr,socfpga"; + + chosen { + bootargs = "console=ttyS0,57600"; + }; + + memory { + name = "memory"; + device_type = "memory"; + reg = <0x0 0x40000000>; /* 1 GB */ + }; + + soc { + timer0 at ffc08000 { + clock-frequency = <7000000>; + }; + + timer1 at ffc09000 { + clock-frequency = <7000000>; + }; + + timer2 at ffd00000 { + clock-frequency = <7000000>; + }; + + timer3 at ffd01000 { + clock-frequency = <7000000>; + }; + + serial0 at ffc02000 { + clock-frequency = <7372800>; + }; + + serial1 at ffc03000 { + clock-frequency = <7372800>; + }; + }; +}; diff --git a/arch/arm/mach-socfpga/socfpga.c b/arch/arm/mach-socfpga/socfpga.c index 6732924..94aa6ad 100644 --- a/arch/arm/mach-socfpga/socfpga.c +++ b/arch/arm/mach-socfpga/socfpga.c @@ -98,7 +98,6 @@ static void __init socfpga_cyclone5_init(void) static const char *altera_dt_match[] = { "altr,socfpga", - "altr,socfpga-cyclone5", NULL }; -- 1.7.9.5 ^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCHv4 for soc 2/4] arm: socfpga: Add entries to enable make dtbs socfpga 2013-02-04 20:12 [PATCHv4 for soc 0/4] Enabling socfpga on hardware dinguyen at altera.com 2013-02-04 20:12 ` [PATCHv4 for soc 1/4] arm: socfpga: Add new device tree source for actual socfpga HW dinguyen at altera.com @ 2013-02-04 20:12 ` dinguyen at altera.com 2013-02-04 20:12 ` [PATCHv4 for soc 3/4] arm: Add v7_invalidate_l1 to cache-v7.S dinguyen at altera.com ` (2 subsequent siblings) 4 siblings, 0 replies; 8+ messages in thread From: dinguyen at altera.com @ 2013-02-04 20:12 UTC (permalink / raw) To: linux-arm-kernel From: Dinh Nguyen <dinguyen@altera.com> Signed-off-by: Dinh Nguyen <dinguyen@altera.com> Tested-by: Pavel Machek <pavel@denx.de> Reviewed-by: Pavel Machek <pavel@denx.de> Cc: Russell King <linux@arm.linux.org.uk> Cc: Arnd Bergmann <arnd@arndb.de> Cc: Olof Johansson <olof@lixom.net> Cc: Pavel Machek <pavel@denx.de> --- arch/arm/boot/dts/Makefile | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 5ebb44f..1b8276c 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -124,6 +124,8 @@ dtb-$(CONFIG_ARCH_SHMOBILE) += emev2-kzm9d.dtb \ r8a7740-armadillo800eva.dtb \ sh73a0-kzm9g.dtb \ sh7372-mackerel.dtb +dtb-$(CONFIG_ARCH_SOCFPGA) += socfpga_cyclone5.dtb \ + socfpga_vt.dtb dtb-$(CONFIG_ARCH_SPEAR13XX) += spear1310-evb.dtb \ spear1340-evb.dtb dtb-$(CONFIG_ARCH_SPEAR3XX)+= spear300-evb.dtb \ -- 1.7.9.5 ^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCHv4 for soc 3/4] arm: Add v7_invalidate_l1 to cache-v7.S 2013-02-04 20:12 [PATCHv4 for soc 0/4] Enabling socfpga on hardware dinguyen at altera.com 2013-02-04 20:12 ` [PATCHv4 for soc 1/4] arm: socfpga: Add new device tree source for actual socfpga HW dinguyen at altera.com 2013-02-04 20:12 ` [PATCHv4 for soc 2/4] arm: socfpga: Add entries to enable make dtbs socfpga dinguyen at altera.com @ 2013-02-04 20:12 ` dinguyen at altera.com 2013-02-04 20:12 ` [PATCHv4 for soc 4/4] arm: socfpga: Add SMP support for actual socfpga harware dinguyen at altera.com 2013-02-11 15:40 ` [PATCHv4 for soc 0/4] Enabling socfpga on hardware Dinh Nguyen 4 siblings, 0 replies; 8+ messages in thread From: dinguyen at altera.com @ 2013-02-04 20:12 UTC (permalink / raw) To: linux-arm-kernel From: Dinh Nguyen <dinguyen@altera.com> mach-socfpga is another platform that needs to use v7_invalidate_l1 to bringup additional cores. There was a comment that the ideal place for v7_invalidate_l1 should be in arm/mm/cache-v7.S Signed-off-by: Dinh Nguyen <dinguyen@altera.com> Acked-by: Simon Horman <horms+renesas@verge.net.au> Acked-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Pavel Machek <pavel@denx.de> Reviewed-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Tested-by: Pavel Machek <pavel@denx.de> Tested-by: Stephen Warren <swarren@nvidia.com> Cc: Arnd Bergmann <arnd@arndb.de> Cc: Russell King <linux@arm.linux.org.uk> Cc: Olof Johansson <olof@lixom.net> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Rob Herring <rob.herring@calxeda.com> Cc: Sascha Hauer <kernel@pengutronix.de> Cc: Magnus Damm <magnus.damm@gmail.com> --- arch/arm/mach-imx/headsmp.S | 47 ------------------------------------- arch/arm/mach-shmobile/headsmp.S | 48 -------------------------------------- arch/arm/mach-tegra/headsmp.S | 43 ---------------------------------- arch/arm/mm/cache-v7.S | 46 ++++++++++++++++++++++++++++++++++++ 4 files changed, 46 insertions(+), 138 deletions(-) diff --git a/arch/arm/mach-imx/headsmp.S b/arch/arm/mach-imx/headsmp.S index 7e49deb..921fc15 100644 --- a/arch/arm/mach-imx/headsmp.S +++ b/arch/arm/mach-imx/headsmp.S @@ -17,53 +17,6 @@ .section ".text.head", "ax" -/* - * The secondary kernel init calls v7_flush_dcache_all before it enables - * the L1; however, the L1 comes out of reset in an undefined state, so - * the clean + invalidate performed by v7_flush_dcache_all causes a bunch - * of cache lines with uninitialized data and uninitialized tags to get - * written out to memory, which does really unpleasant things to the main - * processor. We fix this by performing an invalidate, rather than a - * clean + invalidate, before jumping into the kernel. - * - * This funciton is cloned from arch/arm/mach-tegra/headsmp.S, and needs - * to be called for both secondary cores startup and primary core resume - * procedures. Ideally, it should be moved into arch/arm/mm/cache-v7.S. - */ -ENTRY(v7_invalidate_l1) - mov r0, #0 - mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache - mcr p15, 2, r0, c0, c0, 0 - mrc p15, 1, r0, c0, c0, 0 - - ldr r1, =0x7fff - and r2, r1, r0, lsr #13 - - ldr r1, =0x3ff - - and r3, r1, r0, lsr #3 @ NumWays - 1 - add r2, r2, #1 @ NumSets - - and r0, r0, #0x7 - add r0, r0, #4 @ SetShift - - clz r1, r3 @ WayShift - add r4, r3, #1 @ NumWays -1: sub r2, r2, #1 @ NumSets-- - mov r3, r4 @ Temp = NumWays -2: subs r3, r3, #1 @ Temp-- - mov r5, r3, lsl r1 - mov r6, r2, lsl r0 - orr r5, r5, r6 @ Reg = (Temp<<WayShift)|(NumSets<<SetShift) - mcr p15, 0, r5, c7, c6, 2 - bgt 2b - cmp r2, #0 - bgt 1b - dsb - isb - mov pc, lr -ENDPROC(v7_invalidate_l1) - #ifdef CONFIG_SMP ENTRY(v7_secondary_startup) bl v7_invalidate_l1 diff --git a/arch/arm/mach-shmobile/headsmp.S b/arch/arm/mach-shmobile/headsmp.S index b202c12..96001fd 100644 --- a/arch/arm/mach-shmobile/headsmp.S +++ b/arch/arm/mach-shmobile/headsmp.S @@ -16,54 +16,6 @@ __CPUINIT -/* Cache invalidation nicked from arch/arm/mach-imx/head-v7.S, thanks! - * - * The secondary kernel init calls v7_flush_dcache_all before it enables - * the L1; however, the L1 comes out of reset in an undefined state, so - * the clean + invalidate performed by v7_flush_dcache_all causes a bunch - * of cache lines with uninitialized data and uninitialized tags to get - * written out to memory, which does really unpleasant things to the main - * processor. We fix this by performing an invalidate, rather than a - * clean + invalidate, before jumping into the kernel. - * - * This funciton is cloned from arch/arm/mach-tegra/headsmp.S, and needs - * to be called for both secondary cores startup and primary core resume - * procedures. Ideally, it should be moved into arch/arm/mm/cache-v7.S. - */ -ENTRY(v7_invalidate_l1) - mov r0, #0 - mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache - mcr p15, 2, r0, c0, c0, 0 - mrc p15, 1, r0, c0, c0, 0 - - ldr r1, =0x7fff - and r2, r1, r0, lsr #13 - - ldr r1, =0x3ff - - and r3, r1, r0, lsr #3 @ NumWays - 1 - add r2, r2, #1 @ NumSets - - and r0, r0, #0x7 - add r0, r0, #4 @ SetShift - - clz r1, r3 @ WayShift - add r4, r3, #1 @ NumWays -1: sub r2, r2, #1 @ NumSets-- - mov r3, r4 @ Temp = NumWays -2: subs r3, r3, #1 @ Temp-- - mov r5, r3, lsl r1 - mov r6, r2, lsl r0 - orr r5, r5, r6 @ Reg = (Temp<<WayShift)|(NumSets<<SetShift) - mcr p15, 0, r5, c7, c6, 2 - bgt 2b - cmp r2, #0 - bgt 1b - dsb - isb - mov pc, lr -ENDPROC(v7_invalidate_l1) - ENTRY(shmobile_invalidate_start) bl v7_invalidate_l1 b secondary_startup diff --git a/arch/arm/mach-tegra/headsmp.S b/arch/arm/mach-tegra/headsmp.S index 4a317fa..fb082c4 100644 --- a/arch/arm/mach-tegra/headsmp.S +++ b/arch/arm/mach-tegra/headsmp.S @@ -18,49 +18,6 @@ .section ".text.head", "ax" __CPUINIT -/* - * Tegra specific entry point for secondary CPUs. - * The secondary kernel init calls v7_flush_dcache_all before it enables - * the L1; however, the L1 comes out of reset in an undefined state, so - * the clean + invalidate performed by v7_flush_dcache_all causes a bunch - * of cache lines with uninitialized data and uninitialized tags to get - * written out to memory, which does really unpleasant things to the main - * processor. We fix this by performing an invalidate, rather than a - * clean + invalidate, before jumping into the kernel. - */ -ENTRY(v7_invalidate_l1) - mov r0, #0 - mcr p15, 2, r0, c0, c0, 0 - mrc p15, 1, r0, c0, c0, 0 - - ldr r1, =0x7fff - and r2, r1, r0, lsr #13 - - ldr r1, =0x3ff - - and r3, r1, r0, lsr #3 @ NumWays - 1 - add r2, r2, #1 @ NumSets - - and r0, r0, #0x7 - add r0, r0, #4 @ SetShift - - clz r1, r3 @ WayShift - add r4, r3, #1 @ NumWays -1: sub r2, r2, #1 @ NumSets-- - mov r3, r4 @ Temp = NumWays -2: subs r3, r3, #1 @ Temp-- - mov r5, r3, lsl r1 - mov r6, r2, lsl r0 - orr r5, r5, r6 @ Reg = (Temp<<WayShift)|(NumSets<<SetShift) - mcr p15, 0, r5, c7, c6, 2 - bgt 2b - cmp r2, #0 - bgt 1b - dsb - isb - mov pc, lr -ENDPROC(v7_invalidate_l1) - ENTRY(tegra_secondary_startup) bl v7_invalidate_l1 diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S index 7539ec2..15451ee 100644 --- a/arch/arm/mm/cache-v7.S +++ b/arch/arm/mm/cache-v7.S @@ -19,6 +19,52 @@ #include "proc-macros.S" /* + * The secondary kernel init calls v7_flush_dcache_all before it enables + * the L1; however, the L1 comes out of reset in an undefined state, so + * the clean + invalidate performed by v7_flush_dcache_all causes a bunch + * of cache lines with uninitialized data and uninitialized tags to get + * written out to memory, which does really unpleasant things to the main + * processor. We fix this by performing an invalidate, rather than a + * clean + invalidate, before jumping into the kernel. + * + * This function is cloned from arch/arm/mach-tegra/headsmp.S, and needs + * to be called for both secondary cores startup and primary core resume + * procedures. + */ +ENTRY(v7_invalidate_l1) + mov r0, #0 + mcr p15, 2, r0, c0, c0, 0 + mrc p15, 1, r0, c0, c0, 0 + + ldr r1, =0x7fff + and r2, r1, r0, lsr #13 + + ldr r1, =0x3ff + + and r3, r1, r0, lsr #3 @ NumWays - 1 + add r2, r2, #1 @ NumSets + + and r0, r0, #0x7 + add r0, r0, #4 @ SetShift + + clz r1, r3 @ WayShift + add r4, r3, #1 @ NumWays +1: sub r2, r2, #1 @ NumSets-- + mov r3, r4 @ Temp = NumWays +2: subs r3, r3, #1 @ Temp-- + mov r5, r3, lsl r1 + mov r6, r2, lsl r0 + orr r5, r5, r6 @ Reg = (Temp<<WayShift)|(NumSets<<SetShift) + mcr p15, 0, r5, c7, c6, 2 + bgt 2b + cmp r2, #0 + bgt 1b + dsb + isb + mov pc, lr +ENDPROC(v7_invalidate_l1) + +/* * v7_flush_icache_all() * * Flush the whole I-cache. -- 1.7.9.5 ^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCHv4 for soc 4/4] arm: socfpga: Add SMP support for actual socfpga harware 2013-02-04 20:12 [PATCHv4 for soc 0/4] Enabling socfpga on hardware dinguyen at altera.com ` (2 preceding siblings ...) 2013-02-04 20:12 ` [PATCHv4 for soc 3/4] arm: Add v7_invalidate_l1 to cache-v7.S dinguyen at altera.com @ 2013-02-04 20:12 ` dinguyen at altera.com 2013-02-11 22:16 ` Olof Johansson 2013-02-11 15:40 ` [PATCHv4 for soc 0/4] Enabling socfpga on hardware Dinh Nguyen 4 siblings, 1 reply; 8+ messages in thread From: dinguyen at altera.com @ 2013-02-04 20:12 UTC (permalink / raw) To: linux-arm-kernel From: Dinh Nguyen <dinguyen@altera.com> Because the CPU1 start address is different for socfpga-vt and socfpga-cyclone5, we add code to use the correct CPU1 start addr. Signed-off-by: Dinh Nguyen <dinguyen@altera.com> Signed-off-by: Pavel Machek <pavel@denx.de> Cc: Russell King <linux@arm.linux.org.uk> Cc: Arnd Bergmann <arnd@arndb.de> Cc: Olof Johansson <olof@lixom.net> Cc: Rob Herring <rob.herring@calxeda.com> Cc: Grant Likely <grant.likely@secretlab.ca> --- .../bindings/arm/altera/socfpga-system.txt | 2 ++ arch/arm/boot/dts/socfpga_cyclone5.dts | 4 ++++ arch/arm/boot/dts/socfpga_vt.dts | 4 ++++ arch/arm/mach-socfpga/core.h | 4 +++- arch/arm/mach-socfpga/headsmp.S | 16 ++++++++++++---- arch/arm/mach-socfpga/platsmp.c | 17 ++++++++++------- arch/arm/mach-socfpga/socfpga.c | 6 ++++++ 7 files changed, 41 insertions(+), 12 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/altera/socfpga-system.txt b/Documentation/devicetree/bindings/arm/altera/socfpga-system.txt index 07c65e3..f4d04a0 100644 --- a/Documentation/devicetree/bindings/arm/altera/socfpga-system.txt +++ b/Documentation/devicetree/bindings/arm/altera/socfpga-system.txt @@ -3,9 +3,11 @@ Altera SOCFPGA System Manager Required properties: - compatible : "altr,sys-mgr" - reg : Should contain 1 register ranges(address and length) +- cpu1-start-addr : CPU1 start address in hex. Example: sysmgr at ffd08000 { compatible = "altr,sys-mgr"; reg = <0xffd08000 0x1000>; + cpu1-start-addr = <0xffd080c4>; }; diff --git a/arch/arm/boot/dts/socfpga_cyclone5.dts b/arch/arm/boot/dts/socfpga_cyclone5.dts index 7ad3cc6..3ae8a83 100644 --- a/arch/arm/boot/dts/socfpga_cyclone5.dts +++ b/arch/arm/boot/dts/socfpga_cyclone5.dts @@ -56,5 +56,9 @@ serial1 at ffc03000 { clock-frequency = <100000000>; }; + + sysmgr at ffd08000 { + cpu1-start-addr = <0xffd080c4>; + }; }; }; diff --git a/arch/arm/boot/dts/socfpga_vt.dts b/arch/arm/boot/dts/socfpga_vt.dts index a0c6c65..1036eba 100644 --- a/arch/arm/boot/dts/socfpga_vt.dts +++ b/arch/arm/boot/dts/socfpga_vt.dts @@ -56,5 +56,9 @@ serial1 at ffc03000 { clock-frequency = <7372800>; }; + + sysmgr at ffd08000 { + cpu1-start-addr = <0xffd08010>; + }; }; }; diff --git a/arch/arm/mach-socfpga/core.h b/arch/arm/mach-socfpga/core.h index 9941caa..5b76dd4 100644 --- a/arch/arm/mach-socfpga/core.h +++ b/arch/arm/mach-socfpga/core.h @@ -20,7 +20,7 @@ #ifndef __MACH_CORE_H #define __MACH_CORE_H -extern void secondary_startup(void); +extern void v7_secondary_startup(void); extern void __iomem *socfpga_scu_base_addr; extern void socfpga_init_clocks(void); @@ -29,6 +29,8 @@ extern void socfpga_sysmgr_init(void); extern struct smp_operations socfpga_smp_ops; extern char secondary_trampoline, secondary_trampoline_end; +extern unsigned long cpu1start_addr; + #define SOCFPGA_SCU_VIRT_BASE 0xfffec000 #endif diff --git a/arch/arm/mach-socfpga/headsmp.S b/arch/arm/mach-socfpga/headsmp.S index f09b128..3c83582 100644 --- a/arch/arm/mach-socfpga/headsmp.S +++ b/arch/arm/mach-socfpga/headsmp.S @@ -13,13 +13,21 @@ __CPUINIT .arch armv7-a -#define CPU1_START_ADDR 0xffd08010 - ENTRY(secondary_trampoline) - movw r0, #:lower16:CPU1_START_ADDR - movt r0, #:upper16:CPU1_START_ADDR + movw r2, #:lower16:cpu1start_addr + movt r2, #:upper16:cpu1start_addr + + /* The socfpga VT cannot handle a 0xC0000000 page offset when loading + the cpu1start_addr, we bit clear it. Tested on HW and VT. */ + bic r2, r2, #0x40000000 + ldr r0, [r2] ldr r1, [r0] bx r1 ENTRY(secondary_trampoline_end) + +ENTRY(v7_secondary_startup) + bl v7_invalidate_l1 + b secondary_startup +ENDPROC(v7_secondary_startup) diff --git a/arch/arm/mach-socfpga/platsmp.c b/arch/arm/mach-socfpga/platsmp.c index 68dd1b6..d89bc67 100644 --- a/arch/arm/mach-socfpga/platsmp.c +++ b/arch/arm/mach-socfpga/platsmp.c @@ -47,16 +47,19 @@ static int __cpuinit socfpga_boot_secondary(unsigned int cpu, struct task_struct { int trampoline_size = &secondary_trampoline_end - &secondary_trampoline; - memcpy(phys_to_virt(0), &secondary_trampoline, trampoline_size); + if (cpu1start_addr) { + memcpy(phys_to_virt(0), &secondary_trampoline, trampoline_size); - __raw_writel(virt_to_phys(secondary_startup), (sys_manager_base_addr+0x10)); + __raw_writel(virt_to_phys(v7_secondary_startup), + (sys_manager_base_addr + (cpu1start_addr & 0x000000ff))); - flush_cache_all(); - smp_wmb(); - outer_clean_range(0, trampoline_size); + flush_cache_all(); + smp_wmb(); + outer_clean_range(0, trampoline_size); - /* This will release CPU #1 out of reset.*/ - __raw_writel(0, rst_manager_base_addr + 0x10); + /* This will release CPU #1 out of reset.*/ + __raw_writel(0, rst_manager_base_addr + 0x10); + } return 0; } diff --git a/arch/arm/mach-socfpga/socfpga.c b/arch/arm/mach-socfpga/socfpga.c index 94aa6ad..cec1266 100644 --- a/arch/arm/mach-socfpga/socfpga.c +++ b/arch/arm/mach-socfpga/socfpga.c @@ -29,6 +29,7 @@ void __iomem *socfpga_scu_base_addr = ((void __iomem *)(SOCFPGA_SCU_VIRT_BASE)); void __iomem *sys_manager_base_addr; void __iomem *rst_manager_base_addr; +unsigned long cpu1start_addr; static struct map_desc scu_io_desc __initdata = { .virtual = SOCFPGA_SCU_VIRT_BASE, @@ -72,6 +73,11 @@ void __init socfpga_sysmgr_init(void) struct device_node *np; np = of_find_compatible_node(NULL, NULL, "altr,sys-mgr"); + + if (of_property_read_u32(np, "cpu1-start-addr", + (u32 *) &cpu1start_addr)) + pr_err("SMP: Need cpu1-start-addr in device tree.\n"); + sys_manager_base_addr = of_iomap(np, 0); np = of_find_compatible_node(NULL, NULL, "altr,rst-mgr"); -- 1.7.9.5 ^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCHv4 for soc 4/4] arm: socfpga: Add SMP support for actual socfpga harware 2013-02-04 20:12 ` [PATCHv4 for soc 4/4] arm: socfpga: Add SMP support for actual socfpga harware dinguyen at altera.com @ 2013-02-11 22:16 ` Olof Johansson 0 siblings, 0 replies; 8+ messages in thread From: Olof Johansson @ 2013-02-11 22:16 UTC (permalink / raw) To: linux-arm-kernel Hi, On Mon, Feb 04, 2013 at 02:12:11PM -0600, dinguyen at altera.com wrote: > diff --git a/arch/arm/mach-socfpga/headsmp.S b/arch/arm/mach-socfpga/headsmp.S > index f09b128..3c83582 100644 > --- a/arch/arm/mach-socfpga/headsmp.S > +++ b/arch/arm/mach-socfpga/headsmp.S > @@ -13,13 +13,21 @@ > __CPUINIT > .arch armv7-a > > -#define CPU1_START_ADDR 0xffd08010 > - > ENTRY(secondary_trampoline) > - movw r0, #:lower16:CPU1_START_ADDR > - movt r0, #:upper16:CPU1_START_ADDR > + movw r2, #:lower16:cpu1start_addr > + movt r2, #:upper16:cpu1start_addr > + > + /* The socfpga VT cannot handle a 0xC0000000 page offset when loading > + the cpu1start_addr, we bit clear it. Tested on HW and VT. */ > + bic r2, r2, #0x40000000 > > + ldr r0, [r2] > ldr r1, [r0] > bx r1 > > ENTRY(secondary_trampoline_end) > + > +ENTRY(v7_secondary_startup) > + bl v7_invalidate_l1 > + b secondary_startup > +ENDPROC(v7_secondary_startup) This breaks multiplatform where you build i.MX and socfpga together, since both implement and export a v7_secondary_startup: arch/arm/mach-socfpga/built-in.o: In function `v7_secondary_startup': platsmp.c:(.cpuinit.text+0x18): multiple definition of `v7_secondary_startup' arch/arm/mach-imx/built-in.o:platform-imx-dma.c:(.text.head+0x0): first defined here It makes sense to rename this to socfpga_secondary_startup instead, or move to a common location. -Olof ^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCHv4 for soc 0/4] Enabling socfpga on hardware 2013-02-04 20:12 [PATCHv4 for soc 0/4] Enabling socfpga on hardware dinguyen at altera.com ` (3 preceding siblings ...) 2013-02-04 20:12 ` [PATCHv4 for soc 4/4] arm: socfpga: Add SMP support for actual socfpga harware dinguyen at altera.com @ 2013-02-11 15:40 ` Dinh Nguyen 2013-02-11 22:17 ` Olof Johansson 4 siblings, 1 reply; 8+ messages in thread From: Dinh Nguyen @ 2013-02-11 15:40 UTC (permalink / raw) To: linux-arm-kernel Hi Olof, I was wondering if you or Arnd can apply this series to the arm-soc branch? On Mon, 2013-02-04 at 14:12 -0600, Dinh Nguyen wrote: > From: Dinh Nguyen <dinguyen@altera.com> > > V4: > - Check for cpu1start_addr is valid in socfpga_boot_secondary() > - Add Reviewed-by: Reviewed-by: Santosh Shilimkar <santosh.shilimkar@ti.com> for 3/4 > > V3: > - Addressed comments from Olof Johansson and Russell King > - Received Acked-by and Tested-by Stephen Warren > - Received Signed-off-by Pavel Machek > > V2: > - Remove patch that adds clock entries in the socfpga.dtsi as this > should accompany a rework in drivers/clk and will done in a different > patch series. > - Removed I-cache invalidate from v7_invalidate_l1 > - Defined cpu1-start-addr as a device tree entry > - Removed the need to use CONFIG_VMSPLIT_2G > > Dinh Nguyen (4): > arm: socfpga: Add new device tree source for actual socfpga HW > arm: socfpga: Add entries to enable make dtbs socfpga > arm: Add v7_invalidate_l1 to cache-v7.S > arm: socfpga: Add SMP support for actual socfpga harware > > .../bindings/arm/altera/socfpga-system.txt | 2 + > arch/arm/boot/dts/Makefile | 2 + > arch/arm/boot/dts/socfpga.dtsi | 22 +++---- > arch/arm/boot/dts/socfpga_cyclone5.dts | 34 ++++++++++- > arch/arm/boot/dts/socfpga_vt.dts | 64 ++++++++++++++++++++ > arch/arm/mach-imx/headsmp.S | 47 -------------- > arch/arm/mach-shmobile/headsmp.S | 48 --------------- > arch/arm/mach-socfpga/core.h | 4 +- > arch/arm/mach-socfpga/headsmp.S | 16 +++-- > arch/arm/mach-socfpga/platsmp.c | 19 +++--- > arch/arm/mach-socfpga/socfpga.c | 7 ++- > arch/arm/mach-tegra/headsmp.S | 43 ------------- > arch/arm/mm/cache-v7.S | 46 ++++++++++++++ > 13 files changed, 188 insertions(+), 166 deletions(-) > create mode 100644 arch/arm/boot/dts/socfpga_vt.dts > Thanks, Dinh ^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCHv4 for soc 0/4] Enabling socfpga on hardware 2013-02-11 15:40 ` [PATCHv4 for soc 0/4] Enabling socfpga on hardware Dinh Nguyen @ 2013-02-11 22:17 ` Olof Johansson 0 siblings, 0 replies; 8+ messages in thread From: Olof Johansson @ 2013-02-11 22:17 UTC (permalink / raw) To: linux-arm-kernel On Mon, Feb 11, 2013 at 09:40:34AM -0600, Dinh Nguyen wrote: > Hi Olof, > > I was wondering if you or Arnd can apply this series to the arm-soc > branch? Hi, See new comment on one of the patches, I applied them and enabled in a multi_v7_defconfig build but hit a symbol name conflict. Please fix, I'll be happy to apply the patches after. -Olof ^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2013-02-11 22:17 UTC | newest] Thread overview: 8+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2013-02-04 20:12 [PATCHv4 for soc 0/4] Enabling socfpga on hardware dinguyen at altera.com 2013-02-04 20:12 ` [PATCHv4 for soc 1/4] arm: socfpga: Add new device tree source for actual socfpga HW dinguyen at altera.com 2013-02-04 20:12 ` [PATCHv4 for soc 2/4] arm: socfpga: Add entries to enable make dtbs socfpga dinguyen at altera.com 2013-02-04 20:12 ` [PATCHv4 for soc 3/4] arm: Add v7_invalidate_l1 to cache-v7.S dinguyen at altera.com 2013-02-04 20:12 ` [PATCHv4 for soc 4/4] arm: socfpga: Add SMP support for actual socfpga harware dinguyen at altera.com 2013-02-11 22:16 ` Olof Johansson 2013-02-11 15:40 ` [PATCHv4 for soc 0/4] Enabling socfpga on hardware Dinh Nguyen 2013-02-11 22:17 ` Olof Johansson
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