[PATCH 0/4] ARM: at91: pm: add ULP1 mode support

[PATCH 0/4] ARM: at91: pm: add ULP1 mode support

[Wenyou Yang]

The ULP1 (Ultra Low-power mode 1) is introduced by SAMA5D2.

In order to achieve the lowest power consumption, in the ULP1 mode,
all the clocks are shut off, inclusive the embedded 12MHz RC oscillator.

The fast startup signal is used as a wake up source for ULP1 mode.
As soon as the wake up event is asserted, the embedded 12MHz RC
oscillator restarts automatically, which fast startup signal
to trigger the PMC to wake up the system from the ULP1 mode can be
configured via DT.

It is based on the following patch set:
	http://lists.infradead.org/pipermail/linux-arm-kernel/2015-December/390954.html


Wenyou Yang (4):
  ARM: at91: pm: create a separate procedure for the ULP0 mode
  ARM: at91: pm: add ULP1 mode support
  ARM: at91: pm: configure PMC fast startup signals
  Documentation: atmel-at91: add DT bindings for fast startup

 .../devicetree/bindings/arm/atmel-pmc.txt          |   74 +++++++++
 arch/arm/mach-at91/pm.c                            |  112 +++++++++++++-
 arch/arm/mach-at91/pm.h                            |    7 +
 arch/arm/mach-at91/pm_suspend.S                    |  158 +++++++++++++++++---
 include/linux/clk/at91_pmc.h                       |   36 +++++
 5 files changed, 362 insertions(+), 25 deletions(-)

-- 
1.7.9.5

[PATCH 1/4] ARM: at91: pm: create a separate procedure for the ULP0 mode

[Wenyou Yang]

To make the code more legible and prepare to add the ULP1 mode
support in the future, create a separate procedure for the ULP0 mode.

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
---

 arch/arm/mach-at91/pm_suspend.S |   65 ++++++++++++++++++++++++---------------
 1 file changed, 40 insertions(+), 25 deletions(-)

diff --git a/arch/arm/mach-at91/pm_suspend.S b/arch/arm/mach-at91/pm_suspend.S
index a25defd..5fcffdc 100644
--- a/arch/arm/mach-at91/pm_suspend.S
+++ b/arch/arm/mach-at91/pm_suspend.S
@@ -107,7 +107,7 @@ ENTRY(at91_pm_suspend_in_sram)
 
 	ldr	r0, .pm_mode
 	tst	r0, #AT91_PM_SLOW_CLOCK
-	beq	skip_disable_main_clock
+	beq	standby_mode
 
 	ldr	pmc, .pmc_base
 
@@ -131,32 +131,13 @@ ENTRY(at91_pm_suspend_in_sram)
 	orr	tmp1, tmp1, #(1 << 29)		/* bit 29 always set */
 	str	tmp1, [pmc, #AT91_CKGR_PLLAR]
 
-	/* Turn off the main oscillator */
-	ldr	tmp1, [pmc, #AT91_CKGR_MOR]
-	bic	tmp1, tmp1, #AT91_PMC_MOSCEN
-	orr	tmp1, tmp1, #AT91_PMC_KEY
-	str	tmp1, [pmc, #AT91_CKGR_MOR]
-
-skip_disable_main_clock:
-	ldr	pmc, .pmc_base
-
-	/* Wait for interrupt */
-	at91_cpu_idle
-
-	ldr	r0, .pm_mode
-	tst	r0, #AT91_PM_SLOW_CLOCK
-	beq	skip_enable_main_clock
+ulp0_mode:
+	bl	at91_pm_ulp0_mode
+	b	ulp_exit
 
+ulp_exit:
 	ldr	pmc, .pmc_base
 
-	/* Turn on the main oscillator */
-	ldr	tmp1, [pmc, #AT91_CKGR_MOR]
-	orr	tmp1, tmp1, #AT91_PMC_MOSCEN
-	orr	tmp1, tmp1, #AT91_PMC_KEY
-	str	tmp1, [pmc, #AT91_CKGR_MOR]
-
-	wait_moscrdy
-
 	/* Restore PLLA setting */
 	ldr	tmp1, .saved_pllar
 	str	tmp1, [pmc, #AT91_CKGR_PLLAR]
@@ -177,7 +158,15 @@ skip_disable_main_clock:
 
 	wait_mckrdy
 
-skip_enable_main_clock:
+	b	pm_exit
+
+standby_mode:
+	ldr	pmc, .pmc_base
+
+	/* Wait for interrupt */
+	at91_cpu_idle
+
+pm_exit:
 	/* Exit the self-refresh mode */
 	mov	r0, #SRAMC_SELF_FRESH_EXIT
 	bl	at91_sramc_self_refresh
@@ -311,6 +300,32 @@ exit_sramc_sf:
 	mov	pc, lr
 ENDPROC(at91_sramc_self_refresh)
 
+/*
+ * void at91_pm_ulp0_mode(void)
+ */
+ENTRY(at91_pm_ulp0_mode)
+	ldr	pmc, .pmc_base
+
+	/* Turn off the crystal oscillator */
+	ldr	tmp1, [pmc, #AT91_CKGR_MOR]
+	bic	tmp1, tmp1, #AT91_PMC_MOSCEN
+	orr	tmp1, tmp1, #AT91_PMC_KEY
+	str	tmp1, [pmc, #AT91_CKGR_MOR]
+
+	/* Wait for interrupt */
+	at91_cpu_idle
+
+	/* Turn on the crystal oscillator */
+	ldr	tmp1, [pmc, #AT91_CKGR_MOR]
+	orr	tmp1, tmp1, #AT91_PMC_MOSCEN
+	orr	tmp1, tmp1, #AT91_PMC_KEY
+	str	tmp1, [pmc, #AT91_CKGR_MOR]
+
+	wait_moscrdy
+
+	mov	pc, lr
+ENDPROC(at91_pm_ulp0_mode)
+
 .pmc_base:
 	.word 0
 .sramc_base:
-- 
1.7.9.5

[PATCH 2/4] ARM: at91: pm: add ULP1 mode support

[Wenyou Yang]

The ULP1 (Ultra Low-power mode 1) is introduced by SAMA5D2.

In the ULP1 mode, all the clocks are shut off, inclusive the embedded
12MHz RC oscillator, so as to achieve the lowest power consumption
with the system in retention mode and able to resume on the wake up
events. As soon as the wake up event is asserted, the embedded 12MHz
RC oscillator restarts automatically.

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
---

 arch/arm/mach-at91/pm.c         |   16 ++++++-
 arch/arm/mach-at91/pm.h         |    7 +++
 arch/arm/mach-at91/pm_suspend.S |   97 +++++++++++++++++++++++++++++++++++++++
 include/linux/clk/at91_pmc.h    |    4 ++
 4 files changed, 122 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c
index f82df15..a7aec35 100644
--- a/arch/arm/mach-at91/pm.c
+++ b/arch/arm/mach-at91/pm.c
@@ -36,6 +36,11 @@
 #include "generic.h"
 #include "pm.h"
 
+#define ULP0_MODE	0x00
+#define ULP1_MODE	0x11
+
+#define SAMA5D2_PMC_VERSION	0x20540
+
 void __iomem *pmc;
 
 /*
@@ -52,6 +57,7 @@ extern void at91_pinctrl_gpio_resume(void);
 static struct {
 	unsigned long uhp_udp_mask;
 	int memctrl;
+	u32 ulp_mode;
 } at91_pm_data;
 
 void __iomem *at91_ramc_base[2];
@@ -141,8 +147,11 @@ static void at91_pm_suspend(suspend_state_t state)
 {
 	unsigned int pm_data = at91_pm_data.memctrl;
 
-	pm_data |= (state == PM_SUSPEND_MEM) ?
-				AT91_PM_MODE(AT91_PM_SLOW_CLOCK) : 0;
+	if (state == PM_SUSPEND_MEM) {
+		pm_data |= AT91_PM_MODE(AT91_PM_SLOW_CLOCK);
+		if (at91_pm_data.ulp_mode == ULP1_MODE)
+			pm_data |= AT91_PM_ULP(AT91_PM_ULP1_MODE);
+	}
 
 	flush_cache_all();
 	outer_disable();
@@ -497,4 +506,7 @@ void __init sama5_pm_init(void)
 	at91_pm_data.uhp_udp_mask = AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP;
 	at91_pm_data.memctrl = AT91_MEMCTRL_DDRSDR;
 	at91_pm_init(NULL);
+
+	if (readl(pmc + AT91_PMC_VERSION) >= SAMA5D2_PMC_VERSION)
+		at91_pm_data.ulp_mode = ULP1_MODE;
 }
diff --git a/arch/arm/mach-at91/pm.h b/arch/arm/mach-at91/pm.h
index 3fcf881..2e76745 100644
--- a/arch/arm/mach-at91/pm.h
+++ b/arch/arm/mach-at91/pm.h
@@ -39,4 +39,11 @@ extern void __iomem *at91_ramc_base[];
 
 #define	AT91_PM_SLOW_CLOCK	0x01
 
+#define AT91_PM_ULP_OFFSET	5
+#define AT91_PM_ULP_MASK	0x03
+#define AT91_PM_ULP(x)		(((x) & AT91_PM_ULP_MASK) << AT91_PM_ULP_OFFSET)
+
+#define AT91_PM_ULP0_MODE	0x00
+#define AT91_PM_ULP1_MODE	0x01
+
 #endif
diff --git a/arch/arm/mach-at91/pm_suspend.S b/arch/arm/mach-at91/pm_suspend.S
index 5fcffdc..20f4303 100644
--- a/arch/arm/mach-at91/pm_suspend.S
+++ b/arch/arm/mach-at91/pm_suspend.S
@@ -41,6 +41,15 @@ tmp2	.req	r5
 	.endm
 
 /*
+ * Wait for main oscillator selection is done
+ */
+	.macro wait_moscsels
+1:	ldr	tmp1, [pmc, #AT91_PMC_SR]
+	tst	tmp1, #AT91_PMC_MOSCSELS
+	beq	1b
+	.endm
+
+/*
  * Wait until PLLA has locked.
  */
 	.macro wait_pllalock
@@ -101,6 +110,10 @@ ENTRY(at91_pm_suspend_in_sram)
 	and	r0, r0, #AT91_PM_MODE_MASK
 	str	r0, .pm_mode
 
+	lsr	r0, r3, #AT91_PM_ULP_OFFSET
+	and	r0, r0, #AT91_PM_ULP_MASK
+	str	r0, .ulp_mode
+
 	/* Active the self-refresh mode */
 	mov	r0, #SRAMC_SELF_FRESH_ACTIVE
 	bl	at91_sramc_self_refresh
@@ -131,6 +144,13 @@ ENTRY(at91_pm_suspend_in_sram)
 	orr	tmp1, tmp1, #(1 << 29)		/* bit 29 always set */
 	str	tmp1, [pmc, #AT91_CKGR_PLLAR]
 
+	ldr	r0, .ulp_mode
+	tst	r0, #AT91_PM_ULP1_MODE
+	beq	ulp0_mode
+
+	bl	at91_pm_ulp1_mode
+	b	pm_exit
+
 ulp0_mode:
 	bl	at91_pm_ulp0_mode
 	b	ulp_exit
@@ -326,6 +346,81 @@ ENTRY(at91_pm_ulp0_mode)
 	mov	pc, lr
 ENDPROC(at91_pm_ulp0_mode)
 
+/*
+ * void at91_pm_ulp1_mode(void)
+ */
+ENTRY(at91_pm_ulp1_mode)
+	ldr	pmc, .pmc_base
+
+	/* Switch the main clock source to 12-MHz RC oscillator */
+	ldr	tmp1, [pmc, #AT91_CKGR_MOR]
+	bic	tmp1, tmp1, #AT91_PMC_MOSCSEL
+	bic	tmp1, tmp1, #AT91_PMC_KEY_MASK
+	orr	tmp1, tmp1, #AT91_PMC_KEY
+	str	tmp1, [pmc, #AT91_CKGR_MOR]
+
+	wait_moscsels
+
+	/* Disable the crystal oscillator */
+	ldr	tmp1, [pmc, #AT91_CKGR_MOR]
+	bic	tmp1, tmp1, #AT91_PMC_MOSCEN
+	bic	tmp1, tmp1, #AT91_PMC_KEY_MASK
+	orr	tmp1, tmp1, #AT91_PMC_KEY
+	str	tmp1, [pmc, #AT91_CKGR_MOR]
+
+	/* Switch the master clock source to main clock */
+	ldr	tmp1, [pmc, #AT91_PMC_MCKR]
+	bic	tmp1, tmp1, #AT91_PMC_CSS
+	orr	tmp1, tmp1, #AT91_PMC_CSS_MAIN
+	str	tmp1, [pmc, #AT91_PMC_MCKR]
+
+	wait_mckrdy
+
+	/* Enter the ULP1 mode by set WAITMODE bit in CKGR_MOR */
+	ldr	tmp1, [pmc, #AT91_CKGR_MOR]
+	orr	tmp1, tmp1, #AT91_PMC_WAITMODE
+	bic	tmp1, tmp1, #AT91_PMC_KEY_MASK
+	orr	tmp1, tmp1, #AT91_PMC_KEY
+	str	tmp1, [pmc, #AT91_CKGR_MOR]
+
+	wait_mckrdy
+
+	/* Enable the crystal oscillator */
+	ldr	tmp1, [pmc, #AT91_CKGR_MOR]
+	orr	tmp1, tmp1, #AT91_PMC_MOSCEN
+	bic	tmp1, tmp1, #AT91_PMC_KEY_MASK
+	orr	tmp1, tmp1, #AT91_PMC_KEY
+	str	tmp1, [pmc, #AT91_CKGR_MOR]
+
+	wait_moscrdy
+
+	/* Switch the master clock source to slow clock */
+	ldr	tmp1, [pmc, #AT91_PMC_MCKR]
+	bic	tmp1, tmp1, #AT91_PMC_CSS
+	str	tmp1, [pmc, #AT91_PMC_MCKR]
+
+	wait_mckrdy
+
+	/* Switch main clock source to crystal oscillator */
+	ldr	tmp1, [pmc, #AT91_CKGR_MOR]
+	orr	tmp1, tmp1, #AT91_PMC_MOSCSEL
+	bic	tmp1, tmp1, #AT91_PMC_KEY_MASK
+	orr	tmp1, tmp1, #AT91_PMC_KEY
+	str	tmp1, [pmc, #AT91_CKGR_MOR]
+
+	wait_moscsels
+
+	/* Switch the master clock source to main clock */
+	ldr	tmp1, [pmc, #AT91_PMC_MCKR]
+	bic	tmp1, tmp1, #AT91_PMC_CSS
+	orr	tmp1, tmp1, #AT91_PMC_CSS_MAIN
+	str	tmp1, [pmc, #AT91_PMC_MCKR]
+
+	wait_mckrdy
+
+	mov	pc, lr
+ENDPROC(at91_pm_ulp1_mode)
+
 .pmc_base:
 	.word 0
 .sramc_base:
@@ -336,6 +431,8 @@ ENDPROC(at91_pm_ulp0_mode)
 	.word 0
 .pm_mode:
 	.word 0
+.ulp_mode:
+	.word 0
 .saved_mckr:
 	.word 0
 .saved_pllar:
diff --git a/include/linux/clk/at91_pmc.h b/include/linux/clk/at91_pmc.h
index 17f413b..4afd891 100644
--- a/include/linux/clk/at91_pmc.h
+++ b/include/linux/clk/at91_pmc.h
@@ -47,8 +47,10 @@
 #define	AT91_CKGR_MOR		0x20			/* Main Oscillator Register [not on SAM9RL] */
 #define		AT91_PMC_MOSCEN		(1    <<  0)		/* Main Oscillator Enable */
 #define		AT91_PMC_OSCBYPASS	(1    <<  1)		/* Oscillator Bypass */
+#define		AT91_PMC_WAITMODE	(1    <<  2)		/* Wait Mode Command */
 #define		AT91_PMC_MOSCRCEN	(1    <<  3)		/* Main On-Chip RC Oscillator Enable [some SAM9] */
 #define		AT91_PMC_OSCOUNT	(0xff <<  8)		/* Main Oscillator Start-up Time */
+#define		AT91_PMC_KEY_MASK	(0xff << 16)
 #define		AT91_PMC_KEY		(0x37 << 16)		/* MOR Writing Key */
 #define		AT91_PMC_MOSCSEL	(1    << 24)		/* Main Oscillator Selection [some SAM9] */
 #define		AT91_PMC_CFDEN		(1    << 25)		/* Clock Failure Detector Enable [some SAM9] */
@@ -166,6 +168,8 @@
 #define		AT91_PMC_WPVS		(0x1  <<  0)		/* Write Protect Violation Status */
 #define		AT91_PMC_WPVSRC		(0xffff  <<  8)		/* Write Protect Violation Source */
 
+#define AT91_PMC_VERSION	0xfc
+
 #define AT91_PMC_PCER1		0x100			/* Peripheral Clock Enable Register 1 [SAMA5 only]*/
 #define AT91_PMC_PCDR1		0x104			/* Peripheral Clock Enable Register 1 */
 #define AT91_PMC_PCSR1		0x108			/* Peripheral Clock Enable Register 1 */
-- 
1.7.9.5

[PATCH 3/4] ARM: at91: pm: configure PMC fast startup signals

[Wenyou Yang]

The fast startup signal is used as wake up sources for ULP1 mode.
As soon as a fast startup signal is asserted, the embedded 12 MHz
RC oscillator restarts automatically.

This patch is to configure the fast startup signals, which signal
is enabled to trigger the PMC to wake up the system from ULP1 mode
should be configured via the DT.

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
---

 arch/arm/mach-at91/pm.c      |   96 ++++++++++++++++++++++++++++++++++++++++++
 include/linux/clk/at91_pmc.h |   32 ++++++++++++++
 2 files changed, 128 insertions(+)

diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c
index a7aec35..2c424b3 100644
--- a/arch/arm/mach-at91/pm.c
+++ b/arch/arm/mach-at91/pm.c
@@ -24,6 +24,8 @@
 #include <linux/platform_device.h>
 #include <linux/io.h>
 #include <linux/clk/at91_pmc.h>
+#include <linux/mfd/syscon.h>
+#include <linux/regmap.h>
 
 #include <asm/irq.h>
 #include <linux/atomic.h>
@@ -425,6 +427,98 @@ static void __init at91_pm_sram_init(void)
 			&at91_pm_suspend_in_sram, at91_pm_suspend_in_sram_sz);
 }
 
+static int __init at91_pmc_fast_startup_init(void)
+{
+	struct device_node *np;
+	struct regmap *regmap;
+	u32 mode = 0, polarity = 0;
+
+	np = of_find_compatible_node(NULL, NULL,
+				     "atmel,sama5d2-pmc-fast-startup");
+	if (!np)
+		return -ENODEV;
+
+	regmap = syscon_node_to_regmap(of_get_parent(np));
+	if (IS_ERR(regmap)) {
+		pr_info("AT91: failed to find PMC fast startup\n");
+		return PTR_ERR(regmap);
+	}
+
+	mode |= of_property_read_bool(np, "atmel,fast-startup-wake-up") ?
+		AT91_PMC_FSTT0 : 0;
+	mode |= of_property_read_bool(np, "atmel,fast-startup-secumod") ?
+		AT91_PMC_FSTT1 : 0;
+	mode |= of_property_read_bool(np, "atmel,fast-startup-piobu0") ?
+		AT91_PMC_FSTT2 : 0;
+	mode |= of_property_read_bool(np, "atmel,fast-startup-piobu1") ?
+		AT91_PMC_FSTT3 : 0;
+	mode |= of_property_read_bool(np, "atmel,fast-startup-piobu2") ?
+		AT91_PMC_FSTT4 : 0;
+	mode |= of_property_read_bool(np, "atmel,fast-startup-piobu3") ?
+		AT91_PMC_FSTT5 : 0;
+	mode |= of_property_read_bool(np, "atmel,fast-startup-piobu4") ?
+		AT91_PMC_FSTT6 : 0;
+	mode |= of_property_read_bool(np, "atmel,fast-startup-piobu5") ?
+		AT91_PMC_FSTT7 : 0;
+	mode |= of_property_read_bool(np, "atmel,fast-startup-piobu6") ?
+		AT91_PMC_FSTT8 : 0;
+	mode |= of_property_read_bool(np, "atmel,fast-startup-piobu7") ?
+		AT91_PMC_FSTT9 : 0;
+	mode |= of_property_read_bool(np, "atmel,fast-startup-gmac-wol") ?
+		AT91_PMC_FSTT10 : 0;
+	mode |= of_property_read_bool(np, "atmel,fast-startup-rtc-alarm") ?
+		AT91_PMC_RTCAL : 0;
+	mode |= of_property_read_bool(np, "atmel,fast-startup-usb-resume") ?
+		AT91_PMC_USBAL : 0;
+	mode |= of_property_read_bool(np, "atmel,fast-startup-sdmmc-cd") ?
+		AT91_PMC_SDMMC_CD : 0;
+	mode |= of_property_read_bool(np, "atmel,fast-startup-rxlp-match") ?
+		AT91_PMC_RXLP_MCE : 0;
+	mode |= of_property_read_bool(np, "atmel,fast-startup-acc-comparison") ?
+		AT91_PMC_ACC_CE : 0;
+
+	polarity |= of_property_read_bool(np,
+		"atmel,fast-startup-wkup-pin-high") ? AT91_PMC_FSTP0 : 0;
+
+	if (mode & AT91_PMC_FSTT1)
+		polarity |= AT91_PMC_FSTP1;
+
+	polarity |= of_property_read_bool(np,
+		"atmel,fast-startup-piobu0-high") ? AT91_PMC_FSTP2 : 0;
+
+	polarity |= of_property_read_bool(np,
+		"atmel,fast-startup-piobu1-high") ? AT91_PMC_FSTP3 : 0;
+
+	polarity |= of_property_read_bool(np,
+		"atmel,fast-startup-piobu2-high") ? AT91_PMC_FSTP4 : 0;
+
+	polarity |= of_property_read_bool(np,
+		"atmel,fast-startup-piobu3-high") ? AT91_PMC_FSTP5 : 0;
+
+	polarity |= of_property_read_bool(np,
+		"atmel,fast-startup-piobu4-high") ? AT91_PMC_FSTP6 : 0;
+
+	polarity |= of_property_read_bool(np,
+		"atmel,fast-startup-piobu5-high") ? AT91_PMC_FSTP7 : 0;
+
+	polarity |= of_property_read_bool(np,
+		"atmel,fast-startup-piobu6-high") ? AT91_PMC_FSTP8 : 0;
+
+	polarity |= of_property_read_bool(np,
+		"atmel,fast-startup-piobu7-high") ? AT91_PMC_FSTP9 : 0;
+
+	if (mode & AT91_PMC_FSTT10)
+		polarity |= AT91_PMC_FSTP10;
+
+	regmap_write(regmap, AT91_PMC_FSMR, mode);
+
+	regmap_write(regmap, AT91_PMC_FSPR, polarity);
+
+	of_node_put(np);
+
+	return 0;
+}
+
 static const struct of_device_id atmel_pmc_ids[] = {
 	{ .compatible = "atmel,at91rm9200-pmc"  },
 	{ .compatible = "atmel,at91sam9260-pmc" },
@@ -509,4 +603,6 @@ void __init sama5_pm_init(void)
 
 	if (readl(pmc + AT91_PMC_VERSION) >= SAMA5D2_PMC_VERSION)
 		at91_pm_data.ulp_mode = ULP1_MODE;
+
+	at91_pmc_fast_startup_init();
 }
diff --git a/include/linux/clk/at91_pmc.h b/include/linux/clk/at91_pmc.h
index 4afd891..683580e 100644
--- a/include/linux/clk/at91_pmc.h
+++ b/include/linux/clk/at91_pmc.h
@@ -168,6 +168,38 @@
 #define		AT91_PMC_WPVS		(0x1  <<  0)		/* Write Protect Violation Status */
 #define		AT91_PMC_WPVSRC		(0xffff  <<  8)		/* Write Protect Violation Source */
 
+#define AT91_PMC_FSMR		0x70		/* Fast Startup Mode Register */
+#define AT91_PMC_FSTT0		BIT(0)		/* WKUP Pin Enable */
+#define AT91_PMC_FSTT1		BIT(1)		/* Security Module Enable */
+#define AT91_PMC_FSTT2		BIT(2)		/* PIOBU0 Input Enable */
+#define AT91_PMC_FSTT3		BIT(3)		/* PIOBU1 Input Enable */
+#define AT91_PMC_FSTT4		BIT(4)		/* PIOBU2 Input Enable */
+#define AT91_PMC_FSTT5		BIT(5)		/* PIOBU3 Input Enable */
+#define AT91_PMC_FSTT6		BIT(6)		/* PIOBU4 Input Enable */
+#define AT91_PMC_FSTT7		BIT(7)		/* PIOBU5 Input Enable */
+#define AT91_PMC_FSTT8		BIT(8)		/* PIOBU6 Input Enable */
+#define AT91_PMC_FSTT9		BIT(9)		/* PIOBU7 Input Enable */
+#define AT91_PMC_FSTT10		BIT(10)		/* GMAC Wake-up On LAN Enable */
+#define AT91_PMC_RTCAL		BIT(17)		/* RTC Alarm Enable */
+#define AT91_PMC_USBAL		BIT(18)		/* USB Resume Enable */
+#define AT91_PMC_SDMMC_CD	BIT(19)		/* SDMMC Card Detect Enable */
+#define AT91_PMC_LPM		BIT(20)		/* Low-power Mode */
+#define AT91_PMC_RXLP_MCE	BIT(24)		/* Backup UART Receive Enable */
+#define AT91_PMC_ACC_CE		BIT(25)		/* ACC Enable */
+
+#define AT91_PMC_FSPR		0x74		/* Fast Startup Polarity Reg */
+#define AT91_PMC_FSTP0		BIT(0)		/* WKUP Pin Polarity */
+#define AT91_PMC_FSTP1		BIT(1)		/* Security Module Polarity */
+#define AT91_PMC_FSTP2		BIT(2)		/* PIOBU0 Pin Polarity */
+#define AT91_PMC_FSTP3		BIT(3)		/* PIOBU1 Pin Polarity */
+#define AT91_PMC_FSTP4		BIT(4)		/* PIOBU2 Pin Polarity */
+#define AT91_PMC_FSTP5		BIT(5)		/* PIOBU3 Pin Polarity */
+#define AT91_PMC_FSTP6		BIT(6)		/* PIOBU4 Pin Polarity */
+#define AT91_PMC_FSTP7		BIT(7)		/* PIOBU5 Pin Polarity */
+#define AT91_PMC_FSTP8		BIT(8)		/* PIOBU6 Pin Polarity */
+#define AT91_PMC_FSTP9		BIT(9)		/* PIOBU7 Pin Polarity */
+#define AT91_PMC_FSTP10		BIT(10)		/* Wake-up On LAN Polarity */
+
 #define AT91_PMC_VERSION	0xfc
 
 #define AT91_PMC_PCER1		0x100			/* Peripheral Clock Enable Register 1 [SAMA5 only]*/
-- 
1.7.9.5

[PATCH 4/4] Documentation: atmel-at91: add DT bindings for fast startup

[Wenyou Yang]

Add DT bindings to configurate the PMC_FSMR and PMC_FSPR registers
to trigger a fast restart signal to PMC.

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
---

 .../devicetree/bindings/arm/atmel-pmc.txt          |   74 ++++++++++++++++++++
 1 file changed, 74 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/atmel-pmc.txt b/Documentation/devicetree/bindings/arm/atmel-pmc.txt
index 795cc78..8d45ff9f 100644
--- a/Documentation/devicetree/bindings/arm/atmel-pmc.txt
+++ b/Documentation/devicetree/bindings/arm/atmel-pmc.txt
@@ -12,3 +12,77 @@ Examples:
 		compatible = "atmel,at91rm9200-pmc";
 		reg = <0xfffffc00 0x100>;
 	};
+
+PMC Fast Startup Signals
+
+The PMC Fast Start Signals are used as the wake up source to trigger the PMC
+to wake up the system from the ULP1 mode.
+
+required properties:
+- compatible: Should be "atmel,sama5d2-pmc-fast-startup".
+
+optional properties:
+- atmel,fast-startup-wake-up: boolean to enable the WKUP pin to trigger
+  a fast restart signal to the PMC.
+- atmel,fast-startup-secumod: boolean to enable the Security Mode to trigger
+  a fast restart signal to the PMC.
+- atmel,fast-startup-piobu0: boolean to enable the PIOBU0 Input to trigger
+  a fast restart signal to the PMC.
+- atmel,fast-startup-piobu1: boolean to enable the PIOBU1 Input to trigger
+  a fast restart signal to the PMC.
+- atmel,fast-startup-piobu2: boolean to enable the PIOBU2 Input to trigger
+  a fast restart signal to the PMC.
+- atmel,fast-startup-piobu3: boolean to enable the PIOBU3 Input to trigger
+  a fast restart signal to the PMC.
+- atmel,fast-startup-piobu4: boolean to enable the PIOBU4 Input to trigger
+  a fast restart signal to the PMC.
+- atmel,fast-startup-piobu5: boolean to enable the PIOBU5 Input to trigger
+  a fast restart signal to the PMC.
+- atmel,fast-startup-piobu6: boolean to enable the PIOBU6 Input to trigger
+  a fast restart signal to the PMC.
+- atmel,fast-startup-piobu7: boolean to enable the PIOBU7 Input to trigger
+  a fast restart signal to the PMC.
+- atmel,fast-startup-gmac-wol: boolean to enable the GMAC Wake-up On LAN
+  to trigger a fast restart signal to the PMC.
+- atmel,fast-startup-rtc-alarm: boolean to enable the RTC Alarm to trigger
+  a fast restart signal to the PMC.
+- atmel,fast-startup-usb-resume: boolean to enable the USB Resume to trigger
+  a fast restart signal to the PMC.
+- atmel,fast-startup-sdmmc-cd: boolean to enable the SDMMC Card Detect
+  to trigger a fast restart signal to the PMC.
+- atmel,fast-startup-rxlp-match: boolean to enable the Backuo UART Receive
+  Match Condition to trigger a fast restart signal to the PMC.
+- atmel,fast-startup-acc-comparison: boolean to enable the Analog Comparator
+  Controller (ACC) Comparison to to trigger a fast restart signal to the PMC.
+
+- atmel,fast-startup-wkup-pin-high: boolean to indicate if the WKUP Pin is
+  in the high level to trigger fast restart signal, otherwise low level.
+- atmel,fast-startup-piobu0-high: boolean to indicate if the PIOBU0 Pin is
+  in the high level to trigger fast restart signal, otherwise low level.
+- atmel,fast-startup-piobu1-high: boolean to indicate if the PIOBU1 Pin is
+  in the high level to trigger fast restart signal, otherwise low level.
+- atmel,fast-startup-piobu2-high: boolean to indicate if the PIOBU2 Pin is
+  in the high level to trigger fast restart signal, otherwise low level.
+- atmel,fast-startup-piobu3-high: boolean to indicate if the PIOBU3 Pin is
+  in the high level to trigger fast restart signal, otherwise low level.
+- atmel,fast-startup-piobu4-high: boolean to indicate if the PIOBU4 Pin is
+  in the high level to trigger fast restart signal, otherwise low level.
+- atmel,fast-startup-piobu5-high: boolean to indicate if the PIOBU5 Pin is
+  in the high level to trigger fast restart signal, otherwise low level.
+- atmel,fast-startup-piobu6-high: boolean to indicate if the PIOBU6 Pin is
+  in the high level to trigger fast restart signal, otherwise low level.
+- atmel,fast-startup-piobu7-high: boolean to indicate if the PIOBU7 Pin is
+  in the high level to trigger fast restart signal, otherwise low level.
+
+Example:
+
+	pmc: pmc at f0014000 {
+		compatible = "atmel,sama5d2-pmc";
+		reg = <0xf0014000 0x160>;
+
+		pmc_fast_restart {
+			compatible = "atmel,sama5d2-pmc-fast-startup";
+			atmel,fast-startup-wake-up;
+			atmel,fast-startup-rtc-alarm;
+		};
+	};
-- 
1.7.9.5

[PATCH 4/4] Documentation: atmel-at91: add DT bindings for fast startup

[Rob Herring]

On Thu, Jan 28, 2016 at 06:19:16PM +0800, Wenyou Yang wrote:
> Add DT bindings to configurate the PMC_FSMR and PMC_FSPR registers
> to trigger a fast restart signal to PMC.
> 
> Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
> ---
> 
>  .../devicetree/bindings/arm/atmel-pmc.txt          |   74 ++++++++++++++++++++
>  1 file changed, 74 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/arm/atmel-pmc.txt b/Documentation/devicetree/bindings/arm/atmel-pmc.txt
> index 795cc78..8d45ff9f 100644
> --- a/Documentation/devicetree/bindings/arm/atmel-pmc.txt
> +++ b/Documentation/devicetree/bindings/arm/atmel-pmc.txt
> @@ -12,3 +12,77 @@ Examples:
>  		compatible = "atmel,at91rm9200-pmc";
>  		reg = <0xfffffc00 0x100>;
>  	};
> +
> +PMC Fast Startup Signals
> +
> +The PMC Fast Start Signals are used as the wake up source to trigger the PMC
> +to wake up the system from the ULP1 mode.
> +
> +required properties:
> +- compatible: Should be "atmel,sama5d2-pmc-fast-startup".

Why the compatible? Does this correspond to some h/w block rather than 
features of the PMC? If it is simply because you want to have a separate 
driver, that is not a good reason.

> +
> +optional properties:
> +- atmel,fast-startup-wake-up: boolean to enable the WKUP pin to trigger
> +  a fast restart signal to the PMC.
> +- atmel,fast-startup-secumod: boolean to enable the Security Mode to trigger
> +  a fast restart signal to the PMC.
> +- atmel,fast-startup-piobu0: boolean to enable the PIOBU0 Input to trigger
> +  a fast restart signal to the PMC.
> +- atmel,fast-startup-piobu1: boolean to enable the PIOBU1 Input to trigger
> +  a fast restart signal to the PMC.
> +- atmel,fast-startup-piobu2: boolean to enable the PIOBU2 Input to trigger
> +  a fast restart signal to the PMC.
> +- atmel,fast-startup-piobu3: boolean to enable the PIOBU3 Input to trigger
> +  a fast restart signal to the PMC.
> +- atmel,fast-startup-piobu4: boolean to enable the PIOBU4 Input to trigger
> +  a fast restart signal to the PMC.
> +- atmel,fast-startup-piobu5: boolean to enable the PIOBU5 Input to trigger
> +  a fast restart signal to the PMC.
> +- atmel,fast-startup-piobu6: boolean to enable the PIOBU6 Input to trigger
> +  a fast restart signal to the PMC.
> +- atmel,fast-startup-piobu7: boolean to enable the PIOBU7 Input to trigger
> +  a fast restart signal to the PMC.
> +- atmel,fast-startup-gmac-wol: boolean to enable the GMAC Wake-up On LAN
> +  to trigger a fast restart signal to the PMC.
> +- atmel,fast-startup-rtc-alarm: boolean to enable the RTC Alarm to trigger
> +  a fast restart signal to the PMC.
> +- atmel,fast-startup-usb-resume: boolean to enable the USB Resume to trigger
> +  a fast restart signal to the PMC.
> +- atmel,fast-startup-sdmmc-cd: boolean to enable the SDMMC Card Detect
> +  to trigger a fast restart signal to the PMC.
> +- atmel,fast-startup-rxlp-match: boolean to enable the Backuo UART Receive
> +  Match Condition to trigger a fast restart signal to the PMC.
> +- atmel,fast-startup-acc-comparison: boolean to enable the Analog Comparator
> +  Controller (ACC) Comparison to to trigger a fast restart signal to the PMC.
> +
> +- atmel,fast-startup-wkup-pin-high: boolean to indicate if the WKUP Pin is
> +  in the high level to trigger fast restart signal, otherwise low level.

Perhaps just make the above bool properties take a value to indicate 
high or low triggered.

> +- atmel,fast-startup-piobu0-high: boolean to indicate if the PIOBU0 Pin is
> +  in the high level to trigger fast restart signal, otherwise low level.
> +- atmel,fast-startup-piobu1-high: boolean to indicate if the PIOBU1 Pin is
> +  in the high level to trigger fast restart signal, otherwise low level.
> +- atmel,fast-startup-piobu2-high: boolean to indicate if the PIOBU2 Pin is
> +  in the high level to trigger fast restart signal, otherwise low level.
> +- atmel,fast-startup-piobu3-high: boolean to indicate if the PIOBU3 Pin is
> +  in the high level to trigger fast restart signal, otherwise low level.
> +- atmel,fast-startup-piobu4-high: boolean to indicate if the PIOBU4 Pin is
> +  in the high level to trigger fast restart signal, otherwise low level.
> +- atmel,fast-startup-piobu5-high: boolean to indicate if the PIOBU5 Pin is
> +  in the high level to trigger fast restart signal, otherwise low level.
> +- atmel,fast-startup-piobu6-high: boolean to indicate if the PIOBU6 Pin is
> +  in the high level to trigger fast restart signal, otherwise low level.
> +- atmel,fast-startup-piobu7-high: boolean to indicate if the PIOBU7 Pin is
> +  in the high level to trigger fast restart signal, otherwise low level.

This would be a long list in the DT if you set all these properties. 
Perhaps this should all be expressed in a more compact form.

> +
> +Example:
> +
> +	pmc: pmc at f0014000 {
> +		compatible = "atmel,sama5d2-pmc";
> +		reg = <0xf0014000 0x160>;
> +
> +		pmc_fast_restart {
> +			compatible = "atmel,sama5d2-pmc-fast-startup";
> +			atmel,fast-startup-wake-up;
> +			atmel,fast-startup-rtc-alarm;
> +		};
> +	};
> -- 
> 1.7.9.5
> 

[PATCH 4/4] Documentation: atmel-at91: add DT bindings for fast startup

[Yang, Wenyou]

Hi Rob,

Thank you for your review.

> -----Original Message-----
> From: Rob Herring [mailto:robh at kernel.org]
> Sent: 2016?1?30? 0:20
> To: Yang, Wenyou <Wenyou.Yang@atmel.com>
> Cc: Ferre, Nicolas <Nicolas.FERRE@atmel.com>; Alexandre Belloni
> <alexandre.belloni@free-electrons.com>; Jean-Christophe Plagniol-Villard
> <plagnioj@jcrosoft.com>; Russell King <linux@arm.linux.org.uk>; linux-
> clk at vger.kernel.org; Pawel Moll <pawel.moll@arm.com>; Mark Brown
> <broonie@kernel.org>; Ian Campbell <ijc+devicetree@hellion.org.uk>; Kumar
> Gala <galak@codeaurora.org>; linux-arm-kernel at lists.infradead.org; linux-
> kernel at vger.kernel.org; devicetree at vger.kernel.org
> Subject: Re: [PATCH 4/4] Documentation: atmel-at91: add DT bindings for fast
> startup
> 
> On Thu, Jan 28, 2016 at 06:19:16PM +0800, Wenyou Yang wrote:
> > Add DT bindings to configurate the PMC_FSMR and PMC_FSPR registers to
> > trigger a fast restart signal to PMC.
> >
> > Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
> > ---
> >
> >  .../devicetree/bindings/arm/atmel-pmc.txt          |   74
> ++++++++++++++++++++
> >  1 file changed, 74 insertions(+)
> >
> > diff --git a/Documentation/devicetree/bindings/arm/atmel-pmc.txt
> > b/Documentation/devicetree/bindings/arm/atmel-pmc.txt
> > index 795cc78..8d45ff9f 100644
> > --- a/Documentation/devicetree/bindings/arm/atmel-pmc.txt
> > +++ b/Documentation/devicetree/bindings/arm/atmel-pmc.txt
> > @@ -12,3 +12,77 @@ Examples:
> >  		compatible = "atmel,at91rm9200-pmc";
> >  		reg = <0xfffffc00 0x100>;
> >  	};
> > +
> > +PMC Fast Startup Signals
> > +
> > +The PMC Fast Start Signals are used as the wake up source to trigger
> > +the PMC to wake up the system from the ULP1 mode.
> > +
> > +required properties:
> > +- compatible: Should be "atmel,sama5d2-pmc-fast-startup".
> 
> Why the compatible? Does this correspond to some h/w block rather than features
> of the PMC? If it is simply because you want to have a separate driver, that is not
> a good reason.

The PMC is regarded as an MFD device.

The Fast Startup function is a sub-device, the driver access the register
through regmap returned from the syscon helper API syscon_node_to_regmap().

> 
> > +
> > +optional properties:
> > +- atmel,fast-startup-wake-up: boolean to enable the WKUP pin to
> > +trigger
> > +  a fast restart signal to the PMC.
> > +- atmel,fast-startup-secumod: boolean to enable the Security Mode to
> > +trigger
> > +  a fast restart signal to the PMC.
> > +- atmel,fast-startup-piobu0: boolean to enable the PIOBU0 Input to
> > +trigger
> > +  a fast restart signal to the PMC.
> > +- atmel,fast-startup-piobu1: boolean to enable the PIOBU1 Input to
> > +trigger
> > +  a fast restart signal to the PMC.
> > +- atmel,fast-startup-piobu2: boolean to enable the PIOBU2 Input to
> > +trigger
> > +  a fast restart signal to the PMC.
> > +- atmel,fast-startup-piobu3: boolean to enable the PIOBU3 Input to
> > +trigger
> > +  a fast restart signal to the PMC.
> > +- atmel,fast-startup-piobu4: boolean to enable the PIOBU4 Input to
> > +trigger
> > +  a fast restart signal to the PMC.
> > +- atmel,fast-startup-piobu5: boolean to enable the PIOBU5 Input to
> > +trigger
> > +  a fast restart signal to the PMC.
> > +- atmel,fast-startup-piobu6: boolean to enable the PIOBU6 Input to
> > +trigger
> > +  a fast restart signal to the PMC.
> > +- atmel,fast-startup-piobu7: boolean to enable the PIOBU7 Input to
> > +trigger
> > +  a fast restart signal to the PMC.
> > +- atmel,fast-startup-gmac-wol: boolean to enable the GMAC Wake-up On
> > +LAN
> > +  to trigger a fast restart signal to the PMC.
> > +- atmel,fast-startup-rtc-alarm: boolean to enable the RTC Alarm to
> > +trigger
> > +  a fast restart signal to the PMC.
> > +- atmel,fast-startup-usb-resume: boolean to enable the USB Resume to
> > +trigger
> > +  a fast restart signal to the PMC.
> > +- atmel,fast-startup-sdmmc-cd: boolean to enable the SDMMC Card
> > +Detect
> > +  to trigger a fast restart signal to the PMC.
> > +- atmel,fast-startup-rxlp-match: boolean to enable the Backuo UART
> > +Receive
> > +  Match Condition to trigger a fast restart signal to the PMC.
> > +- atmel,fast-startup-acc-comparison: boolean to enable the Analog
> > +Comparator
> > +  Controller (ACC) Comparison to to trigger a fast restart signal to the PMC.
> > +
> > +- atmel,fast-startup-wkup-pin-high: boolean to indicate if the WKUP
> > +Pin is
> > +  in the high level to trigger fast restart signal, otherwise low level.
> 
> Perhaps just make the above bool properties take a value to indicate high or low
> triggered.

Agreed. 

How about the following changes? And a more compact form.

atmel,fs-wkup-pin-level = <1>; to indicated the WKUP Pin is in the high level trigged.
atmel,fs-wkup-pin-level = <0>; to indicated the WKUP Pin is in the low level trigged.

> 
> > +- atmel,fast-startup-piobu0-high: boolean to indicate if the PIOBU0
> > +Pin is
> > +  in the high level to trigger fast restart signal, otherwise low level.
> > +- atmel,fast-startup-piobu1-high: boolean to indicate if the PIOBU1
> > +Pin is
> > +  in the high level to trigger fast restart signal, otherwise low level.
> > +- atmel,fast-startup-piobu2-high: boolean to indicate if the PIOBU2
> > +Pin is
> > +  in the high level to trigger fast restart signal, otherwise low level.
> > +- atmel,fast-startup-piobu3-high: boolean to indicate if the PIOBU3
> > +Pin is
> > +  in the high level to trigger fast restart signal, otherwise low level.
> > +- atmel,fast-startup-piobu4-high: boolean to indicate if the PIOBU4
> > +Pin is
> > +  in the high level to trigger fast restart signal, otherwise low level.
> > +- atmel,fast-startup-piobu5-high: boolean to indicate if the PIOBU5
> > +Pin is
> > +  in the high level to trigger fast restart signal, otherwise low level.
> > +- atmel,fast-startup-piobu6-high: boolean to indicate if the PIOBU6
> > +Pin is
> > +  in the high level to trigger fast restart signal, otherwise low level.
> > +- atmel,fast-startup-piobu7-high: boolean to indicate if the PIOBU7
> > +Pin is
> > +  in the high level to trigger fast restart signal, otherwise low level.
> 
> This would be a long list in the DT if you set all these properties.
> Perhaps this should all be expressed in a more compact form.
> 

Yes, change as above.

> > +
> > +Example:
> > +
> > +	pmc: pmc at f0014000 {
> > +		compatible = "atmel,sama5d2-pmc";
> > +		reg = <0xf0014000 0x160>;
> > +
> > +		pmc_fast_restart {
> > +			compatible = "atmel,sama5d2-pmc-fast-startup";
> > +			atmel,fast-startup-wake-up;
> > +			atmel,fast-startup-rtc-alarm;
> > +		};
> > +	};
> > --
> > 1.7.9.5
> >


Best Regards,
Wenyou Yang

[PATCH 0/4] rework ULP1 patches

[Claudiu Beznea]

Hi,

Based on the discussion at [1] and private discussion I had with Alexandre
Belloni on IRC, I reworked ULP1 patches to remove device tree bindings
proposed in [1].

The implementation from this patches (mostly patch 4/4) is using
device_may_wakeup() API that current Linux code provides and the fact that
for the ULP1 the wakeup souces are known and well defined.
Basically, this rework (mostly patch 4/4) loops through well defined ULP1
wakeup sources and check if those wakeup sources were configured to wake
up the system (vid DT or sysfs) and, based on that (and in case of RTC,
based on SHDWC.MR), set the PMC fast startup mode and polarity registers.
In [1] PMC fast startup mode and polarity registers were configured by
introducing new DT bindings.

Since with these patches SHDWC registers are used in ULP1 wakeup sources
configuration the patch 4/4 changed a bit the PM initialization phase for
SAMA5D2 in order to have mapped also the SHDWC in case ULP1 needs to be
initialized. In case ULP1 configuration fails the ULP0 mode is used (same
approach as in backup mode case).

I measure the delay introduced in suspend sequence by using an oscilloscope
connected to a GPIO and calling gpio_direction_output(PIN, 0) at the beginning
of at91_pm_config_ws() and gpio_direction_output(PIN, 1) at the end of
at91_pm_config_ws(). With these I measureed on oscilloscope the difference
b/w the front changes. The measured time was *1.56ms*. Keep in mind that
gpio_direction_output() will call, in the end,
atmel_gpio_direction_output() which access 4 registers to toggle the PIN
(in at91_pm_config_ws() there are also 4 peripheral register accesses).

Besides this rework, I took the chance and I appended few other patches to
this series, based on Wenyou Yang's previous work, related to ULP modes.

Patch 1/4: replaces slow clock with ULP0
Patch 2/4: is the Wenyou's patch wich adds ULP1 support
Patch 3/4: is defining PMC fast startup registers

The patches were based on v4.18-rc1.

[1] https://patchwork.kernel.org/patch/8595091/

Claudiu Beznea (3):
  ARM: at91: pm: Use ULP0 naming instead of slow clock
  ARM: at91: pm: add PMC fast startup registers defines
  ARM: at91: pm: configure wakeup sources for ULP1 mode

Wenyou Yang (1):
  ARM: at91: pm: Add ULP1 mode support

 arch/arm/mach-at91/pm.c         | 184 +++++++++++++++++++++++++++++++++-------
 arch/arm/mach-at91/pm.h         |   6 +-
 arch/arm/mach-at91/pm_suspend.S | 142 ++++++++++++++++++++++++++-----
 include/linux/clk/at91_pmc.h    |  15 ++++
 4 files changed, 294 insertions(+), 53 deletions(-)

-- 
2.7.4

[PATCH 2/4] ARM: at91: pm: Add ULP1 mode support

[Claudiu Beznea]

From: Wenyou Yang <wenyou.yang@atmel.com>

In the ULP1 mode, in order to achieve the lowest power consumption
with the system in retention mode and be able to resume on the wake
up events, all the clocks are shut off, inclusive the embedded 12MHz
RC oscillator, and the number of wake up sources is limited as well.
When the wake up event is asserted, the embedded 12MHz RC oscillator
restarts automatically.

The ULP1 (Ultra Low-power mode 1) is introduced by SAMA5D2.

The previous size of pm_suspend.o was 2148 bytes. With the addition of
ULP1 mode the new size of pm_suspend.o raised at 2456 bytes.

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Signed-off-by: Ludovic Desroches <ludovic.desroches@microchip.com>
[claudiu.beznea at microchip.com: aligned with 4.18-rc1]
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
---
 arch/arm/mach-at91/pm.c         |   1 +
 arch/arm/mach-at91/pm.h         |   3 +-
 arch/arm/mach-at91/pm_suspend.S | 142 ++++++++++++++++++++++++++++++++++------
 include/linux/clk/at91_pmc.h    |   2 +
 4 files changed, 127 insertions(+), 21 deletions(-)

diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c
index d43f00a715d7..099d8094018c 100644
--- a/arch/arm/mach-at91/pm.c
+++ b/arch/arm/mach-at91/pm.c
@@ -42,6 +42,7 @@ extern void at91_pinctrl_gpio_resume(void);
 static const match_table_t pm_modes __initconst = {
 	{ AT91_PM_STANDBY, "standby" },
 	{ AT91_PM_ULP0, "ulp0" },
+	{ AT91_PM_ULP1, "ulp1" },
 	{ AT91_PM_BACKUP, "backup" },
 	{ -1, NULL },
 };
diff --git a/arch/arm/mach-at91/pm.h b/arch/arm/mach-at91/pm.h
index c44eaf17db86..9bd4e6ca672a 100644
--- a/arch/arm/mach-at91/pm.h
+++ b/arch/arm/mach-at91/pm.h
@@ -23,7 +23,8 @@
 
 #define	AT91_PM_STANDBY		0x00
 #define AT91_PM_ULP0		0x01
-#define	AT91_PM_BACKUP		0x02
+#define AT91_PM_ULP1		0x02
+#define	AT91_PM_BACKUP		0x03
 
 #ifndef __ASSEMBLY__
 struct at91_pm_data {
diff --git a/arch/arm/mach-at91/pm_suspend.S b/arch/arm/mach-at91/pm_suspend.S
index 821322d1a64d..a7c6ae13c945 100644
--- a/arch/arm/mach-at91/pm_suspend.S
+++ b/arch/arm/mach-at91/pm_suspend.S
@@ -42,6 +42,15 @@ tmp2	.req	r5
 	.endm
 
 /*
+ * Wait for main oscillator selection is done
+ */
+	.macro wait_moscsels
+1:	ldr	tmp1, [pmc, #AT91_PMC_SR]
+	tst	tmp1, #AT91_PMC_MOSCSELS
+	beq	1b
+	.endm
+
+/*
  * Wait until PLLA has locked.
  */
 	.macro wait_pllalock
@@ -112,19 +121,20 @@ ENTRY(at91_pm_suspend_in_sram)
 	bl	at91_sramc_self_refresh
 
 	ldr	r0, .pm_mode
-	cmp	r0, #AT91_PM_ULP0
-	beq	ulp0_mode
+	cmp	r0, #AT91_PM_STANDBY
+	beq	standby
 	cmp	r0, #AT91_PM_BACKUP
 	beq	backup_mode
 
+	bl	at91_ulp_mode
+	b	exit_suspend
+
+standby:
 	/* Wait for interrupt */
 	ldr	pmc, .pmc_base
 	at91_cpu_idle
 	b	exit_suspend
 
-ulp0_mode:
-	bl	at91_ulp0_mode
-	b	exit_suspend
 backup_mode:
 	bl	at91_backup_mode
 	b	exit_suspend
@@ -151,7 +161,102 @@ ENTRY(at91_backup_mode)
 	str	tmp1, [r0, #0]
 ENDPROC(at91_backup_mode)
 
-ENTRY(at91_ulp0_mode)
+.macro at91_pm_ulp0_mode
+	ldr	pmc, .pmc_base
+
+	/* Turn off the crystal oscillator */
+	ldr	tmp1, [pmc, #AT91_CKGR_MOR]
+	bic	tmp1, tmp1, #AT91_PMC_MOSCEN
+	orr	tmp1, tmp1, #AT91_PMC_KEY
+	str	tmp1, [pmc, #AT91_CKGR_MOR]
+
+	/* Wait for interrupt */
+	at91_cpu_idle
+
+	/* Turn on the crystal oscillator */
+	ldr	tmp1, [pmc, #AT91_CKGR_MOR]
+	orr	tmp1, tmp1, #AT91_PMC_MOSCEN
+	orr	tmp1, tmp1, #AT91_PMC_KEY
+	str	tmp1, [pmc, #AT91_CKGR_MOR]
+
+	wait_moscrdy
+.endm
+
+/**
+ * Note: This procedure only applies on the platform which uses
+ * the external crystal oscillator as a main clock source.
+ */
+.macro at91_pm_ulp1_mode
+	ldr	pmc, .pmc_base
+
+	/* Switch the main clock source to 12-MHz RC oscillator */
+	ldr	tmp1, [pmc, #AT91_CKGR_MOR]
+	bic	tmp1, tmp1, #AT91_PMC_MOSCSEL
+	bic	tmp1, tmp1, #AT91_PMC_KEY_MASK
+	orr	tmp1, tmp1, #AT91_PMC_KEY
+	str	tmp1, [pmc, #AT91_CKGR_MOR]
+
+	wait_moscsels
+
+	/* Disable the crystal oscillator */
+	ldr	tmp1, [pmc, #AT91_CKGR_MOR]
+	bic	tmp1, tmp1, #AT91_PMC_MOSCEN
+	bic	tmp1, tmp1, #AT91_PMC_KEY_MASK
+	orr	tmp1, tmp1, #AT91_PMC_KEY
+	str	tmp1, [pmc, #AT91_CKGR_MOR]
+
+	/* Switch the master clock source to main clock */
+	ldr	tmp1, [pmc, #AT91_PMC_MCKR]
+	bic	tmp1, tmp1, #AT91_PMC_CSS
+	orr	tmp1, tmp1, #AT91_PMC_CSS_MAIN
+	str	tmp1, [pmc, #AT91_PMC_MCKR]
+
+	wait_mckrdy
+
+	/* Enter the ULP1 mode by set WAITMODE bit in CKGR_MOR */
+	ldr	tmp1, [pmc, #AT91_CKGR_MOR]
+	orr	tmp1, tmp1, #AT91_PMC_WAITMODE
+	bic	tmp1, tmp1, #AT91_PMC_KEY_MASK
+	orr	tmp1, tmp1, #AT91_PMC_KEY
+	str	tmp1, [pmc, #AT91_CKGR_MOR]
+
+	wait_mckrdy
+
+	/* Enable the crystal oscillator */
+	ldr	tmp1, [pmc, #AT91_CKGR_MOR]
+	orr	tmp1, tmp1, #AT91_PMC_MOSCEN
+	bic	tmp1, tmp1, #AT91_PMC_KEY_MASK
+	orr	tmp1, tmp1, #AT91_PMC_KEY
+	str	tmp1, [pmc, #AT91_CKGR_MOR]
+
+	wait_moscrdy
+
+	/* Switch the master clock source to slow clock */
+	ldr	tmp1, [pmc, #AT91_PMC_MCKR]
+	bic	tmp1, tmp1, #AT91_PMC_CSS
+	str	tmp1, [pmc, #AT91_PMC_MCKR]
+
+	wait_mckrdy
+
+	/* Switch main clock source to crystal oscillator */
+	ldr	tmp1, [pmc, #AT91_CKGR_MOR]
+	orr	tmp1, tmp1, #AT91_PMC_MOSCSEL
+	bic	tmp1, tmp1, #AT91_PMC_KEY_MASK
+	orr	tmp1, tmp1, #AT91_PMC_KEY
+	str	tmp1, [pmc, #AT91_CKGR_MOR]
+
+	wait_moscsels
+
+	/* Switch the master clock source to main clock */
+	ldr	tmp1, [pmc, #AT91_PMC_MCKR]
+	bic	tmp1, tmp1, #AT91_PMC_CSS
+	orr	tmp1, tmp1, #AT91_PMC_CSS_MAIN
+	str	tmp1, [pmc, #AT91_PMC_MCKR]
+
+	wait_mckrdy
+.endm
+
+ENTRY(at91_ulp_mode)
 	ldr	pmc, .pmc_base
 
 	/* Save Master clock setting */
@@ -174,22 +279,19 @@ ENTRY(at91_ulp0_mode)
 	orr	tmp1, tmp1, #(1 << 29)		/* bit 29 always set */
 	str	tmp1, [pmc, #AT91_CKGR_PLLAR]
 
-	/* Turn off the main oscillator */
-	ldr	tmp1, [pmc, #AT91_CKGR_MOR]
-	bic	tmp1, tmp1, #AT91_PMC_MOSCEN
-	orr	tmp1, tmp1, #AT91_PMC_KEY
-	str	tmp1, [pmc, #AT91_CKGR_MOR]
+	ldr	r0, .pm_mode
+	cmp	r0, #AT91_PM_ULP1
+	beq	ulp1_mode
 
-	/* Wait for interrupt */
-	at91_cpu_idle
+	at91_pm_ulp0_mode
+	b	ulp_exit
 
-	/* Turn on the main oscillator */
-	ldr	tmp1, [pmc, #AT91_CKGR_MOR]
-	orr	tmp1, tmp1, #AT91_PMC_MOSCEN
-	orr	tmp1, tmp1, #AT91_PMC_KEY
-	str	tmp1, [pmc, #AT91_CKGR_MOR]
+ulp1_mode:
+	at91_pm_ulp1_mode
+	b	ulp_exit
 
-	wait_moscrdy
+ulp_exit:
+	ldr	pmc, .pmc_base
 
 	/* Restore PLLA setting */
 	ldr	tmp1, .saved_pllar
@@ -212,7 +314,7 @@ ENTRY(at91_ulp0_mode)
 	wait_mckrdy
 
 	mov	pc, lr
-ENDPROC(at91_ulp0_mode)
+ENDPROC(at91_ulp_mode)
 
 /*
  * void at91_sramc_self_refresh(unsigned int is_active)
diff --git a/include/linux/clk/at91_pmc.h b/include/linux/clk/at91_pmc.h
index 6aca5ce8a99a..4ea2cbf9b50d 100644
--- a/include/linux/clk/at91_pmc.h
+++ b/include/linux/clk/at91_pmc.h
@@ -47,8 +47,10 @@
 #define	AT91_CKGR_MOR		0x20			/* Main Oscillator Register [not on SAM9RL] */
 #define		AT91_PMC_MOSCEN		(1    <<  0)		/* Main Oscillator Enable */
 #define		AT91_PMC_OSCBYPASS	(1    <<  1)		/* Oscillator Bypass */
+#define		AT91_PMC_WAITMODE	(1    <<  2)		/* Wait Mode Command */
 #define		AT91_PMC_MOSCRCEN	(1    <<  3)		/* Main On-Chip RC Oscillator Enable [some SAM9] */
 #define		AT91_PMC_OSCOUNT	(0xff <<  8)		/* Main Oscillator Start-up Time */
+#define		AT91_PMC_KEY_MASK	(0xff << 16)
 #define		AT91_PMC_KEY		(0x37 << 16)		/* MOR Writing Key */
 #define		AT91_PMC_MOSCSEL	(1    << 24)		/* Main Oscillator Selection [some SAM9] */
 #define		AT91_PMC_CFDEN		(1    << 25)		/* Clock Failure Detector Enable [some SAM9] */
-- 
2.7.4