* [PATCH v4 0/2] PCI: mediatek: Fixups for the IRQ handle routine and MT7622's class code @ 2017-12-22 5:39 honghui.zhang at mediatek.com 2017-12-22 5:39 ` [PATCH v4 1/2] PCI: mediatek: Clear IRQ status after IRQ dispatched to avoid reentry honghui.zhang at mediatek.com 2017-12-22 5:39 ` [PATCH v4 2/2] PCI: mediatek: Set up class type and vendor ID for MT7622 honghui.zhang at mediatek.com 0 siblings, 2 replies; 5+ messages in thread From: honghui.zhang at mediatek.com @ 2017-12-22 5:39 UTC (permalink / raw) To: linux-arm-kernel From: Honghui Zhang <honghui.zhang@mediatek.com> Two fixups for mediatek's host bridge: The first patch fixup the IRQ handle routine to avoid IRQ reentry which may exist for both MT2712 and MT7622. The second patch fixup class type for MT7622. Change since v3: - Setup the class type and vendor ID at the beginning of startup instead of in a quirk. - Add mediatek's vendor ID, it could be found in: https://pcisig.com/membership/member-companies?combine=&page=4 Change since v2: - Move the initialize of the iterate before the loop to fix an INTx IRQ issue in the first patch Change since v1: - Add the second patch. - Make the first patch's commit message more standard. Honghui Zhang (2): PCI: mediatek: Clear IRQ status after IRQ dispatched to avoid reentry PCI: mediatek: Set up class type and vendor ID for MT7622 drivers/pci/host/pcie-mediatek.c | 23 ++++++++++++++++++----- include/linux/pci_ids.h | 3 +++ 2 files changed, 21 insertions(+), 5 deletions(-) -- 2.6.4 ^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH v4 1/2] PCI: mediatek: Clear IRQ status after IRQ dispatched to avoid reentry 2017-12-22 5:39 [PATCH v4 0/2] PCI: mediatek: Fixups for the IRQ handle routine and MT7622's class code honghui.zhang at mediatek.com @ 2017-12-22 5:39 ` honghui.zhang at mediatek.com 2017-12-22 5:39 ` [PATCH v4 2/2] PCI: mediatek: Set up class type and vendor ID for MT7622 honghui.zhang at mediatek.com 1 sibling, 0 replies; 5+ messages in thread From: honghui.zhang at mediatek.com @ 2017-12-22 5:39 UTC (permalink / raw) To: linux-arm-kernel From: Honghui Zhang <honghui.zhang@mediatek.com> There maybe a same IRQ reentry scenario after IRQ received in current IRQ handle flow: EP device PCIe host driver EP driver 1. issue an IRQ 2. received IRQ 3. clear IRQ status 4. dispatch IRQ 5. clear IRQ source The IRQ status was not successfully cleared at step 2 since the IRQ source was not cleared yet. So the PCIe host driver may receive the same IRQ after step 5. Then there's an IRQ reentry occurred. Even worse, if the reentry IRQ was not an IRQ that EP driver expected, it may not handle the IRQ. Then we may run into the infinite loop from step 2 to step 4. Clear the IRQ status after IRQ have been dispatched to avoid the IRQ reentry. This patch also fix another INTx IRQ issue by initialize the iterate before the loop. If an INTx IRQ re-occurred while we are dispatching the INTx IRQ, then iterate may start from PCI_NUM_INTX + INTX_SHIFT instead of INTX_SHIFT for the second time entering the for_each_set_bit_from() loop. Signed-off-by: Honghui Zhang <honghui.zhang@mediatek.com> Acked-by: Ryder Lee <ryder.lee@mediatek.com> --- drivers/pci/host/pcie-mediatek.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/drivers/pci/host/pcie-mediatek.c b/drivers/pci/host/pcie-mediatek.c index db93efd..fc29a9a 100644 --- a/drivers/pci/host/pcie-mediatek.c +++ b/drivers/pci/host/pcie-mediatek.c @@ -601,15 +601,16 @@ static irqreturn_t mtk_pcie_intr_handler(int irq, void *data) struct mtk_pcie_port *port = (struct mtk_pcie_port *)data; unsigned long status; u32 virq; - u32 bit = INTX_SHIFT; + u32 bit; while ((status = readl(port->base + PCIE_INT_STATUS)) & INTX_MASK) { + bit = INTX_SHIFT; for_each_set_bit_from(bit, &status, PCI_NUM_INTX + INTX_SHIFT) { - /* Clear the INTx */ - writel(1 << bit, port->base + PCIE_INT_STATUS); virq = irq_find_mapping(port->irq_domain, bit - INTX_SHIFT); generic_handle_irq(virq); + /* Clear the INTx */ + writel(1 << bit, port->base + PCIE_INT_STATUS); } } @@ -619,10 +620,10 @@ static irqreturn_t mtk_pcie_intr_handler(int irq, void *data) while ((imsi_status = readl(port->base + PCIE_IMSI_STATUS))) { for_each_set_bit(bit, &imsi_status, MTK_MSI_IRQS_NUM) { - /* Clear the MSI */ - writel(1 << bit, port->base + PCIE_IMSI_STATUS); virq = irq_find_mapping(port->msi_domain, bit); generic_handle_irq(virq); + /* Clear the MSI */ + writel(1 << bit, port->base + PCIE_IMSI_STATUS); } } /* Clear MSI interrupt status */ -- 2.6.4 ^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH v4 2/2] PCI: mediatek: Set up class type and vendor ID for MT7622 2017-12-22 5:39 [PATCH v4 0/2] PCI: mediatek: Fixups for the IRQ handle routine and MT7622's class code honghui.zhang at mediatek.com 2017-12-22 5:39 ` [PATCH v4 1/2] PCI: mediatek: Clear IRQ status after IRQ dispatched to avoid reentry honghui.zhang at mediatek.com @ 2017-12-22 5:39 ` honghui.zhang at mediatek.com 2017-12-25 10:27 ` Ryder Lee 1 sibling, 1 reply; 5+ messages in thread From: honghui.zhang at mediatek.com @ 2017-12-22 5:39 UTC (permalink / raw) To: linux-arm-kernel From: Honghui Zhang <honghui.zhang@mediatek.com> The hardware default value of IDs and class type is not correct, fix that by setup the correct values before start up. Signed-off-by: Honghui Zhang <honghui.zhang@mediatek.com> --- drivers/pci/host/pcie-mediatek.c | 12 ++++++++++++ include/linux/pci_ids.h | 3 +++ 2 files changed, 15 insertions(+) diff --git a/drivers/pci/host/pcie-mediatek.c b/drivers/pci/host/pcie-mediatek.c index fc29a9a..0ef33e4 100644 --- a/drivers/pci/host/pcie-mediatek.c +++ b/drivers/pci/host/pcie-mediatek.c @@ -74,6 +74,10 @@ /* PCIe V2 per-port registers */ #define PCIE_MSI_VECTOR 0x0c0 + +#define PCIE_CONF_ID 0x100 +#define PCIE_CONF_CLASS 0x104 + #define PCIE_INT_MASK 0x420 #define INTX_MASK GENMASK(19, 16) #define INTX_SHIFT 16 @@ -393,6 +397,14 @@ static int mtk_pcie_startup_port_v2(struct mtk_pcie_port *port) val |= PCIE_CSR_LTSSM_EN(port->slot) | PCIE_CSR_ASPM_L1_EN(port->slot); writel(val, pcie->base + PCIE_SYS_CFG_V2); + + /* Set up vendor ID and device ID for MT7622*/ + val = PCI_VENDOR_ID_MEDIATEK | (PCI_DEVICE_ID_MT7622 << 16); + writel(val, port->base + PCIE_CONF_ID); + + /* Set up class code for MT7622 */ + val = PCI_CLASS_BRIDGE_PCI << 16; + writel(val, port->base + PCIE_CONF_CLASS); } /* Assert all reset signals */ diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h index ab20dc5..000c5df 100644 --- a/include/linux/pci_ids.h +++ b/include/linux/pci_ids.h @@ -2113,6 +2113,9 @@ #define PCI_VENDOR_ID_MYRICOM 0x14c1 +#define PCI_VENDOR_ID_MEDIATEK 0x14c3 +#define PCI_DEVICE_ID_MT7622 0x5396 + #define PCI_VENDOR_ID_TITAN 0x14D2 #define PCI_DEVICE_ID_TITAN_010L 0x8001 #define PCI_DEVICE_ID_TITAN_100L 0x8010 -- 2.6.4 ^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH v4 2/2] PCI: mediatek: Set up class type and vendor ID for MT7622 2017-12-22 5:39 ` [PATCH v4 2/2] PCI: mediatek: Set up class type and vendor ID for MT7622 honghui.zhang at mediatek.com @ 2017-12-25 10:27 ` Ryder Lee 2017-12-26 1:41 ` Honghui Zhang 0 siblings, 1 reply; 5+ messages in thread From: Ryder Lee @ 2017-12-25 10:27 UTC (permalink / raw) To: linux-arm-kernel On Fri, 2017-12-22 at 13:39 +0800, honghui.zhang at mediatek.com wrote: > From: Honghui Zhang <honghui.zhang@mediatek.com> > > The hardware default value of IDs and class type is not correct, > fix that by setup the correct values before start up. > > Signed-off-by: Honghui Zhang <honghui.zhang@mediatek.com> > --- > drivers/pci/host/pcie-mediatek.c | 12 ++++++++++++ > include/linux/pci_ids.h | 3 +++ > 2 files changed, 15 insertions(+) > > diff --git a/drivers/pci/host/pcie-mediatek.c b/drivers/pci/host/pcie-mediatek.c > index fc29a9a..0ef33e4 100644 > --- a/drivers/pci/host/pcie-mediatek.c > +++ b/drivers/pci/host/pcie-mediatek.c > @@ -74,6 +74,10 @@ > > /* PCIe V2 per-port registers */ > #define PCIE_MSI_VECTOR 0x0c0 > + > +#define PCIE_CONF_ID 0x100 > +#define PCIE_CONF_CLASS 0x104 > + > #define PCIE_INT_MASK 0x420 > #define INTX_MASK GENMASK(19, 16) > #define INTX_SHIFT 16 > @@ -393,6 +397,14 @@ static int mtk_pcie_startup_port_v2(struct mtk_pcie_port *port) > val |= PCIE_CSR_LTSSM_EN(port->slot) | > PCIE_CSR_ASPM_L1_EN(port->slot); > writel(val, pcie->base + PCIE_SYS_CFG_V2); > + > + /* Set up vendor ID and device ID for MT7622*/ > + val = PCI_VENDOR_ID_MEDIATEK | (PCI_DEVICE_ID_MT7622 << 16); > + writel(val, port->base + PCIE_CONF_ID); IMHO, this is a general function so you can ignore "device ID for MT7622" here, but just make sure class code/vendor ID correct. > + /* Set up class code for MT7622 */ > + val = PCI_CLASS_BRIDGE_PCI << 16; > + writel(val, port->base + PCIE_CONF_CLASS); > } > > /* Assert all reset signals */ > diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h > index ab20dc5..000c5df 100644 > --- a/include/linux/pci_ids.h > +++ b/include/linux/pci_ids.h > @@ -2113,6 +2113,9 @@ > > #define PCI_VENDOR_ID_MYRICOM 0x14c1 > > +#define PCI_VENDOR_ID_MEDIATEK 0x14c3 > +#define PCI_DEVICE_ID_MT7622 0x5396 > + > #define PCI_VENDOR_ID_TITAN 0x14D2 > #define PCI_DEVICE_ID_TITAN_010L 0x8001 > #define PCI_DEVICE_ID_TITAN_100L 0x8010 ^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH v4 2/2] PCI: mediatek: Set up class type and vendor ID for MT7622 2017-12-25 10:27 ` Ryder Lee @ 2017-12-26 1:41 ` Honghui Zhang 0 siblings, 0 replies; 5+ messages in thread From: Honghui Zhang @ 2017-12-26 1:41 UTC (permalink / raw) To: linux-arm-kernel On Mon, 2017-12-25 at 18:27 +0800, Ryder Lee wrote: > On Fri, 2017-12-22 at 13:39 +0800, honghui.zhang at mediatek.com wrote: > > From: Honghui Zhang <honghui.zhang@mediatek.com> > > > > The hardware default value of IDs and class type is not correct, > > fix that by setup the correct values before start up. > > > > Signed-off-by: Honghui Zhang <honghui.zhang@mediatek.com> > > --- > > drivers/pci/host/pcie-mediatek.c | 12 ++++++++++++ > > include/linux/pci_ids.h | 3 +++ > > 2 files changed, 15 insertions(+) > > > > diff --git a/drivers/pci/host/pcie-mediatek.c b/drivers/pci/host/pcie-mediatek.c > > index fc29a9a..0ef33e4 100644 > > --- a/drivers/pci/host/pcie-mediatek.c > > +++ b/drivers/pci/host/pcie-mediatek.c > > @@ -74,6 +74,10 @@ > > > > /* PCIe V2 per-port registers */ > > #define PCIE_MSI_VECTOR 0x0c0 > > + > > +#define PCIE_CONF_ID 0x100 > > +#define PCIE_CONF_CLASS 0x104 > > + > > #define PCIE_INT_MASK 0x420 > > #define INTX_MASK GENMASK(19, 16) > > #define INTX_SHIFT 16 > > @@ -393,6 +397,14 @@ static int mtk_pcie_startup_port_v2(struct mtk_pcie_port *port) > > val |= PCIE_CSR_LTSSM_EN(port->slot) | > > PCIE_CSR_ASPM_L1_EN(port->slot); > > writel(val, pcie->base + PCIE_SYS_CFG_V2); > > + > > + /* Set up vendor ID and device ID for MT7622*/ > > + val = PCI_VENDOR_ID_MEDIATEK | (PCI_DEVICE_ID_MT7622 << 16); > > + writel(val, port->base + PCIE_CONF_ID); > > IMHO, this is a general function so you can ignore "device ID for > MT7622" here, but just make sure class code/vendor ID correct. Hmm, this condition is only for MT7622 for now. Well, host driver and framework does not cares about the device ID for host bridge. I guess I can bypass the setting of device ID. thanks. > > > + /* Set up class code for MT7622 */ > > + val = PCI_CLASS_BRIDGE_PCI << 16; > > + writel(val, port->base + PCIE_CONF_CLASS); > > } > > > > /* Assert all reset signals */ > > diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h > > index ab20dc5..000c5df 100644 > ^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2017-12-26 1:41 UTC | newest] Thread overview: 5+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2017-12-22 5:39 [PATCH v4 0/2] PCI: mediatek: Fixups for the IRQ handle routine and MT7622's class code honghui.zhang at mediatek.com 2017-12-22 5:39 ` [PATCH v4 1/2] PCI: mediatek: Clear IRQ status after IRQ dispatched to avoid reentry honghui.zhang at mediatek.com 2017-12-22 5:39 ` [PATCH v4 2/2] PCI: mediatek: Set up class type and vendor ID for MT7622 honghui.zhang at mediatek.com 2017-12-25 10:27 ` Ryder Lee 2017-12-26 1:41 ` Honghui Zhang
This is a public inbox, see mirroring instructions for how to clone and mirror all data and code used for this inbox