Re: [PATCH 2/5] irqchip/irq-imx-gpcv2: Share reg offset calculation code

From: Lucas Stach <l.stach@pengutronix.de>
To: Andrey Smirnov <andrew.smirnov@gmail.com>,
	Marc Zyngier <marc.zyngier@arm.com>
Cc: "A.s. Dong" <aisheng.dong@nxp.com>,
	Richard Zhu <hongxing.zhu@nxp.com>,
	Jason Cooper <jason@lakedaemon.net>,
	linux-kernel@vger.kernel.org, linux-imx@nxp.com,
	Thomas Gleixner <tglx@linutronix.de>,
	Leonard Crestez <leonard.crestez@nxp.com>,
	cphealy@gmail.com, linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH 2/5] irqchip/irq-imx-gpcv2: Share reg offset calculation code
Date: Thu, 06 Dec 2018 12:11:29 +0100	[thread overview]
Message-ID: <1544094689.3709.59.camel@pengutronix.de> (raw)
In-Reply-To: <20181206073125.7255-3-andrew.smirnov@gmail.com>

Am Mittwoch, den 05.12.2018, 23:31 -0800 schrieb Andrey Smirnov:
> Move identical offset calculation code into a small helper function
> and make use of it in the rest of the code.
> 
> > Cc: Thomas Gleixner <tglx@linutronix.de>
> > Cc: Jason Cooper <jason@lakedaemon.net>
> > Cc: Marc Zyngier <marc.zyngier@arm.com>
> Cc: cphealy@gmail.com
> Cc: l.stach@pengutronix.de
> > Cc: Leonard Crestez <leonard.crestez@nxp.com>
> > Cc: "A.s. Dong" <aisheng.dong@nxp.com>
> > Cc: Richard Zhu <hongxing.zhu@nxp.com>
> Cc: linux-imx@nxp.com
> Cc: linux-arm-kernel@lists.infradead.org
> Cc: linux-kernel@vger.kernel.org
> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>

Nice cleanup!

Reviewed-by: Lucas Stach <l.stach@pengutronix.de>

> ---
>  drivers/irqchip/irq-imx-gpcv2.c | 18 ++++++++++--------
>  1 file changed, 10 insertions(+), 8 deletions(-)
> 
> diff --git a/drivers/irqchip/irq-imx-gpcv2.c b/drivers/irqchip/irq-imx-gpcv2.c
> index cbed00319315..b262ba8b2652 100644
> --- a/drivers/irqchip/irq-imx-gpcv2.c
> +++ b/drivers/irqchip/irq-imx-gpcv2.c
> @@ -28,6 +28,11 @@ struct gpcv2_irqchip_data {
>  
>  static struct gpcv2_irqchip_data *imx_gpcv2_instance;
>  
> +static void __iomem *gpcv2_idx_to_reg(struct gpcv2_irqchip_data *cd, int i)
> +{
> > +	return cd->gpc_base + cd->cpu2wakeup + i * 4;
> +}
> +
>  static int gpcv2_wakeup_source_save(void)
>  {
> >  	struct gpcv2_irqchip_data *cd;
> @@ -39,7 +44,7 @@ static int gpcv2_wakeup_source_save(void)
> >  		return 0;
>  
> >  	for (i = 0; i < IMR_NUM; i++) {
> > -		reg = cd->gpc_base + cd->cpu2wakeup + i * 4;
> > +		reg = gpcv2_idx_to_reg(cd, i);
> >  		cd->saved_irq_mask[i] = readl_relaxed(reg);
> >  		writel_relaxed(cd->wakeup_sources[i], reg);
> >  	}
> @@ -50,17 +55,14 @@ static int gpcv2_wakeup_source_save(void)
>  static void gpcv2_wakeup_source_restore(void)
>  {
> >  	struct gpcv2_irqchip_data *cd;
> > -	void __iomem *reg;
> >  	int i;
>  
> >  	cd = imx_gpcv2_instance;
> >  	if (!cd)
> >  		return;
>  
> > -	for (i = 0; i < IMR_NUM; i++) {
> > -		reg = cd->gpc_base + cd->cpu2wakeup + i * 4;
> > -		writel_relaxed(cd->saved_irq_mask[i], reg);
> > -	}
> > +	for (i = 0; i < IMR_NUM; i++)
> > +		writel_relaxed(cd->saved_irq_mask[i], gpcv2_idx_to_reg(cd, i));
>  }
>  
>  static struct syscore_ops imx_gpcv2_syscore_ops = {
> @@ -97,7 +99,7 @@ static void imx_gpcv2_irq_unmask(struct irq_data *d)
> >  	u32 val;
>  
> >  	raw_spin_lock(&cd->rlock);
> > -	reg = cd->gpc_base + cd->cpu2wakeup + d->hwirq / 32 * 4;
> > +	reg = gpcv2_idx_to_reg(cd, d->hwirq / 32);
> >  	val = readl_relaxed(reg);
> >  	val &= ~(1 << d->hwirq % 32);
> >  	writel_relaxed(val, reg);
> @@ -113,7 +115,7 @@ static void imx_gpcv2_irq_mask(struct irq_data *d)
> >  	u32 val;
>  
> >  	raw_spin_lock(&cd->rlock);
> > -	reg = cd->gpc_base + cd->cpu2wakeup + d->hwirq / 32 * 4;
> > +	reg = gpcv2_idx_to_reg(cd, d->hwirq / 32);
> >  	val = readl_relaxed(reg);
> >  	val |= 1 << (d->hwirq % 32);
> >  	writel_relaxed(val, reg);

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