* [PATCH] clk: mediatek: mt8195-infra_ao: Fix parent for infra_ao_hdmi_26m
@ 2025-07-24 8:38 AngeloGioacchino Del Regno
2025-09-21 16:31 ` Stephen Boyd
0 siblings, 1 reply; 2+ messages in thread
From: AngeloGioacchino Del Regno @ 2025-07-24 8:38 UTC (permalink / raw)
To: sboyd
Cc: mturquette, matthias.bgg, angelogioacchino.delregno,
u.kleine-koenig, geert+renesas, chun-jie.chen, wenst, linux-clk,
linux-kernel, linux-arm-kernel, linux-mediatek, kernel
The infrastructure gate for the HDMI specific crystal needs the
top_hdmi_xtal clock to be configured in order to ungate the 26m
clock to the HDMI IP, and it wouldn't work without.
Reparent the infra_ao_hdmi_26m clock to top_hdmi_xtal to fix that.
Fixes: e2edf59dec0b ("clk: mediatek: Add MT8195 infrastructure clock support")
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
drivers/clk/mediatek/clk-mt8195-infra_ao.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/mediatek/clk-mt8195-infra_ao.c b/drivers/clk/mediatek/clk-mt8195-infra_ao.c
index bb648a88e43a..ad47fdb23460 100644
--- a/drivers/clk/mediatek/clk-mt8195-infra_ao.c
+++ b/drivers/clk/mediatek/clk-mt8195-infra_ao.c
@@ -103,7 +103,7 @@ static const struct mtk_gate infra_ao_clks[] = {
GATE_INFRA_AO0(CLK_INFRA_AO_CQ_DMA_FPC, "infra_ao_cq_dma_fpc", "fpc", 28),
GATE_INFRA_AO0(CLK_INFRA_AO_UART5, "infra_ao_uart5", "top_uart", 29),
/* INFRA_AO1 */
- GATE_INFRA_AO1(CLK_INFRA_AO_HDMI_26M, "infra_ao_hdmi_26m", "clk26m", 0),
+ GATE_INFRA_AO1(CLK_INFRA_AO_HDMI_26M, "infra_ao_hdmi_26m", "top_hdmi_xtal", 0),
GATE_INFRA_AO1(CLK_INFRA_AO_SPI0, "infra_ao_spi0", "top_spi", 1),
GATE_INFRA_AO1(CLK_INFRA_AO_MSDC0, "infra_ao_msdc0", "top_msdc50_0_hclk", 2),
GATE_INFRA_AO1(CLK_INFRA_AO_MSDC1, "infra_ao_msdc1", "top_axi", 4),
--
2.50.1
^ permalink raw reply related [flat|nested] 2+ messages in thread* Re: [PATCH] clk: mediatek: mt8195-infra_ao: Fix parent for infra_ao_hdmi_26m
2025-07-24 8:38 [PATCH] clk: mediatek: mt8195-infra_ao: Fix parent for infra_ao_hdmi_26m AngeloGioacchino Del Regno
@ 2025-09-21 16:31 ` Stephen Boyd
0 siblings, 0 replies; 2+ messages in thread
From: Stephen Boyd @ 2025-09-21 16:31 UTC (permalink / raw)
To: AngeloGioacchino Del Regno
Cc: mturquette, matthias.bgg, angelogioacchino.delregno,
u.kleine-koenig, geert+renesas, chun-jie.chen, wenst, linux-clk,
linux-kernel, linux-arm-kernel, linux-mediatek, kernel
Quoting AngeloGioacchino Del Regno (2025-07-24 01:38:28)
> The infrastructure gate for the HDMI specific crystal needs the
> top_hdmi_xtal clock to be configured in order to ungate the 26m
> clock to the HDMI IP, and it wouldn't work without.
>
> Reparent the infra_ao_hdmi_26m clock to top_hdmi_xtal to fix that.
>
> Fixes: e2edf59dec0b ("clk: mediatek: Add MT8195 infrastructure clock support")
> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> ---
Applied to clk-next
^ permalink raw reply [flat|nested] 2+ messages in thread
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2025-07-24 8:38 [PATCH] clk: mediatek: mt8195-infra_ao: Fix parent for infra_ao_hdmi_26m AngeloGioacchino Del Regno
2025-09-21 16:31 ` Stephen Boyd
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