Re: [PATCH v3 0/2] Add AM62P silicon revision detection via NVMEM

[Nishanth Menon <nm@ti.com>]

Hi Judith Mendez,

On Mon, 09 Feb 2026 11:23:28 -0600, Judith Mendez wrote:
> This series adds support for detecting AM62P silicon revisions using
> the NVMEM framework to read the GP_SW1 register.
> 
> Background:
> ===========
> On AM62P SoCs, the standard JTAGID register does not provide information
> on silicon revision, instead the GP_SW1 register contains the information
> needed for proper device identification.
> 
> [...]

I have applied the following to branch ti-drivers-soc-next on [1].
Thank you!

[1/2] dt-bindings: hwinfo: ti,k3-socinfo: Add nvmem-cells support
      commit: b0ea5175358f0872ffdc9c6073585637dc01815a
[2/2] soc: ti: k3-socinfo: Add support for AM62P variants via NVMEM
      commit: 97cfbd30525ef0df3de0681a4ca04a80a06d4f16

All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent up the chain during
the next merge window (or sooner if it is a relevant bug fix), however if
problems are discovered then the patch may be dropped or reverted.

You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.

If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.

Please add any relevant lists and maintainers to the CCs when replying
to this mail.

[1] https://git.kernel.org/pub/scm/linux/kernel/git/ti/linux.git
-- 
Regards,
Nishanth Menon
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