[PATCH 0/5] ARM: sun6i: dt: Add support for GMAC

[PATCH 0/5] ARM: sun6i: dt: Add support for GMAC

[Chen-Yu Tsai]

Hi Maxime,

This series add support for the GMAC in A31. The GMAC is the same as in
the A20, except it has an extra reset control. The GMAC clock module is
mostly the same as in the A20, without the extra dividers, which I left
out intentionally from the clock driver.

The register offsets and interrupts were copied from A31 SDK in Rhombus
Tech's repository. The pin muxes were from the EVB fex file. If you have
the A31 datasheet, you could double check them.

This series is based on current sunxi-next ( e8176a3b0 ).

As I don't have actual A31 hardware, this is only compile tested.
Please give it a try, and let me know if it works or not.


Cheers,
ChenYu


Chen-Yu Tsai (5):
  ARM: sun6i: dt: Add pin muxing options for GMAC
  ARM: sun6i: dt: Add GMAC clock node to the A31 DTSI
  ARM: sun6i: dt: Add A31 GMAC gigabit ethernet controller node
  ARM: sun6i: dt: Add ethernet alias for GMAC
  ARM: sun6i: columbus: Enable the GMAC

 arch/arm/boot/dts/sun6i-a31-colombus.dts | 12 +++++
 arch/arm/boot/dts/sun6i-a31.dtsi         | 87 ++++++++++++++++++++++++++++++++
 2 files changed, 99 insertions(+)

-- 
1.9.0

[PATCH 1/5] ARM: sun6i: dt: Add pin muxing options for GMAC

[Chen-Yu Tsai]

The A31 SoC has a GMAC gigabit ethernet controller supporting
MII, GMII, RGMII modes. Add pin muxing options for these modes.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
 arch/arm/boot/dts/sun6i-a31.dtsi | 42 ++++++++++++++++++++++++++++++++++++++++
 1 file changed, 42 insertions(+)

diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi
index 42f310a..4d2a2bf 100644
--- a/arch/arm/boot/dts/sun6i-a31.dtsi
+++ b/arch/arm/boot/dts/sun6i-a31.dtsi
@@ -257,6 +257,48 @@
 				allwinner,drive = <0>;
 				allwinner,pull = <0>;
 			};
+
+			gmac_pins_mii_a: gmac_mii at 0 {
+				allwinner,pins = "PA0", "PA1", "PA2", "PA3",
+						"PA8", "PA9", "PA11",
+						"PA12", "PA13", "PA14", "PA19",
+						"PA20", "PA21", "PA22", "PA23",
+						"PA24", "PA26", "PA27";
+				allwinner,function = "gmac";
+				allwinner,drive = <0>;
+				allwinner,pull = <0>;
+			};
+
+			gmac_pins_gmii_a: gmac_gmii at 0 {
+				allwinner,pins = "PA0", "PA1", "PA2", "PA3",
+						"PA4", "PA5", "PA6", "PA7",
+						"PA8", "PA9", "PA10", "PA11",
+						"PA12", "PA13", "PA14",	"PA15",
+						"PA16", "PA17", "PA18", "PA19",
+						"PA20", "PA21", "PA22", "PA23",
+						"PA24", "PA25", "PA26", "PA27";
+				allwinner,function = "gmac";
+				/*
+				 * data lines in GMII mode run at 125MHz and
+				 * might need a higher signal drive strength
+				 */
+				allwinner,drive = <2>;
+				allwinner,pull = <0>;
+			};
+
+			gmac_pins_rgmii_a: gmac_rgmii at 0 {
+				allwinner,pins = "PA0", "PA1", "PA2", "PA3",
+						"PA9", "PA10", "PA11",
+						"PA12", "PA13", "PA14", "PA19",
+						"PA20", "PA25", "PA26", "PA27";
+				allwinner,function = "gmac";
+				/*
+				 * data lines in RGMII mode use DDR mode
+				 * and need a higher signal drive strength
+				 */
+				allwinner,drive = <3>;
+				allwinner,pull = <0>;
+			};
 		};
 
 		ahb1_rst: reset at 01c202c0 {
-- 
1.9.0

[PATCH 2/5] ARM: sun6i: dt: Add GMAC clock node to the A31 DTSI

[Chen-Yu Tsai]

The GMAC uses 1 of 2 sources for its transmit clock, depending on the
PHY interface mode. Add both sources as dummy clocks, and as parents
to the GMAC clock node.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
 arch/arm/boot/dts/sun6i-a31.dtsi | 28 ++++++++++++++++++++++++++++
 1 file changed, 28 insertions(+)

diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi
index 4d2a2bf..ee09e4c 100644
--- a/arch/arm/boot/dts/sun6i-a31.dtsi
+++ b/arch/arm/boot/dts/sun6i-a31.dtsi
@@ -229,6 +229,34 @@
 			clocks = <&osc24M>, <&pll6>;
 			clock-output-names = "spi3";
 		};
+
+		/*
+		 * The following two are dummy clocks, placeholders used in the gmac_tx
+		 * clock. The gmac driver will choose one parent depending on the PHY
+		 * interface mode, using clk_set_rate auto-reparenting.
+		 * The actual TX clock rate is not controlled by the gmac_tx clock.
+		 */
+		mii_phy_tx_clk: clk at 1 {
+			#clock-cells = <0>;
+			compatible = "fixed-clock";
+			clock-frequency = <25000000>;
+			clock-output-names = "mii_phy_tx";
+		};
+
+		gmac_int_tx_clk: clk at 2 {
+			#clock-cells = <0>;
+			compatible = "fixed-clock";
+			clock-frequency = <125000000>;
+			clock-output-names = "gmac_int_tx";
+		};
+
+		gmac_tx_clk: clk at 01c200d0 {
+			#clock-cells = <0>;
+			compatible = "allwinner,sun7i-a20-gmac-clk";
+			reg = <0x01c200d0 0x4>;
+			clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>;
+			clock-output-names = "gmac_tx";
+		};
 	};
 
 	soc at 01c00000 {
-- 
1.9.0

[PATCH 3/5] ARM: sun6i: dt: Add A31 GMAC gigabit ethernet controller node

[Chen-Yu Tsai]

The A31 has the same GMAC found on the A20 SoC, except it has
an extra reset control.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
 arch/arm/boot/dts/sun6i-a31.dtsi | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi
index ee09e4c..e958d5f 100644
--- a/arch/arm/boot/dts/sun6i-a31.dtsi
+++ b/arch/arm/boot/dts/sun6i-a31.dtsi
@@ -429,6 +429,22 @@
 			status = "disabled";
 		};
 
+		gmac: ethernet at 01c30000 {
+			compatible = "allwinner,sun7i-a20-gmac";
+			reg = <0x01c30000 0x1054>;
+			interrupts = <0 82 4>;
+			interrupt-names = "macirq";
+			clocks = <&ahb1_gates 17>, <&gmac_tx_clk>;
+			clock-names = "stmmaceth", "allwinner_gmac_tx";
+			resets = <&ahb1_rst 17>;
+			snps,pbl = <2>;
+			snps,fixed-burst;
+			snps,force_sf_dma_mode;
+			status = "disabled";
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
 		spi0: spi at 01c68000 {
 			compatible = "allwinner,sun6i-a31-spi";
 			reg = <0x01c68000 0x1000>;
-- 
1.9.0

[PATCH 4/5] ARM: sun6i: dt: Add ethernet alias for GMAC

[Chen-Yu Tsai]

Alias GMAC as ethernet0 so U-boot can fill in the MAC address.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
 arch/arm/boot/dts/sun6i-a31.dtsi | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi
index e958d5f..02d2270 100644
--- a/arch/arm/boot/dts/sun6i-a31.dtsi
+++ b/arch/arm/boot/dts/sun6i-a31.dtsi
@@ -23,6 +23,7 @@
 		serial3 = &uart3;
 		serial4 = &uart4;
 		serial5 = &uart5;
+		ethernet0 = &gmac;
 	};
 
 
-- 
1.9.0

[PATCH 5/5] ARM: sun6i: columbus: Enable the GMAC

[Chen-Yu Tsai]

The A31 Colombus board uses the GMAC with a Realtek RTL8211E-VB RGMII phy.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
 arch/arm/boot/dts/sun6i-a31-colombus.dts | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/arch/arm/boot/dts/sun6i-a31-colombus.dts b/arch/arm/boot/dts/sun6i-a31-colombus.dts
index e5adae3..19a0385 100644
--- a/arch/arm/boot/dts/sun6i-a31-colombus.dts
+++ b/arch/arm/boot/dts/sun6i-a31-colombus.dts
@@ -28,5 +28,17 @@
 			pinctrl-0 = <&uart0_pins_a>;
 			status = "okay";
 		};
+
+		gmac: ethernet at 01c30000 {
+			pinctrl-names = "default";
+			pinctrl-0 = <&gmac_pins_rgmii_a>;
+			phy = <&phy1>;
+			phy-mode = "rgmii";
+			status = "okay";
+
+			phy1: ethernet-phy at 1 {
+				reg = <1>;
+			};
+		};
 	};
 };
-- 
1.9.0

[PATCH 0/5] ARM: sun6i: dt: Add support for GMAC

[Maxime Ripard]

Hi,

On Thu, Mar 06, 2014 at 12:27:10AM +0800, Chen-Yu Tsai wrote:
> Hi Maxime,
> 
> This series add support for the GMAC in A31. The GMAC is the same as in
> the A20, except it has an extra reset control. The GMAC clock module is
> mostly the same as in the A20, without the extra dividers, which I left
> out intentionally from the clock driver.
> 
> The register offsets and interrupts were copied from A31 SDK in Rhombus
> Tech's repository. The pin muxes were from the EVB fex file. If you have
> the A31 datasheet, you could double check them.
> 
> This series is based on current sunxi-next ( e8176a3b0 ).
> 
> As I don't have actual A31 hardware, this is only compile tested.
> Please give it a try, and let me know if it works or not.

I finally took some time to give it a try.

It actually doesn't work, but presumably not because of you, but
because the PHY is powered up by the PMIC, which is not supported
yet. This is the same situation on Hans' Melee, so we will only be
ably to test it whenever we have support for the AXP :(

Thanks for your efforts,
Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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[PATCH 3/5] ARM: sun6i: dt: Add A31 GMAC gigabit ethernet controller node

[Maxime Ripard]

On Thu, Mar 06, 2014 at 12:27:13AM +0800, Chen-Yu Tsai wrote:
> The A31 has the same GMAC found on the A20 SoC, except it has
> an extra reset control.
> 
> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
> ---
>  arch/arm/boot/dts/sun6i-a31.dtsi | 16 ++++++++++++++++
>  1 file changed, 16 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi
> index ee09e4c..e958d5f 100644
> --- a/arch/arm/boot/dts/sun6i-a31.dtsi
> +++ b/arch/arm/boot/dts/sun6i-a31.dtsi
> @@ -429,6 +429,22 @@
>  			status = "disabled";
>  		};
>  
> +		gmac: ethernet at 01c30000 {
> +			compatible = "allwinner,sun7i-a20-gmac";
> +			reg = <0x01c30000 0x1054>;
> +			interrupts = <0 82 4>;
> +			interrupt-names = "macirq";
> +			clocks = <&ahb1_gates 17>, <&gmac_tx_clk>;
> +			clock-names = "stmmaceth", "allwinner_gmac_tx";
> +			resets = <&ahb1_rst 17>;

You need an additional
			reset-names = "stmmaceth";

Thanks!

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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