[PATCH 0/3] arm64: dts: uniphier: switch to PSCI, DT-side support for cpufreq driver

[PATCH 0/3] arm64: dts: uniphier: switch to PSCI, DT-side support for cpufreq driver

[Masahiro Yamada]

The UniPhier clock driver was merged, and now ARM Trusted Firmware
poring was finished.

Now, I can upstream more features with this platform.



Masahiro Yamada (3):
  arm64: dts: uniphier: switch over to PSCI enable method
  arm64: dts: uniphier: add CPU clock and OPP table for LD11 SoC
  arm64: dts: uniphier: add CPU clocks and OPP tables for LD20 SoC

 arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi |  51 +++++++++--
 arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi | 103 +++++++++++++++++++++--
 2 files changed, 140 insertions(+), 14 deletions(-)

-- 
1.9.1

[PATCH 1/3] arm64: dts: uniphier: switch over to PSCI enable method

[Masahiro Yamada]

At the first system bring-up, I chose to use spin-table because ARM
Trusted Firmware was not ready for this platform at that moment.

Actually, these SoCs are equipped with EL3 and able to provide PSCI.
Now I finished porting the ATF BL31 for the UniPhier platform, so it
is ready to migrate to PSCI enable method.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
---

 arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi | 13 ++++++++-----
 arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi | 19 ++++++++++---------
 2 files changed, 18 insertions(+), 14 deletions(-)

diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi b/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi
index da3cdd8..73e0acf 100644
--- a/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi
+++ b/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi
@@ -43,7 +43,7 @@
  *     OTHER DEALINGS IN THE SOFTWARE.
  */
 
-/memreserve/ 0x80000000 0x00000008;	/* cpu-release-addr */
+/memreserve/ 0x80000000 0x00080000;
 
 / {
 	compatible = "socionext,uniphier-ld11";
@@ -70,19 +70,22 @@
 			device_type = "cpu";
 			compatible = "arm,cortex-a53", "arm,armv8";
 			reg = <0 0x000>;
-			enable-method = "spin-table";
-			cpu-release-addr = <0 0x80000000>;
+			enable-method = "psci";
 		};
 
 		cpu1: cpu at 1 {
 			device_type = "cpu";
 			compatible = "arm,cortex-a53", "arm,armv8";
 			reg = <0 0x001>;
-			enable-method = "spin-table";
-			cpu-release-addr = <0 0x80000000>;
+			enable-method = "psci";
 		};
 	};
 
+	psci {
+		compatible = "arm,psci-1.0";
+		method = "smc";
+	};
+
 	clocks {
 		refclk: ref {
 			compatible = "fixed-clock";
diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi b/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi
index efb47ea..6f48e82 100644
--- a/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi
+++ b/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi
@@ -43,7 +43,7 @@
  *     OTHER DEALINGS IN THE SOFTWARE.
  */
 
-/memreserve/ 0x80000000 0x00000008;	/* cpu-release-addr */
+/memreserve/ 0x80000000 0x00080000;
 
 / {
 	compatible = "socionext,uniphier-ld20";
@@ -79,35 +79,36 @@
 			device_type = "cpu";
 			compatible = "arm,cortex-a72", "arm,armv8";
 			reg = <0 0x000>;
-			enable-method = "spin-table";
-			cpu-release-addr = <0 0x80000000>;
+			enable-method = "psci";
 		};
 
 		cpu1: cpu at 1 {
 			device_type = "cpu";
 			compatible = "arm,cortex-a72", "arm,armv8";
 			reg = <0 0x001>;
-			enable-method = "spin-table";
-			cpu-release-addr = <0 0x80000000>;
+			enable-method = "psci";
 		};
 
 		cpu2: cpu at 100 {
 			device_type = "cpu";
 			compatible = "arm,cortex-a53", "arm,armv8";
 			reg = <0 0x100>;
-			enable-method = "spin-table";
-			cpu-release-addr = <0 0x80000000>;
+			enable-method = "psci";
 		};
 
 		cpu3: cpu at 101 {
 			device_type = "cpu";
 			compatible = "arm,cortex-a53", "arm,armv8";
 			reg = <0 0x101>;
-			enable-method = "spin-table";
-			cpu-release-addr = <0 0x80000000>;
+			enable-method = "psci";
 		};
 	};
 
+	psci {
+		compatible = "arm,psci-1.0";
+		method = "smc";
+	};
+
 	clocks {
 		refclk: ref {
 			compatible = "fixed-clock";
-- 
1.9.1

[PATCH 2/3] arm64: dts: uniphier: add CPU clock and OPP table for LD11 SoC

[Masahiro Yamada]

Add a CPU clock to every CPU node and a CPU OPP table to use the
generic cpufreq driver.

Note:
clock-latency-ns (300ns) was calculated based on the CPU-gear switch
sequencer spec; it takes 12 clock cycles on the sequencer running
at 50 MHz, plus a bit additional latency.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
---

 arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi | 38 ++++++++++++++++++++++++
 1 file changed, 38 insertions(+)

diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi b/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi
index 73e0acf..e3eb10f 100644
--- a/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi
+++ b/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi
@@ -70,14 +70,18 @@
 			device_type = "cpu";
 			compatible = "arm,cortex-a53", "arm,armv8";
 			reg = <0 0x000>;
+			clocks = <&sys_clk 33>;
 			enable-method = "psci";
+			operating-points-v2 = <&cluster0_opp>;
 		};
 
 		cpu1: cpu at 1 {
 			device_type = "cpu";
 			compatible = "arm,cortex-a53", "arm,armv8";
 			reg = <0 0x001>;
+			clocks = <&sys_clk 33>;
 			enable-method = "psci";
+			operating-points-v2 = <&cluster0_opp>;
 		};
 	};
 
@@ -86,6 +90,40 @@
 		method = "smc";
 	};
 
+	cluster0_opp: opp_table {
+		compatible = "operating-points-v2";
+		opp-shared;
+
+		opp at 245000000 {
+			opp-hz = /bits/ 64 <245000000>;
+			clock-latency-ns = <300>;
+		};
+		opp at 250000000 {
+			opp-hz = /bits/ 64 <250000000>;
+			clock-latency-ns = <300>;
+		};
+		opp at 490000000 {
+			opp-hz = /bits/ 64 <490000000>;
+			clock-latency-ns = <300>;
+		};
+		opp at 500000000 {
+			opp-hz = /bits/ 64 <500000000>;
+			clock-latency-ns = <300>;
+		};
+		opp at 653333333 {
+			opp-hz = /bits/ 64 <653334000>;
+			clock-latency-ns = <300>;
+		};
+		opp at 666666666 {
+			opp-hz = /bits/ 64 <666667000>;
+			clock-latency-ns = <300>;
+		};
+		opp at 980000000 {
+			opp-hz = /bits/ 64 <980000000>;
+			clock-latency-ns = <300>;
+		};
+	};
+
 	clocks {
 		refclk: ref {
 			compatible = "fixed-clock";
-- 
1.9.1

[PATCH 2/3] arm64: dts: uniphier: add CPU clock and OPP table for LD11 SoC

[Viresh Kumar]

On 16-10-16, 23:59, Masahiro Yamada wrote:
> +	cluster0_opp: opp_table {
> +		compatible = "operating-points-v2";
> +		opp-shared;
> +
> +		opp at 245000000 {
> +			opp-hz = /bits/ 64 <245000000>;
> +			clock-latency-ns = <300>;
> +		};
> +		opp at 250000000 {
> +			opp-hz = /bits/ 64 <250000000>;
> +			clock-latency-ns = <300>;
> +		};
> +		opp at 490000000 {
> +			opp-hz = /bits/ 64 <490000000>;
> +			clock-latency-ns = <300>;
> +		};
> +		opp at 500000000 {
> +			opp-hz = /bits/ 64 <500000000>;
> +			clock-latency-ns = <300>;
> +		};
> +		opp at 653333333 {

Why isn't ^^ matching with below values ? Same in next patch as well.

> +			opp-hz = /bits/ 64 <653334000>;
> +			clock-latency-ns = <300>;
> +		};
> +		opp at 666666666 {
> +			opp-hz = /bits/ 64 <666667000>;
> +			clock-latency-ns = <300>;
> +		};
> +		opp at 980000000 {
> +			opp-hz = /bits/ 64 <980000000>;
> +			clock-latency-ns = <300>;
> +		};
> +	};
> +
>  	clocks {
>  		refclk: ref {
>  			compatible = "fixed-clock";
> -- 
> 1.9.1

-- 
viresh

[PATCH 2/3] arm64: dts: uniphier: add CPU clock and OPP table for LD11 SoC

[Masahiro Yamada]

Hi Viresh,


2016-10-18 20:25 GMT+09:00 Viresh Kumar <viresh.kumar@linaro.org>:
> On 16-10-16, 23:59, Masahiro Yamada wrote:
>> +     cluster0_opp: opp_table {
>> +             compatible = "operating-points-v2";
>> +             opp-shared;
>> +
>> +             opp at 245000000 {
>> +                     opp-hz = /bits/ 64 <245000000>;
>> +                     clock-latency-ns = <300>;
>> +             };
>> +             opp at 250000000 {
>> +                     opp-hz = /bits/ 64 <250000000>;
>> +                     clock-latency-ns = <300>;
>> +             };
>> +             opp at 490000000 {
>> +                     opp-hz = /bits/ 64 <490000000>;
>> +                     clock-latency-ns = <300>;
>> +             };
>> +             opp at 500000000 {
>> +                     opp-hz = /bits/ 64 <500000000>;
>> +                     clock-latency-ns = <300>;
>> +             };
>> +             opp at 653333333 {
>
> Why isn't ^^ matching with below values ? Same in next patch as well.



When I try to update /sys/devices/system/cpu/cpufreq/policy*/scaling_max_freq,
it did not work as I had expected.


scaling_max_freq is specified by kHz unit,
on the other hand, clock frequency in the clk driver is specified by Hz.



If the operating point is 653333kHz, the cpufreq requests
the clk driver to set 653333000, but it is lower than
the exact clock, 653333333.
So, the next lower frequency, 500000000 is selected.
As a result, the operating point 653333kHz is never enabled.


So, the operating point must be equal or a little bit bigger.


Do you know a better way to solve this distortion?


-- 
Best Regards
Masahiro Yamada

[PATCH 2/3] arm64: dts: uniphier: add CPU clock and OPP table for LD11 SoC

[Viresh Kumar]

On 19-10-16, 17:33, Masahiro Yamada wrote:
> Hi Viresh,
> 
> 
> 2016-10-18 20:25 GMT+09:00 Viresh Kumar <viresh.kumar@linaro.org>:
> > On 16-10-16, 23:59, Masahiro Yamada wrote:
> >> +     cluster0_opp: opp_table {
> >> +             compatible = "operating-points-v2";
> >> +             opp-shared;
> >> +
> >> +             opp at 245000000 {
> >> +                     opp-hz = /bits/ 64 <245000000>;
> >> +                     clock-latency-ns = <300>;
> >> +             };
> >> +             opp at 250000000 {
> >> +                     opp-hz = /bits/ 64 <250000000>;
> >> +                     clock-latency-ns = <300>;
> >> +             };
> >> +             opp at 490000000 {
> >> +                     opp-hz = /bits/ 64 <490000000>;
> >> +                     clock-latency-ns = <300>;
> >> +             };
> >> +             opp at 500000000 {
> >> +                     opp-hz = /bits/ 64 <500000000>;
> >> +                     clock-latency-ns = <300>;
> >> +             };
> >> +             opp at 653333333 {
> >
> > Why isn't ^^ matching with below values ? Same in next patch as well.
> 
> 
> 
> When I try to update /sys/devices/system/cpu/cpufreq/policy*/scaling_max_freq,
> it did not work as I had expected.
> 
> 
> scaling_max_freq is specified by kHz unit,
> on the other hand, clock frequency in the clk driver is specified by Hz.
> 
> 
> 
> If the operating point is 653333kHz, the cpufreq requests
> the clk driver to set 653333000, but it is lower than
> the exact clock, 653333333.
> So, the next lower frequency, 500000000 is selected.
> As a result, the operating point 653333kHz is never enabled.
> 
> 
> So, the operating point must be equal or a little bit bigger.
> 
> 
> Do you know a better way to solve this distortion?

I am not sure about how to fix that problem but there is no reason to
have the exact frequency in opp@*** name. Just use what you have used
in opp-hz line and you will have the exact same behavior.

Right now, its a bit confusing if we read the DT.

-- 
viresh

[PATCH 3/3] arm64: dts: uniphier: add CPU clocks and OPP tables for LD20 SoC

[Masahiro Yamada]

Add a CPU clock to every CPU node and CPU OPP tables to use the
generic cpufreq driver.  All the CPUs in each cluster share the
same OPP table.

Note:
clock-latency-ns (300ns) was calculated based on the CPU-gear switch
sequencer spec; it takes 12 clock cycles on the sequencer running
at 50 MHz, plus a bit additional latency.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
---

 arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi | 84 ++++++++++++++++++++++++
 1 file changed, 84 insertions(+)

diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi b/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi
index 6f48e82..0ebcdbb 100644
--- a/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi
+++ b/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi
@@ -79,28 +79,36 @@
 			device_type = "cpu";
 			compatible = "arm,cortex-a72", "arm,armv8";
 			reg = <0 0x000>;
+			clocks = <&sys_clk 32>;
 			enable-method = "psci";
+			operating-points-v2 = <&cluster0_opp>;
 		};
 
 		cpu1: cpu at 1 {
 			device_type = "cpu";
 			compatible = "arm,cortex-a72", "arm,armv8";
 			reg = <0 0x001>;
+			clocks = <&sys_clk 32>;
 			enable-method = "psci";
+			operating-points-v2 = <&cluster0_opp>;
 		};
 
 		cpu2: cpu at 100 {
 			device_type = "cpu";
 			compatible = "arm,cortex-a53", "arm,armv8";
 			reg = <0 0x100>;
+			clocks = <&sys_clk 33>;
 			enable-method = "psci";
+			operating-points-v2 = <&cluster1_opp>;
 		};
 
 		cpu3: cpu at 101 {
 			device_type = "cpu";
 			compatible = "arm,cortex-a53", "arm,armv8";
 			reg = <0 0x101>;
+			clocks = <&sys_clk 33>;
 			enable-method = "psci";
+			operating-points-v2 = <&cluster1_opp>;
 		};
 	};
 
@@ -109,6 +117,82 @@
 		method = "smc";
 	};
 
+	cluster0_opp: opp_table0 {
+		compatible = "operating-points-v2";
+		opp-shared;
+
+		opp at 250000000 {
+			opp-hz = /bits/ 64 <250000000>;
+			clock-latency-ns = <300>;
+		};
+		opp at 275000000 {
+			opp-hz = /bits/ 64 <275000000>;
+			clock-latency-ns = <300>;
+		};
+		opp at 500000000 {
+			opp-hz = /bits/ 64 <500000000>;
+			clock-latency-ns = <300>;
+		};
+		opp at 550000000 {
+			opp-hz = /bits/ 64 <550000000>;
+			clock-latency-ns = <300>;
+		};
+		opp at 666666666 {
+			opp-hz = /bits/ 64 <666667000>;
+			clock-latency-ns = <300>;
+		};
+		opp at 733333333 {
+			opp-hz = /bits/ 64 <733334000>;
+			clock-latency-ns = <300>;
+		};
+		opp at 1000000000 {
+			opp-hz = /bits/ 64 <1000000000>;
+			clock-latency-ns = <300>;
+		};
+		opp at 1100000000 {
+			opp-hz = /bits/ 64 <1100000000>;
+			clock-latency-ns = <300>;
+		};
+	};
+
+	cluster1_opp: opp_table1 {
+		compatible = "operating-points-v2";
+		opp-shared;
+
+		opp at 250000000 {
+			opp-hz = /bits/ 64 <250000000>;
+			clock-latency-ns = <300>;
+		};
+		opp at 275000000 {
+			opp-hz = /bits/ 64 <275000000>;
+			clock-latency-ns = <300>;
+		};
+		opp at 500000000 {
+			opp-hz = /bits/ 64 <500000000>;
+			clock-latency-ns = <300>;
+		};
+		opp at 550000000 {
+			opp-hz = /bits/ 64 <550000000>;
+			clock-latency-ns = <300>;
+		};
+		opp at 666666666 {
+			opp-hz = /bits/ 64 <666667000>;
+			clock-latency-ns = <300>;
+		};
+		opp at 733333333 {
+			opp-hz = /bits/ 64 <733334000>;
+			clock-latency-ns = <300>;
+		};
+		opp at 1000000000 {
+			opp-hz = /bits/ 64 <1000000000>;
+			clock-latency-ns = <300>;
+		};
+		opp at 1100000000 {
+			opp-hz = /bits/ 64 <1100000000>;
+			clock-latency-ns = <300>;
+		};
+	};
+
 	clocks {
 		refclk: ref {
 			compatible = "fixed-clock";
-- 
1.9.1