* [PATCH v3 1/2] arm64: dts: uniphier: add CPU clock and OPP table for LD11 SoC
@ 2016-10-20 4:44 Masahiro Yamada
2016-10-20 4:44 ` [PATCH v3 2/2] arm64: dts: uniphier: add CPU clocks and OPP tables for LD20 SoC Masahiro Yamada
2016-10-20 4:47 ` [PATCH v3 1/2] arm64: dts: uniphier: add CPU clock and OPP table for LD11 SoC Viresh Kumar
0 siblings, 2 replies; 3+ messages in thread
From: Masahiro Yamada @ 2016-10-20 4:44 UTC (permalink / raw)
To: linux-arm-kernel
Add a CPU clock to every CPU node and a CPU OPP table to use the
generic cpufreq driver.
Note:
clock-latency-ns (300ns) was calculated based on the CPU-gear switch
sequencer spec; it takes 12 clock cycles on the sequencer running
at 50 MHz, plus a bit additional latency.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
---
Changes in v2:
- Match the node name to the opp-hz property.
arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi | 38 ++++++++++++++++++++++++
1 file changed, 38 insertions(+)
diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi b/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi
index 73e0acf..bb05f0a 100644
--- a/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi
+++ b/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi
@@ -70,14 +70,18 @@
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0 0x000>;
+ clocks = <&sys_clk 33>;
enable-method = "psci";
+ operating-points-v2 = <&cluster0_opp>;
};
cpu1: cpu at 1 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0 0x001>;
+ clocks = <&sys_clk 33>;
enable-method = "psci";
+ operating-points-v2 = <&cluster0_opp>;
};
};
@@ -86,6 +90,40 @@
method = "smc";
};
+ cluster0_opp: opp_table {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp at 245000000 {
+ opp-hz = /bits/ 64 <245000000>;
+ clock-latency-ns = <300>;
+ };
+ opp at 250000000 {
+ opp-hz = /bits/ 64 <250000000>;
+ clock-latency-ns = <300>;
+ };
+ opp at 490000000 {
+ opp-hz = /bits/ 64 <490000000>;
+ clock-latency-ns = <300>;
+ };
+ opp at 500000000 {
+ opp-hz = /bits/ 64 <500000000>;
+ clock-latency-ns = <300>;
+ };
+ opp at 653334000 {
+ opp-hz = /bits/ 64 <653334000>;
+ clock-latency-ns = <300>;
+ };
+ opp at 666667000 {
+ opp-hz = /bits/ 64 <666667000>;
+ clock-latency-ns = <300>;
+ };
+ opp at 980000000 {
+ opp-hz = /bits/ 64 <980000000>;
+ clock-latency-ns = <300>;
+ };
+ };
+
clocks {
refclk: ref {
compatible = "fixed-clock";
--
1.9.1
^ permalink raw reply related [flat|nested] 3+ messages in thread* [PATCH v3 2/2] arm64: dts: uniphier: add CPU clocks and OPP tables for LD20 SoC
2016-10-20 4:44 [PATCH v3 1/2] arm64: dts: uniphier: add CPU clock and OPP table for LD11 SoC Masahiro Yamada
@ 2016-10-20 4:44 ` Masahiro Yamada
2016-10-20 4:47 ` [PATCH v3 1/2] arm64: dts: uniphier: add CPU clock and OPP table for LD11 SoC Viresh Kumar
1 sibling, 0 replies; 3+ messages in thread
From: Masahiro Yamada @ 2016-10-20 4:44 UTC (permalink / raw)
To: linux-arm-kernel
Add a CPU clock to every CPU node and CPU OPP tables to use the
generic cpufreq driver. All the CPUs in each cluster share the
same OPP table.
Note:
clock-latency-ns (300ns) was calculated based on the CPU-gear switch
sequencer spec; it takes 12 clock cycles on the sequencer running
at 50 MHz, plus a bit additional latency.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
- Fix cluster1 OPP as well.
---
Changes in v2:
- Match the node name to the opp-hz property.
arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi | 84 ++++++++++++++++++++++++
1 file changed, 84 insertions(+)
diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi b/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi
index 6f48e82..a9a08dd 100644
--- a/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi
+++ b/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi
@@ -79,28 +79,36 @@
device_type = "cpu";
compatible = "arm,cortex-a72", "arm,armv8";
reg = <0 0x000>;
+ clocks = <&sys_clk 32>;
enable-method = "psci";
+ operating-points-v2 = <&cluster0_opp>;
};
cpu1: cpu at 1 {
device_type = "cpu";
compatible = "arm,cortex-a72", "arm,armv8";
reg = <0 0x001>;
+ clocks = <&sys_clk 32>;
enable-method = "psci";
+ operating-points-v2 = <&cluster0_opp>;
};
cpu2: cpu at 100 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0 0x100>;
+ clocks = <&sys_clk 33>;
enable-method = "psci";
+ operating-points-v2 = <&cluster1_opp>;
};
cpu3: cpu at 101 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0 0x101>;
+ clocks = <&sys_clk 33>;
enable-method = "psci";
+ operating-points-v2 = <&cluster1_opp>;
};
};
@@ -109,6 +117,82 @@
method = "smc";
};
+ cluster0_opp: opp_table0 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp at 250000000 {
+ opp-hz = /bits/ 64 <250000000>;
+ clock-latency-ns = <300>;
+ };
+ opp at 275000000 {
+ opp-hz = /bits/ 64 <275000000>;
+ clock-latency-ns = <300>;
+ };
+ opp at 500000000 {
+ opp-hz = /bits/ 64 <500000000>;
+ clock-latency-ns = <300>;
+ };
+ opp at 550000000 {
+ opp-hz = /bits/ 64 <550000000>;
+ clock-latency-ns = <300>;
+ };
+ opp at 666667000 {
+ opp-hz = /bits/ 64 <666667000>;
+ clock-latency-ns = <300>;
+ };
+ opp at 733334000 {
+ opp-hz = /bits/ 64 <733334000>;
+ clock-latency-ns = <300>;
+ };
+ opp at 1000000000 {
+ opp-hz = /bits/ 64 <1000000000>;
+ clock-latency-ns = <300>;
+ };
+ opp at 1100000000 {
+ opp-hz = /bits/ 64 <1100000000>;
+ clock-latency-ns = <300>;
+ };
+ };
+
+ cluster1_opp: opp_table1 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp at 250000000 {
+ opp-hz = /bits/ 64 <250000000>;
+ clock-latency-ns = <300>;
+ };
+ opp at 275000000 {
+ opp-hz = /bits/ 64 <275000000>;
+ clock-latency-ns = <300>;
+ };
+ opp at 500000000 {
+ opp-hz = /bits/ 64 <500000000>;
+ clock-latency-ns = <300>;
+ };
+ opp at 550000000 {
+ opp-hz = /bits/ 64 <550000000>;
+ clock-latency-ns = <300>;
+ };
+ opp at 666667000 {
+ opp-hz = /bits/ 64 <666667000>;
+ clock-latency-ns = <300>;
+ };
+ opp at 733334000 {
+ opp-hz = /bits/ 64 <733334000>;
+ clock-latency-ns = <300>;
+ };
+ opp at 1000000000 {
+ opp-hz = /bits/ 64 <1000000000>;
+ clock-latency-ns = <300>;
+ };
+ opp at 1100000000 {
+ opp-hz = /bits/ 64 <1100000000>;
+ clock-latency-ns = <300>;
+ };
+ };
+
clocks {
refclk: ref {
compatible = "fixed-clock";
--
1.9.1
^ permalink raw reply related [flat|nested] 3+ messages in thread* [PATCH v3 1/2] arm64: dts: uniphier: add CPU clock and OPP table for LD11 SoC
2016-10-20 4:44 [PATCH v3 1/2] arm64: dts: uniphier: add CPU clock and OPP table for LD11 SoC Masahiro Yamada
2016-10-20 4:44 ` [PATCH v3 2/2] arm64: dts: uniphier: add CPU clocks and OPP tables for LD20 SoC Masahiro Yamada
@ 2016-10-20 4:47 ` Viresh Kumar
1 sibling, 0 replies; 3+ messages in thread
From: Viresh Kumar @ 2016-10-20 4:47 UTC (permalink / raw)
To: linux-arm-kernel
On 20-10-16, 13:44, Masahiro Yamada wrote:
> Add a CPU clock to every CPU node and a CPU OPP table to use the
> generic cpufreq driver.
>
> Note:
> clock-latency-ns (300ns) was calculated based on the CPU-gear switch
> sequencer spec; it takes 12 clock cycles on the sequencer running
> at 50 MHz, plus a bit additional latency.
>
> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
> ---
>
> Changes in v2:
> - Match the node name to the opp-hz property.
For both the patches ..
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
--
viresh
^ permalink raw reply [flat|nested] 3+ messages in thread
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2016-10-20 4:44 [PATCH v3 1/2] arm64: dts: uniphier: add CPU clock and OPP table for LD11 SoC Masahiro Yamada
2016-10-20 4:44 ` [PATCH v3 2/2] arm64: dts: uniphier: add CPU clocks and OPP tables for LD20 SoC Masahiro Yamada
2016-10-20 4:47 ` [PATCH v3 1/2] arm64: dts: uniphier: add CPU clock and OPP table for LD11 SoC Viresh Kumar
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