[PATCH 0/7] Pad retentions support for Exynos5433

[PATCH 0/7] Pad retentions support for Exynos5433

[Marek Szyprowski]

Hello,

This patchset is a first step to add support for all power domains on
Exynos5433 SoCs. This patchset contains patches for Exynos pin control
driver and Exynos LPASS MFD driver, which are needed to make the
platform ready for adding power domains support.

Patches in this patchset depends on each other. They are order in such a
way to make the changes bisectable.

Patch #3 has runtime dependency on #1.
Patch #5 has runtime dependency on #3.
Patch #6 has runtime dependency on #4.

This patchset also directly depends on the "Move pad retention control to
Exynos pin controller driver" patchset:
https://www.spinics.net/lists/arm-kernel/msg556074.html

Patches have been generated on top of linux-next from 25th January 2017.

This is a part of a larger task, which goal is to add support for power
domains on Exynos5433 SoCs / TM2 boards. All patches needed to get it
working have been pushed to the following git repo:
https://git.linaro.org/people/marek.szyprowski/linux-srpol.git v4.10-next-tm2-pd

Best regards
Marek Szyprowski
Samsung R&D Institute Poland


Patch summary:

Marek Szyprowski (7):
  soc: samsung: pmu: Add dummy support for Exynos5433 SoC
  pinctrl: samsung: Ensure that pad retention is disabled on driver init
  pinctrl: samsung: Add support for pad retention control for Exynos5433
    SoCs
  arm64: dts: exynos: Add clocks to Exynos5433 LPASS module
  mfd: exynos-lpass: Remove pad retention control
  mfd: exynos-lpass: Add support for clocks
  mfd: exynos-lpass: Add runtime PM support

 .../bindings/mfd/samsung,exynos5433-lpass.txt      |  8 ++-
 arch/arm64/boot/dts/exynos/exynos5433.dtsi         |  2 +
 drivers/mfd/exynos-lpass.c                         | 35 ++++++------
 drivers/pinctrl/samsung/pinctrl-exynos.c           | 63 ++++++++++++++++++++++
 drivers/soc/samsung/exynos-pmu.c                   |  4 +-
 include/linux/mfd/syscon/exynos5-pmu.h             |  3 --
 include/linux/soc/samsung/exynos-regs-pmu.h        | 19 +++++++
 7 files changed, 110 insertions(+), 24 deletions(-)

-- 
1.9.1

[PATCH 1/7] soc: samsung: pmu: Add dummy support for Exynos5433 SoC

[Marek Szyprowski]

Add compatible for Exynos5433 SoC, so the driver will bind and let other
drivers to use PMU regmap.

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
---
 drivers/soc/samsung/exynos-pmu.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/soc/samsung/exynos-pmu.c b/drivers/soc/samsung/exynos-pmu.c
index 813df6e7292d..effb8a8a78c6 100644
--- a/drivers/soc/samsung/exynos-pmu.c
+++ b/drivers/soc/samsung/exynos-pmu.c
@@ -90,6 +90,8 @@ void exynos_sys_powerdown_conf(enum sys_powerdown mode)
 	}, {
 		.compatible = "samsung,exynos5420-pmu",
 		.data = &exynos5420_pmu_data,
+	}, {
+		.compatible = "samsung,exynos5433-pmu",
 	},
 	{ /*sentinel*/ },
 };
@@ -122,7 +124,7 @@ static int exynos_pmu_probe(struct platform_device *pdev)
 	pmu_context->dev = dev;
 	pmu_context->pmu_data = of_device_get_match_data(dev);
 
-	if (pmu_context->pmu_data->pmu_init)
+	if (pmu_context->pmu_data && pmu_context->pmu_data->pmu_init)
 		pmu_context->pmu_data->pmu_init();
 
 	platform_set_drvdata(pdev, pmu_context);
-- 
1.9.1

[PATCH 1/7] soc: samsung: pmu: Add dummy support for Exynos5433 SoC

[Krzysztof Kozlowski]

On Wed, Jan 25, 2017 at 12:50:25PM +0100, Marek Szyprowski wrote:
> Add compatible for Exynos5433 SoC, so the driver will bind and let other
> drivers to use PMU regmap.
> 
> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
> ---
>  drivers/soc/samsung/exynos-pmu.c | 4 +++-
>  1 file changed, 3 insertions(+), 1 deletion(-)
> 

Makes sense but please also add a check in exynos_sys_powerdown_conf() for
!pmu_data or a comment for that. For current architecture, this will not
happen but you are adding different usage thus forcing reader to find the
dependencies on his own (dependecies are already spread all over for ARMv7).

Best regards,
Krzysztof

> diff --git a/drivers/soc/samsung/exynos-pmu.c b/drivers/soc/samsung/exynos-pmu.c
> index 813df6e7292d..effb8a8a78c6 100644
> --- a/drivers/soc/samsung/exynos-pmu.c
> +++ b/drivers/soc/samsung/exynos-pmu.c
> @@ -90,6 +90,8 @@ void exynos_sys_powerdown_conf(enum sys_powerdown mode)
>  	}, {
>  		.compatible = "samsung,exynos5420-pmu",
>  		.data = &exynos5420_pmu_data,
> +	}, {
> +		.compatible = "samsung,exynos5433-pmu",
>  	},
>  	{ /*sentinel*/ },
>  };
> @@ -122,7 +124,7 @@ static int exynos_pmu_probe(struct platform_device *pdev)
>  	pmu_context->dev = dev;
>  	pmu_context->pmu_data = of_device_get_match_data(dev);
>  
> -	if (pmu_context->pmu_data->pmu_init)
> +	if (pmu_context->pmu_data && pmu_context->pmu_data->pmu_init)
>  		pmu_context->pmu_data->pmu_init();
>  
>  	platform_set_drvdata(pdev, pmu_context);
> -- 
> 1.9.1
> 

[PATCH 2/7] pinctrl: samsung: Ensure that pad retention is disabled on driver init

[Marek Szyprowski]

When pin controller device is a part of power domain, there is no guarantee
that the power domain was not turned off and then on during boot process
before probing of the pin control driver. If it happened, then pin control
driver should ensure that pad retention is turned off during its probe call.

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
---
 drivers/pinctrl/samsung/pinctrl-exynos.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.c b/drivers/pinctrl/samsung/pinctrl-exynos.c
index 63e51b56a22a..fa3802970570 100644
--- a/drivers/pinctrl/samsung/pinctrl-exynos.c
+++ b/drivers/pinctrl/samsung/pinctrl-exynos.c
@@ -777,6 +777,7 @@ static void exynos_retention_disable(struct samsung_pinctrl_drv_data *drvdata)
 {
 	struct samsung_retention_ctrl *ctrl;
 	struct regmap *pmu_regs;
+	int i;
 
 	ctrl = devm_kzalloc(drvdata->dev, sizeof(*ctrl), GFP_KERNEL);
 	if (!ctrl)
@@ -794,6 +795,10 @@ static void exynos_retention_disable(struct samsung_pinctrl_drv_data *drvdata)
 	ctrl->enable = exynos_retention_enable;
 	ctrl->disable = exynos_retention_disable;
 
+	/* Ensure that retention is disabled on driver init */
+	for (i = 0; i < ctrl->nr_regs; i++)
+		regmap_write(pmu_regs, ctrl->regs[i], ctrl->value);
+
 	return ctrl;
 }
 
-- 
1.9.1

[PATCH 2/7] pinctrl: samsung: Ensure that pad retention is disabled on driver init

[Krzysztof Kozlowski]

On Wed, Jan 25, 2017 at 12:50:26PM +0100, Marek Szyprowski wrote:
> When pin controller device is a part of power domain, there is no guarantee
> that the power domain was not turned off and then on during boot process
> before probing of the pin control driver. If it happened, then pin control
> driver should ensure that pad retention is turned off during its probe call.
> 
> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
> ---
>  drivers/pinctrl/samsung/pinctrl-exynos.c | 5 +++++
>  1 file changed, 5 insertions(+)
> 

Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>

Best regards,
Krzysztof

[PATCH 3/7] pinctrl: samsung: Add support for pad retention control for Exynos5433 SoCs

[Marek Szyprowski]

This patch adds support for retention control for Exynos5433 SoCs. Three
groups of pins has been defined for retention control: common shared group
for ALIVE, CPIF, eSE, FINGER, IMEM, NFC, PERIC, TOUCH pin banks and
separate control for FSYS and AUD pin banks, for which PMU retention
registers match whole banks.

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
---
 drivers/pinctrl/samsung/pinctrl-exynos.c    | 58 +++++++++++++++++++++++++++++
 include/linux/soc/samsung/exynos-regs-pmu.h | 19 ++++++++++
 2 files changed, 77 insertions(+)

diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.c b/drivers/pinctrl/samsung/pinctrl-exynos.c
index fa3802970570..f854c92209e1 100644
--- a/drivers/pinctrl/samsung/pinctrl-exynos.c
+++ b/drivers/pinctrl/samsung/pinctrl-exynos.c
@@ -1551,6 +1551,54 @@ static void exynos_retention_disable(struct samsung_pinctrl_drv_data *drvdata)
 	EXYNOS5433_PIN_BANK_EINTG(3, 0x000, "gpj1", 0x00),
 };
 
+/* PMU pin retention groups registers for Exynos5433 (without audio & fsys) */
+static const u32 exynos5433_retention_regs[] = {
+	EXYNOS5433_PAD_RETENTION_TOP_OPTION,
+	EXYNOS5433_PAD_RETENTION_UART_OPTION,
+	EXYNOS5433_PAD_RETENTION_EBIA_OPTION,
+	EXYNOS5433_PAD_RETENTION_EBIB_OPTION,
+	EXYNOS5433_PAD_RETENTION_SPI_OPTION,
+	EXYNOS5433_PAD_RETENTION_MIF_OPTION,
+	EXYNOS5433_PAD_RETENTION_USBXTI_OPTION,
+	EXYNOS5433_PAD_RETENTION_BOOTLDO_OPTION,
+	EXYNOS5433_PAD_RETENTION_UFS_OPTION,
+	EXYNOS5433_PAD_RETENTION_FSYSGENIO_OPTION,
+};
+
+static const struct samsung_retention_data exynos5433_retention_data __initconst = {
+	.regs	 = exynos5433_retention_regs,
+	.nr_regs = ARRAY_SIZE(exynos5433_retention_regs),
+	.value	 = PAD_INITIATE_WAKEUP,
+	.refcnt	 = &exynos_shared_retention_refcnt,
+	.init	 = exynos_retention_init,
+};
+
+/* PMU retention control for audio pins can be tied to audio pin bank */
+static const u32 exynos5433_audio_retention_regs[] = {
+	EXYNOS5433_PAD_RETENTION_AUD_OPTION,
+};
+
+static const struct samsung_retention_data exynos5433_audio_retention_data __initconst = {
+	.regs	 = exynos5433_audio_retention_regs,
+	.nr_regs = ARRAY_SIZE(exynos5433_audio_retention_regs),
+	.value	 = PAD_INITIATE_WAKEUP,
+	.init	 = exynos_retention_init,
+};
+
+/* PMU retention control for mmc pins can be tied to fsys pin bank */
+static const u32 exynos5433_fsys_retention_regs[] = {
+	EXYNOS5433_PAD_RETENTION_MMC0_OPTION,
+	EXYNOS5433_PAD_RETENTION_MMC1_OPTION,
+	EXYNOS5433_PAD_RETENTION_MMC2_OPTION,
+};
+
+static const struct samsung_retention_data exynos5433_fsys_retention_data __initconst = {
+	.regs	 = exynos5433_fsys_retention_regs,
+	.nr_regs = ARRAY_SIZE(exynos5433_fsys_retention_regs),
+	.value	 = PAD_INITIATE_WAKEUP,
+	.init	 = exynos_retention_init,
+};
+
 /*
  * Samsung pinctrl driver data for Exynos5433 SoC. Exynos5433 SoC includes
  * ten gpio/pin-mux/pinconfig controllers.
@@ -1564,6 +1612,7 @@ static void exynos_retention_disable(struct samsung_pinctrl_drv_data *drvdata)
 		.suspend	= exynos_pinctrl_suspend,
 		.resume		= exynos_pinctrl_resume,
 		.nr_ext_resources = 1,
+		.retention_data	= &exynos5433_retention_data,
 	}, {
 		/* pin-controller instance 1 data */
 		.pin_banks	= exynos5433_pin_banks1,
@@ -1571,6 +1620,7 @@ static void exynos_retention_disable(struct samsung_pinctrl_drv_data *drvdata)
 		.eint_gpio_init = exynos_eint_gpio_init,
 		.suspend	= exynos_pinctrl_suspend,
 		.resume		= exynos_pinctrl_resume,
+		.retention_data	= &exynos5433_audio_retention_data,
 	}, {
 		/* pin-controller instance 2 data */
 		.pin_banks	= exynos5433_pin_banks2,
@@ -1578,6 +1628,7 @@ static void exynos_retention_disable(struct samsung_pinctrl_drv_data *drvdata)
 		.eint_gpio_init = exynos_eint_gpio_init,
 		.suspend	= exynos_pinctrl_suspend,
 		.resume		= exynos_pinctrl_resume,
+		.retention_data	= &exynos5433_retention_data,
 	}, {
 		/* pin-controller instance 3 data */
 		.pin_banks	= exynos5433_pin_banks3,
@@ -1585,6 +1636,7 @@ static void exynos_retention_disable(struct samsung_pinctrl_drv_data *drvdata)
 		.eint_gpio_init = exynos_eint_gpio_init,
 		.suspend	= exynos_pinctrl_suspend,
 		.resume		= exynos_pinctrl_resume,
+		.retention_data	= &exynos5433_retention_data,
 	}, {
 		/* pin-controller instance 4 data */
 		.pin_banks	= exynos5433_pin_banks4,
@@ -1592,6 +1644,7 @@ static void exynos_retention_disable(struct samsung_pinctrl_drv_data *drvdata)
 		.eint_gpio_init = exynos_eint_gpio_init,
 		.suspend	= exynos_pinctrl_suspend,
 		.resume		= exynos_pinctrl_resume,
+		.retention_data	= &exynos5433_retention_data,
 	}, {
 		/* pin-controller instance 5 data */
 		.pin_banks	= exynos5433_pin_banks5,
@@ -1599,6 +1652,7 @@ static void exynos_retention_disable(struct samsung_pinctrl_drv_data *drvdata)
 		.eint_gpio_init = exynos_eint_gpio_init,
 		.suspend	= exynos_pinctrl_suspend,
 		.resume		= exynos_pinctrl_resume,
+		.retention_data	= &exynos5433_fsys_retention_data,
 	}, {
 		/* pin-controller instance 6 data */
 		.pin_banks	= exynos5433_pin_banks6,
@@ -1606,6 +1660,7 @@ static void exynos_retention_disable(struct samsung_pinctrl_drv_data *drvdata)
 		.eint_gpio_init = exynos_eint_gpio_init,
 		.suspend	= exynos_pinctrl_suspend,
 		.resume		= exynos_pinctrl_resume,
+		.retention_data	= &exynos5433_retention_data,
 	}, {
 		/* pin-controller instance 7 data */
 		.pin_banks	= exynos5433_pin_banks7,
@@ -1613,6 +1668,7 @@ static void exynos_retention_disable(struct samsung_pinctrl_drv_data *drvdata)
 		.eint_gpio_init = exynos_eint_gpio_init,
 		.suspend	= exynos_pinctrl_suspend,
 		.resume		= exynos_pinctrl_resume,
+		.retention_data	= &exynos5433_retention_data,
 	}, {
 		/* pin-controller instance 8 data */
 		.pin_banks	= exynos5433_pin_banks8,
@@ -1620,6 +1676,7 @@ static void exynos_retention_disable(struct samsung_pinctrl_drv_data *drvdata)
 		.eint_gpio_init = exynos_eint_gpio_init,
 		.suspend	= exynos_pinctrl_suspend,
 		.resume		= exynos_pinctrl_resume,
+		.retention_data	= &exynos5433_retention_data,
 	}, {
 		/* pin-controller instance 9 data */
 		.pin_banks	= exynos5433_pin_banks9,
@@ -1627,6 +1684,7 @@ static void exynos_retention_disable(struct samsung_pinctrl_drv_data *drvdata)
 		.eint_gpio_init = exynos_eint_gpio_init,
 		.suspend	= exynos_pinctrl_suspend,
 		.resume		= exynos_pinctrl_resume,
+		.retention_data	= &exynos5433_retention_data,
 	},
 };
 
diff --git a/include/linux/soc/samsung/exynos-regs-pmu.h b/include/linux/soc/samsung/exynos-regs-pmu.h
index d30186e2b609..6a160e2ef4f0 100644
--- a/include/linux/soc/samsung/exynos-regs-pmu.h
+++ b/include/linux/soc/samsung/exynos-regs-pmu.h
@@ -690,4 +690,23 @@
 					 | EXYNOS5420_KFC_USE_STANDBY_WFI2  \
 					 | EXYNOS5420_KFC_USE_STANDBY_WFI3)
 
+/* For EXYNOS5433 */
+#define EXYNOS5433_PAD_RETENTION_AUD_OPTION			(0x3028)
+#define EXYNOS5433_PAD_RETENTION_MMC2_OPTION			(0x30C8)
+#define EXYNOS5433_PAD_RETENTION_TOP_OPTION			(0x3108)
+#define EXYNOS5433_PAD_RETENTION_UART_OPTION			(0x3128)
+#define EXYNOS5433_PAD_RETENTION_MMC0_OPTION			(0x3148)
+#define EXYNOS5433_PAD_RETENTION_MMC1_OPTION			(0x3168)
+#define EXYNOS5433_PAD_RETENTION_EBIA_OPTION			(0x3188)
+#define EXYNOS5433_PAD_RETENTION_EBIB_OPTION			(0x31A8)
+#define EXYNOS5433_PAD_RETENTION_SPI_OPTION			(0x31C8)
+#define EXYNOS5433_PAD_RETENTION_MIF_OPTION			(0x31E8)
+#define EXYNOS5433_PAD_RETENTION_USBXTI_OPTION			(0x3228)
+#define EXYNOS5433_PAD_RETENTION_BOOTLDO_OPTION			(0x3248)
+#define EXYNOS5433_PAD_RETENTION_UFS_OPTION			(0x3268)
+#define EXYNOS5433_PAD_RETENTION_FSYSGENIO_OPTION		(0x32A8)
+
+/* EXYNOS5433_PAD_RETENTION_*_OPTION */
+#define PAD_INITIATE_WAKEUP					(0x1 << 28)
+
 #endif /* __LINUX_SOC_EXYNOS_REGS_PMU_H */
-- 
1.9.1

[PATCH 3/7] pinctrl: samsung: Add support for pad retention control for Exynos5433 SoCs

[Krzysztof Kozlowski]

On Wed, Jan 25, 2017 at 12:50:27PM +0100, Marek Szyprowski wrote:
> This patch adds support for retention control for Exynos5433 SoCs. Three
> groups of pins has been defined for retention control: common shared group
> for ALIVE, CPIF, eSE, FINGER, IMEM, NFC, PERIC, TOUCH pin banks and
> separate control for FSYS and AUD pin banks, for which PMU retention
> registers match whole banks.
> 
> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
> ---
>  drivers/pinctrl/samsung/pinctrl-exynos.c    | 58 +++++++++++++++++++++++++++++
>  include/linux/soc/samsung/exynos-regs-pmu.h | 19 ++++++++++
>  2 files changed, 77 insertions(+)
> 
> diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.c b/drivers/pinctrl/samsung/pinctrl-exynos.c
> index fa3802970570..f854c92209e1 100644
> --- a/drivers/pinctrl/samsung/pinctrl-exynos.c
> +++ b/drivers/pinctrl/samsung/pinctrl-exynos.c
> @@ -1551,6 +1551,54 @@ static void exynos_retention_disable(struct samsung_pinctrl_drv_data *drvdata)
>  	EXYNOS5433_PIN_BANK_EINTG(3, 0x000, "gpj1", 0x00),
>  };
>  
> +/* PMU pin retention groups registers for Exynos5433 (without audio & fsys) */
> +static const u32 exynos5433_retention_regs[] = {
> +	EXYNOS5433_PAD_RETENTION_TOP_OPTION,
> +	EXYNOS5433_PAD_RETENTION_UART_OPTION,
> +	EXYNOS5433_PAD_RETENTION_EBIA_OPTION,
> +	EXYNOS5433_PAD_RETENTION_EBIB_OPTION,
> +	EXYNOS5433_PAD_RETENTION_SPI_OPTION,
> +	EXYNOS5433_PAD_RETENTION_MIF_OPTION,
> +	EXYNOS5433_PAD_RETENTION_USBXTI_OPTION,
> +	EXYNOS5433_PAD_RETENTION_BOOTLDO_OPTION,
> +	EXYNOS5433_PAD_RETENTION_UFS_OPTION,
> +	EXYNOS5433_PAD_RETENTION_FSYSGENIO_OPTION,
> +};
> +
> +static const struct samsung_retention_data exynos5433_retention_data __initconst = {
> +	.regs	 = exynos5433_retention_regs,
> +	.nr_regs = ARRAY_SIZE(exynos5433_retention_regs),
> +	.value	 = PAD_INITIATE_WAKEUP,
> +	.refcnt	 = &exynos_shared_retention_refcnt,
> +	.init	 = exynos_retention_init,
> +};
> +
> +/* PMU retention control for audio pins can be tied to audio pin bank */
> +static const u32 exynos5433_audio_retention_regs[] = {
> +	EXYNOS5433_PAD_RETENTION_AUD_OPTION,
> +};
> +
> +static const struct samsung_retention_data exynos5433_audio_retention_data __initconst = {
> +	.regs	 = exynos5433_audio_retention_regs,
> +	.nr_regs = ARRAY_SIZE(exynos5433_audio_retention_regs),
> +	.value	 = PAD_INITIATE_WAKEUP,
> +	.init	 = exynos_retention_init,
> +};
> +
> +/* PMU retention control for mmc pins can be tied to fsys pin bank */
> +static const u32 exynos5433_fsys_retention_regs[] = {
> +	EXYNOS5433_PAD_RETENTION_MMC0_OPTION,
> +	EXYNOS5433_PAD_RETENTION_MMC1_OPTION,
> +	EXYNOS5433_PAD_RETENTION_MMC2_OPTION,
> +};
> +
> +static const struct samsung_retention_data exynos5433_fsys_retention_data __initconst = {
> +	.regs	 = exynos5433_fsys_retention_regs,
> +	.nr_regs = ARRAY_SIZE(exynos5433_fsys_retention_regs),
> +	.value	 = PAD_INITIATE_WAKEUP,
> +	.init	 = exynos_retention_init,
> +};
> +
>  /*
>   * Samsung pinctrl driver data for Exynos5433 SoC. Exynos5433 SoC includes
>   * ten gpio/pin-mux/pinconfig controllers.
> @@ -1564,6 +1612,7 @@ static void exynos_retention_disable(struct samsung_pinctrl_drv_data *drvdata)
>  		.suspend	= exynos_pinctrl_suspend,
>  		.resume		= exynos_pinctrl_resume,
>  		.nr_ext_resources = 1,
> +		.retention_data	= &exynos5433_retention_data,
>  	}, {
>  		/* pin-controller instance 1 data */
>  		.pin_banks	= exynos5433_pin_banks1,
> @@ -1571,6 +1620,7 @@ static void exynos_retention_disable(struct samsung_pinctrl_drv_data *drvdata)
>  		.eint_gpio_init = exynos_eint_gpio_init,
>  		.suspend	= exynos_pinctrl_suspend,
>  		.resume		= exynos_pinctrl_resume,
> +		.retention_data	= &exynos5433_audio_retention_data,
>  	}, {
>  		/* pin-controller instance 2 data */
>  		.pin_banks	= exynos5433_pin_banks2,
> @@ -1578,6 +1628,7 @@ static void exynos_retention_disable(struct samsung_pinctrl_drv_data *drvdata)
>  		.eint_gpio_init = exynos_eint_gpio_init,
>  		.suspend	= exynos_pinctrl_suspend,
>  		.resume		= exynos_pinctrl_resume,
> +		.retention_data	= &exynos5433_retention_data,
>  	}, {
>  		/* pin-controller instance 3 data */
>  		.pin_banks	= exynos5433_pin_banks3,
> @@ -1585,6 +1636,7 @@ static void exynos_retention_disable(struct samsung_pinctrl_drv_data *drvdata)
>  		.eint_gpio_init = exynos_eint_gpio_init,
>  		.suspend	= exynos_pinctrl_suspend,
>  		.resume		= exynos_pinctrl_resume,
> +		.retention_data	= &exynos5433_retention_data,
>  	}, {
>  		/* pin-controller instance 4 data */
>  		.pin_banks	= exynos5433_pin_banks4,
> @@ -1592,6 +1644,7 @@ static void exynos_retention_disable(struct samsung_pinctrl_drv_data *drvdata)
>  		.eint_gpio_init = exynos_eint_gpio_init,
>  		.suspend	= exynos_pinctrl_suspend,
>  		.resume		= exynos_pinctrl_resume,
> +		.retention_data	= &exynos5433_retention_data,
>  	}, {
>  		/* pin-controller instance 5 data */
>  		.pin_banks	= exynos5433_pin_banks5,
> @@ -1599,6 +1652,7 @@ static void exynos_retention_disable(struct samsung_pinctrl_drv_data *drvdata)
>  		.eint_gpio_init = exynos_eint_gpio_init,
>  		.suspend	= exynos_pinctrl_suspend,
>  		.resume		= exynos_pinctrl_resume,
> +		.retention_data	= &exynos5433_fsys_retention_data,
>  	}, {
>  		/* pin-controller instance 6 data */
>  		.pin_banks	= exynos5433_pin_banks6,
> @@ -1606,6 +1660,7 @@ static void exynos_retention_disable(struct samsung_pinctrl_drv_data *drvdata)
>  		.eint_gpio_init = exynos_eint_gpio_init,
>  		.suspend	= exynos_pinctrl_suspend,
>  		.resume		= exynos_pinctrl_resume,
> +		.retention_data	= &exynos5433_retention_data,
>  	}, {
>  		/* pin-controller instance 7 data */
>  		.pin_banks	= exynos5433_pin_banks7,
> @@ -1613,6 +1668,7 @@ static void exynos_retention_disable(struct samsung_pinctrl_drv_data *drvdata)
>  		.eint_gpio_init = exynos_eint_gpio_init,
>  		.suspend	= exynos_pinctrl_suspend,
>  		.resume		= exynos_pinctrl_resume,
> +		.retention_data	= &exynos5433_retention_data,
>  	}, {
>  		/* pin-controller instance 8 data */
>  		.pin_banks	= exynos5433_pin_banks8,
> @@ -1620,6 +1676,7 @@ static void exynos_retention_disable(struct samsung_pinctrl_drv_data *drvdata)
>  		.eint_gpio_init = exynos_eint_gpio_init,
>  		.suspend	= exynos_pinctrl_suspend,
>  		.resume		= exynos_pinctrl_resume,
> +		.retention_data	= &exynos5433_retention_data,
>  	}, {
>  		/* pin-controller instance 9 data */
>  		.pin_banks	= exynos5433_pin_banks9,
> @@ -1627,6 +1684,7 @@ static void exynos_retention_disable(struct samsung_pinctrl_drv_data *drvdata)
>  		.eint_gpio_init = exynos_eint_gpio_init,
>  		.suspend	= exynos_pinctrl_suspend,
>  		.resume		= exynos_pinctrl_resume,
> +		.retention_data	= &exynos5433_retention_data,
>  	},
>  };
>  
> diff --git a/include/linux/soc/samsung/exynos-regs-pmu.h b/include/linux/soc/samsung/exynos-regs-pmu.h
> index d30186e2b609..6a160e2ef4f0 100644
> --- a/include/linux/soc/samsung/exynos-regs-pmu.h
> +++ b/include/linux/soc/samsung/exynos-regs-pmu.h
> @@ -690,4 +690,23 @@
>  					 | EXYNOS5420_KFC_USE_STANDBY_WFI2  \
>  					 | EXYNOS5420_KFC_USE_STANDBY_WFI3)
>  
> +/* For EXYNOS5433 */
> +#define EXYNOS5433_PAD_RETENTION_AUD_OPTION			(0x3028)
> +#define EXYNOS5433_PAD_RETENTION_MMC2_OPTION			(0x30C8)
> +#define EXYNOS5433_PAD_RETENTION_TOP_OPTION			(0x3108)
> +#define EXYNOS5433_PAD_RETENTION_UART_OPTION			(0x3128)
> +#define EXYNOS5433_PAD_RETENTION_MMC0_OPTION			(0x3148)
> +#define EXYNOS5433_PAD_RETENTION_MMC1_OPTION			(0x3168)
> +#define EXYNOS5433_PAD_RETENTION_EBIA_OPTION			(0x3188)
> +#define EXYNOS5433_PAD_RETENTION_EBIB_OPTION			(0x31A8)
> +#define EXYNOS5433_PAD_RETENTION_SPI_OPTION			(0x31C8)
> +#define EXYNOS5433_PAD_RETENTION_MIF_OPTION			(0x31E8)
> +#define EXYNOS5433_PAD_RETENTION_USBXTI_OPTION			(0x3228)
> +#define EXYNOS5433_PAD_RETENTION_BOOTLDO_OPTION			(0x3248)
> +#define EXYNOS5433_PAD_RETENTION_UFS_OPTION			(0x3268)
> +#define EXYNOS5433_PAD_RETENTION_FSYSGENIO_OPTION		(0x32A8)
> +
> +/* EXYNOS5433_PAD_RETENTION_*_OPTION */
> +#define PAD_INITIATE_WAKEUP					(0x1 << 28)

Use existing EXYNOS_WAKEUP_FROM_LOWPWR unless there is a reason not to
use it?

Best regards,
Krzysztof

[PATCH 4/7] arm64: dts: exynos: Add clocks to Exynos5433 LPASS module

[Marek Szyprowski]

Exynos5433 LPASS module requires some clocks for proper operation with
power domain.

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
---
 arch/arm64/boot/dts/exynos/exynos5433.dtsi | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
index 57c7bbeb65a7..16072c1c3ed3 100644
--- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
@@ -1494,6 +1494,8 @@
 		audio-subsystem at 11400000 {
 			compatible = "samsung,exynos5433-lpass";
 			reg = <0x11400000 0x100>, <0x11500000 0x08>;
+			clocks = <&cmu_aud CLK_PCLK_SFR0_CTRL>;
+			clock-names = "sfr0_ctrl";
 			samsung,pmu-syscon = <&pmu_system_controller>;
 			#address-cells = <1>;
 			#size-cells = <1>;
-- 
1.9.1

[PATCH 4/7] arm64: dts: exynos: Add clocks to Exynos5433 LPASS module

[Krzysztof Kozlowski]

On Wed, Jan 25, 2017 at 12:50:28PM +0100, Marek Szyprowski wrote:
> Exynos5433 LPASS module requires some clocks for proper operation with
> power domain.
> 
> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
> ---
>  arch/arm64/boot/dts/exynos/exynos5433.dtsi | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
> index 57c7bbeb65a7..16072c1c3ed3 100644
> --- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi
> +++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
> @@ -1494,6 +1494,8 @@
>  		audio-subsystem at 11400000 {
>  			compatible = "samsung,exynos5433-lpass";
>  			reg = <0x11400000 0x100>, <0x11500000 0x08>;
> +			clocks = <&cmu_aud CLK_PCLK_SFR0_CTRL>;
> +			clock-names = "sfr0_ctrl";

You wrote that 6/7 depends on this. I prefer not to take DTS changes if
the corresponding user (driver) is still under discussion because the
bindings might change. I'll take it when bindings got acked or accepted.

BTW, the 6/7 is a quite reasonable ABI break, but for the sake of
documentation - why you did not continue with the patch for marking
bidings as experimental/under-development?

Best regards,
Krzysztof

>  			samsung,pmu-syscon = <&pmu_system_controller>;
>  			#address-cells = <1>;
>  			#size-cells = <1>;
> -- 
> 1.9.1
> 

[PATCH 4/7] arm64: dts: exynos: Add clocks to Exynos5433 LPASS module

[Marek Szyprowski]

Hi Krzysztof,


On 2017-01-25 20:50, Krzysztof Kozlowski wrote:
> On Wed, Jan 25, 2017 at 12:50:28PM +0100, Marek Szyprowski wrote:
>> Exynos5433 LPASS module requires some clocks for proper operation with
>> power domain.
>>
>> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
>> ---
>>   arch/arm64/boot/dts/exynos/exynos5433.dtsi | 2 ++
>>   1 file changed, 2 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
>> index 57c7bbeb65a7..16072c1c3ed3 100644
>> --- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi
>> +++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
>> @@ -1494,6 +1494,8 @@
>>   		audio-subsystem at 11400000 {
>>   			compatible = "samsung,exynos5433-lpass";
>>   			reg = <0x11400000 0x100>, <0x11500000 0x08>;
>> +			clocks = <&cmu_aud CLK_PCLK_SFR0_CTRL>;
>> +			clock-names = "sfr0_ctrl";
> You wrote that 6/7 depends on this. I prefer not to take DTS changes if
> the corresponding user (driver) is still under discussion because the
> bindings might change. I'll take it when bindings got acked or accepted.

Well, audio support in 4.9 is still not functional due to missing other
patches to ALSA SoC, so nothing will break as for now if we manage to get
this into v4.10.

> BTW, the 6/7 is a quite reasonable ABI break, but for the sake of
> documentation - why you did not continue with the patch for marking
> bidings as experimental/under-development?

Because I had no time to list all breaks, what was requested by Rob.


Best regards
-- 
Marek Szyprowski, PhD
Samsung R&D Institute Poland

[PATCH 4/7] arm64: dts: exynos: Add clocks to Exynos5433 LPASS module

[Krzysztof Kozlowski]

On Thu, Jan 26, 2017 at 9:18 AM, Marek Szyprowski
<m.szyprowski@samsung.com> wrote:
> Hi Krzysztof,
>
>
> On 2017-01-25 20:50, Krzysztof Kozlowski wrote:
>>
>> On Wed, Jan 25, 2017 at 12:50:28PM +0100, Marek Szyprowski wrote:
>>>
>>> Exynos5433 LPASS module requires some clocks for proper operation with
>>> power domain.
>>>
>>> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
>>> ---
>>>   arch/arm64/boot/dts/exynos/exynos5433.dtsi | 2 ++
>>>   1 file changed, 2 insertions(+)
>>>
>>> diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi
>>> b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
>>> index 57c7bbeb65a7..16072c1c3ed3 100644
>>> --- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi
>>> +++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
>>> @@ -1494,6 +1494,8 @@
>>>                 audio-subsystem at 11400000 {
>>>                         compatible = "samsung,exynos5433-lpass";
>>>                         reg = <0x11400000 0x100>, <0x11500000 0x08>;
>>> +                       clocks = <&cmu_aud CLK_PCLK_SFR0_CTRL>;
>>> +                       clock-names = "sfr0_ctrl";
>>
>> You wrote that 6/7 depends on this. I prefer not to take DTS changes if
>> the corresponding user (driver) is still under discussion because the
>> bindings might change. I'll take it when bindings got acked or accepted.
>
>
> Well, audio support in 4.9 is still not functional due to missing other
> patches to ALSA SoC, so nothing will break as for now if we manage to get
> this into v4.10.

Get this into v4.10? So this needs some additional explanation in the
commit message why this is a fix. Probably one more sentence would be
enough. Or did you mean v4.11?

Best regards,
Krzysztof

[PATCH 4/7] arm64: dts: exynos: Add clocks to Exynos5433 LPASS module

[Marek Szyprowski]

Hi Krzysztof,

On 2017-01-26 09:40, Krzysztof Kozlowski wrote:
> On Thu, Jan 26, 2017 at 9:18 AM, Marek Szyprowski
> <m.szyprowski@samsung.com> wrote:
>> On 2017-01-25 20:50, Krzysztof Kozlowski wrote:
>>> On Wed, Jan 25, 2017 at 12:50:28PM +0100, Marek Szyprowski wrote:
>>>> Exynos5433 LPASS module requires some clocks for proper operation with
>>>> power domain.
>>>>
>>>> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
>>>> ---
>>>>    arch/arm64/boot/dts/exynos/exynos5433.dtsi | 2 ++
>>>>    1 file changed, 2 insertions(+)
>>>>
>>>> diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi
>>>> b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
>>>> index 57c7bbeb65a7..16072c1c3ed3 100644
>>>> --- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi
>>>> +++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
>>>> @@ -1494,6 +1494,8 @@
>>>>                  audio-subsystem at 11400000 {
>>>>                          compatible = "samsung,exynos5433-lpass";
>>>>                          reg = <0x11400000 0x100>, <0x11500000 0x08>;
>>>> +                       clocks = <&cmu_aud CLK_PCLK_SFR0_CTRL>;
>>>> +                       clock-names = "sfr0_ctrl";
>>> You wrote that 6/7 depends on this. I prefer not to take DTS changes if
>>> the corresponding user (driver) is still under discussion because the
>>> bindings might change. I'll take it when bindings got acked or accepted.
>>
>> Well, audio support in 4.9 is still not functional due to missing other
>> patches to ALSA SoC, so nothing will break as for now if we manage to get
>> this into v4.10.
> Get this into v4.10? So this needs some additional explanation in the
> commit message why this is a fix. Probably one more sentence would be
> enough. Or did you mean v4.11?

Yes, I meant v4.11.

Best regards
-- 
Marek Szyprowski, PhD
Samsung R&D Institute Poland

[PATCH 5/7] mfd: exynos-lpass: Remove pad retention control

[Marek Szyprowski]

Pad retention should be controlled from pin control driver, so remove it
from Exynos LPASS driver. After this change, no more access to PMU regmap
is needed, so remove also the code for handling PMU regmap.

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
---
 .../bindings/mfd/samsung,exynos5433-lpass.txt           |  2 --
 drivers/mfd/exynos-lpass.c                              | 17 -----------------
 include/linux/mfd/syscon/exynos5-pmu.h                  |  3 ---
 3 files changed, 22 deletions(-)

diff --git a/Documentation/devicetree/bindings/mfd/samsung,exynos5433-lpass.txt b/Documentation/devicetree/bindings/mfd/samsung,exynos5433-lpass.txt
index c110e118b79f..a8deaee82c44 100644
--- a/Documentation/devicetree/bindings/mfd/samsung,exynos5433-lpass.txt
+++ b/Documentation/devicetree/bindings/mfd/samsung,exynos5433-lpass.txt
@@ -5,7 +5,6 @@ Required properties:
  - compatible		: "samsung,exynos5433-lpass"
  - reg			: should contain the LPASS top SFR region location
 			  and size
- - samsung,pmu-syscon	: the phandle to the Power Management Unit node
  - #address-cells	: should be 1
  - #size-cells		: should be 1
  - ranges		: must be present
@@ -25,7 +24,6 @@ Example:
 audio-subsystem {
 	compatible = "samsung,exynos5433-lpass";
 	reg = <0x11400000 0x100>, <0x11500000 0x08>;
-	samsung,pmu-syscon = <&pmu_system_controller>;
 	#address-cells = <1>;
 	#size-cells = <1>;
 	ranges;
diff --git a/drivers/mfd/exynos-lpass.c b/drivers/mfd/exynos-lpass.c
index 2e064fb8826f..17915daa2e80 100644
--- a/drivers/mfd/exynos-lpass.c
+++ b/drivers/mfd/exynos-lpass.c
@@ -18,7 +18,6 @@
 #include <linux/io.h>
 #include <linux/module.h>
 #include <linux/mfd/syscon.h>
-#include <linux/mfd/syscon/exynos5-pmu.h>
 #include <linux/of.h>
 #include <linux/of_platform.h>
 #include <linux/platform_device.h>
@@ -51,8 +50,6 @@
 #define  LPASS_INTR_SFR			BIT(0)
 
 struct exynos_lpass {
-	/* pointer to the Power Management Unit regmap */
-	struct regmap *pmu;
 	/* pointer to the LPASS TOP regmap */
 	struct regmap *top;
 };
@@ -81,10 +78,6 @@ static void exynos_lpass_enable(struct exynos_lpass *lpass)
 	regmap_write(lpass->top, SFR_LPASS_INTR_CPU_MASK,
 		     LPASS_INTR_SFR | LPASS_INTR_DMA | LPASS_INTR_I2S);
 
-	/* Activate related PADs from retention state */
-	regmap_write(lpass->pmu, EXYNOS5433_PAD_RETENTION_AUD_OPTION,
-		     EXYNOS5433_PAD_INITIATE_WAKEUP_FROM_LOWPWR);
-
 	exynos_lpass_core_sw_reset(lpass, LPASS_I2S_SW_RESET);
 	exynos_lpass_core_sw_reset(lpass, LPASS_DMA_SW_RESET);
 	exynos_lpass_core_sw_reset(lpass, LPASS_MEM_SW_RESET);
@@ -95,9 +88,6 @@ static void exynos_lpass_disable(struct exynos_lpass *lpass)
 	/* Mask any unmasked IP interrupt sources */
 	regmap_write(lpass->top, SFR_LPASS_INTR_CPU_MASK, 0);
 	regmap_write(lpass->top, SFR_LPASS_INTR_CA5_MASK, 0);
-
-	/* Deactivate related PADs from retention state */
-	regmap_write(lpass->pmu, EXYNOS5433_PAD_RETENTION_AUD_OPTION, 0);
 }
 
 static const struct regmap_config exynos_lpass_reg_conf = {
@@ -131,13 +121,6 @@ static int exynos_lpass_probe(struct platform_device *pdev)
 		return PTR_ERR(lpass->top);
 	}
 
-	lpass->pmu = syscon_regmap_lookup_by_phandle(dev->of_node,
-						"samsung,pmu-syscon");
-	if (IS_ERR(lpass->pmu)) {
-		dev_err(dev, "Failed to lookup PMU regmap\n");
-		return PTR_ERR(lpass->pmu);
-	}
-
 	platform_set_drvdata(pdev, lpass);
 	exynos_lpass_enable(lpass);
 
diff --git a/include/linux/mfd/syscon/exynos5-pmu.h b/include/linux/mfd/syscon/exynos5-pmu.h
index c28ff21ca4d2..0622ae86f9db 100644
--- a/include/linux/mfd/syscon/exynos5-pmu.h
+++ b/include/linux/mfd/syscon/exynos5-pmu.h
@@ -46,7 +46,4 @@
 #define EXYNOS5_MIPI_PHY_S_RESETN		BIT(1)
 #define EXYNOS5_MIPI_PHY_M_RESETN		BIT(2)
 
-#define EXYNOS5433_PAD_RETENTION_AUD_OPTION		(0x3028)
-#define EXYNOS5433_PAD_INITIATE_WAKEUP_FROM_LOWPWR	BIT(28)
-
 #endif /* _LINUX_MFD_SYSCON_PMU_EXYNOS5_H_ */
-- 
1.9.1

[PATCH 5/7] mfd: exynos-lpass: Remove pad retention control

[Krzysztof Kozlowski]

On Wed, Jan 25, 2017 at 12:50:29PM +0100, Marek Szyprowski wrote:
> Pad retention should be controlled from pin control driver, so remove it
> from Exynos LPASS driver. After this change, no more access to PMU regmap
> is needed, so remove also the code for handling PMU regmap.
> 
> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
> ---
>  .../bindings/mfd/samsung,exynos5433-lpass.txt           |  2 --
>  drivers/mfd/exynos-lpass.c                              | 17 -----------------
>  include/linux/mfd/syscon/exynos5-pmu.h                  |  3 ---
>  3 files changed, 22 deletions(-)
> 

Acked-by: Krzysztof Kozlowski <krzk@kernel.org>

Best regards,
Krzysztof

[PATCH 5/7] mfd: exynos-lpass: Remove pad retention control

[Sylwester Nawrocki]

On 01/25/2017 12:50 PM, Marek Szyprowski wrote:
> Pad retention should be controlled from pin control driver, so remove it
> from Exynos LPASS driver. After this change, no more access to PMU regmap
> is needed, so remove also the code for handling PMU regmap.
> 
> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>

Acked-by: Sylwester Nawrocki <s.nawrocki@samsung.com>

[PATCH 6/7] mfd: exynos-lpass: Add support for clocks

[Marek Szyprowski]

Exynos LPASS requires some clocks to be enabled to make any access to its
registers. This patch adds code for handling such clocks. For current set
of registers it is enough to keep sfr0_ctrl clock enabled. Till now it
worked only because those clocks were enabled by bootloader and driver
probe() happened before they were disabled by clock core because of lack
of users. Handling those clocks is also needed to make it possible to
enable support for audio power domain.

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
---
 .../devicetree/bindings/mfd/samsung,exynos5433-lpass.txt       |  6 ++++++
 drivers/mfd/exynos-lpass.c                                     | 10 ++++++++++
 2 files changed, 16 insertions(+)

diff --git a/Documentation/devicetree/bindings/mfd/samsung,exynos5433-lpass.txt b/Documentation/devicetree/bindings/mfd/samsung,exynos5433-lpass.txt
index a8deaee82c44..df664018c148 100644
--- a/Documentation/devicetree/bindings/mfd/samsung,exynos5433-lpass.txt
+++ b/Documentation/devicetree/bindings/mfd/samsung,exynos5433-lpass.txt
@@ -5,6 +5,10 @@ Required properties:
  - compatible		: "samsung,exynos5433-lpass"
  - reg			: should contain the LPASS top SFR region location
 			  and size
+ - clock-names		: should contain following required clocks: "sfr0_ctrl"
+ - clocks		: should contain clock specifiers of all clocks, which
+			  input names have been specified in clock-names
+			  property, in same order.
  - #address-cells	: should be 1
  - #size-cells		: should be 1
  - ranges		: must be present
@@ -24,6 +28,8 @@ Example:
 audio-subsystem {
 	compatible = "samsung,exynos5433-lpass";
 	reg = <0x11400000 0x100>, <0x11500000 0x08>;
+	clocks = <&cmu_aud CLK_PCLK_SFR0_CTRL>;
+	clock-names = "sfr0_ctrl";
 	#address-cells = <1>;
 	#size-cells = <1>;
 	ranges;
diff --git a/drivers/mfd/exynos-lpass.c b/drivers/mfd/exynos-lpass.c
index 17915daa2e80..44d8ea1a978b 100644
--- a/drivers/mfd/exynos-lpass.c
+++ b/drivers/mfd/exynos-lpass.c
@@ -14,6 +14,7 @@
  * only version 2 as published by the Free Software Foundation.
  */
 
+#include <linux/clk.h>
 #include <linux/delay.h>
 #include <linux/io.h>
 #include <linux/module.h>
@@ -52,6 +53,7 @@
 struct exynos_lpass {
 	/* pointer to the LPASS TOP regmap */
 	struct regmap *top;
+	struct clk *sfr0_clk;
 };
 
 static void exynos_lpass_core_sw_reset(struct exynos_lpass *lpass, int mask)
@@ -71,6 +73,8 @@ static void exynos_lpass_core_sw_reset(struct exynos_lpass *lpass, int mask)
 
 static void exynos_lpass_enable(struct exynos_lpass *lpass)
 {
+	clk_prepare_enable(lpass->sfr0_clk);
+
 	/* Unmask SFR, DMA and I2S interrupt */
 	regmap_write(lpass->top, SFR_LPASS_INTR_CA5_MASK,
 		     LPASS_INTR_SFR | LPASS_INTR_DMA | LPASS_INTR_I2S);
@@ -88,6 +92,8 @@ static void exynos_lpass_disable(struct exynos_lpass *lpass)
 	/* Mask any unmasked IP interrupt sources */
 	regmap_write(lpass->top, SFR_LPASS_INTR_CPU_MASK, 0);
 	regmap_write(lpass->top, SFR_LPASS_INTR_CA5_MASK, 0);
+
+	clk_disable_unprepare(lpass->sfr0_clk);
 }
 
 static const struct regmap_config exynos_lpass_reg_conf = {
@@ -114,6 +120,10 @@ static int exynos_lpass_probe(struct platform_device *pdev)
 	if (IS_ERR(base_top))
 		return PTR_ERR(base_top);
 
+	lpass->sfr0_clk = clk_get(dev, "sfr0_ctrl");
+	if (IS_ERR(lpass->sfr0_clk))
+		return PTR_ERR(lpass->sfr0_clk);
+
 	lpass->top = regmap_init_mmio(dev, base_top,
 					&exynos_lpass_reg_conf);
 	if (IS_ERR(lpass->top)) {
-- 
1.9.1

[PATCH 6/7] mfd: exynos-lpass: Add support for clocks

[Krzysztof Kozlowski]

On Wed, Jan 25, 2017 at 12:50:30PM +0100, Marek Szyprowski wrote:
> Exynos LPASS requires some clocks to be enabled to make any access to its
> registers. This patch adds code for handling such clocks. For current set
> of registers it is enough to keep sfr0_ctrl clock enabled. Till now it
> worked only because those clocks were enabled by bootloader and driver
> probe() happened before they were disabled by clock core because of lack
> of users. Handling those clocks is also needed to make it possible to
> enable support for audio power domain.
> 
> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
> ---
>  .../devicetree/bindings/mfd/samsung,exynos5433-lpass.txt       |  6 ++++++
>  drivers/mfd/exynos-lpass.c                                     | 10 ++++++++++
>  2 files changed, 16 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/mfd/samsung,exynos5433-lpass.txt b/Documentation/devicetree/bindings/mfd/samsung,exynos5433-lpass.txt
> index a8deaee82c44..df664018c148 100644
> --- a/Documentation/devicetree/bindings/mfd/samsung,exynos5433-lpass.txt
> +++ b/Documentation/devicetree/bindings/mfd/samsung,exynos5433-lpass.txt
> @@ -5,6 +5,10 @@ Required properties:
>   - compatible		: "samsung,exynos5433-lpass"
>   - reg			: should contain the LPASS top SFR region location
>  			  and size
> + - clock-names		: should contain following required clocks: "sfr0_ctrl"
> + - clocks		: should contain clock specifiers of all clocks, which
> +			  input names have been specified in clock-names
> +			  property, in same order.
>   - #address-cells	: should be 1
>   - #size-cells		: should be 1
>   - ranges		: must be present
> @@ -24,6 +28,8 @@ Example:
>  audio-subsystem {
>  	compatible = "samsung,exynos5433-lpass";
>  	reg = <0x11400000 0x100>, <0x11500000 0x08>;
> +	clocks = <&cmu_aud CLK_PCLK_SFR0_CTRL>;
> +	clock-names = "sfr0_ctrl";
>  	#address-cells = <1>;
>  	#size-cells = <1>;
>  	ranges;
> diff --git a/drivers/mfd/exynos-lpass.c b/drivers/mfd/exynos-lpass.c
> index 17915daa2e80..44d8ea1a978b 100644
> --- a/drivers/mfd/exynos-lpass.c
> +++ b/drivers/mfd/exynos-lpass.c
> @@ -14,6 +14,7 @@
>   * only version 2 as published by the Free Software Foundation.
>   */
>  
> +#include <linux/clk.h>
>  #include <linux/delay.h>
>  #include <linux/io.h>
>  #include <linux/module.h>
> @@ -52,6 +53,7 @@
>  struct exynos_lpass {
>  	/* pointer to the LPASS TOP regmap */
>  	struct regmap *top;
> +	struct clk *sfr0_clk;
>  };
>  
>  static void exynos_lpass_core_sw_reset(struct exynos_lpass *lpass, int mask)
> @@ -71,6 +73,8 @@ static void exynos_lpass_core_sw_reset(struct exynos_lpass *lpass, int mask)
>  
>  static void exynos_lpass_enable(struct exynos_lpass *lpass)
>  {
> +	clk_prepare_enable(lpass->sfr0_clk);
> +
>  	/* Unmask SFR, DMA and I2S interrupt */
>  	regmap_write(lpass->top, SFR_LPASS_INTR_CA5_MASK,
>  		     LPASS_INTR_SFR | LPASS_INTR_DMA | LPASS_INTR_I2S);
> @@ -88,6 +92,8 @@ static void exynos_lpass_disable(struct exynos_lpass *lpass)
>  	/* Mask any unmasked IP interrupt sources */
>  	regmap_write(lpass->top, SFR_LPASS_INTR_CPU_MASK, 0);
>  	regmap_write(lpass->top, SFR_LPASS_INTR_CA5_MASK, 0);
> +
> +	clk_disable_unprepare(lpass->sfr0_clk);
>  }
>  
>  static const struct regmap_config exynos_lpass_reg_conf = {
> @@ -114,6 +120,10 @@ static int exynos_lpass_probe(struct platform_device *pdev)
>  	if (IS_ERR(base_top))
>  		return PTR_ERR(base_top);
>  
> +	lpass->sfr0_clk = clk_get(dev, "sfr0_ctrl");
> +	if (IS_ERR(lpass->sfr0_clk))
> +		return PTR_ERR(lpass->sfr0_clk);

devm_clk_get() or implement the remove() or the unbind should be
suppressed.

Not related to this particular patch, but:
1. regmap_exit() is also missing (anyone would like to add it?),
2. Also I wonder, whether we would like to disable the LPASS on
   unbind...

Best regards,
Krzysztof

[PATCH 6/7] mfd: exynos-lpass: Add support for clocks

[Krzysztof Kozlowski]

On Wed, Jan 25, 2017 at 10:00:06PM +0200, Krzysztof Kozlowski wrote:
> On Wed, Jan 25, 2017 at 12:50:30PM +0100, Marek Szyprowski wrote:
> > Exynos LPASS requires some clocks to be enabled to make any access to its
> > registers. This patch adds code for handling such clocks. For current set
> > of registers it is enough to keep sfr0_ctrl clock enabled. Till now it
> > worked only because those clocks were enabled by bootloader and driver
> > probe() happened before they were disabled by clock core because of lack
> > of users. Handling those clocks is also needed to make it possible to
> > enable support for audio power domain.
> > 
> > Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
> > ---
> >  .../devicetree/bindings/mfd/samsung,exynos5433-lpass.txt       |  6 ++++++
> >  drivers/mfd/exynos-lpass.c                                     | 10 ++++++++++
> >  2 files changed, 16 insertions(+)
> > 
> > diff --git a/Documentation/devicetree/bindings/mfd/samsung,exynos5433-lpass.txt b/Documentation/devicetree/bindings/mfd/samsung,exynos5433-lpass.txt
> > index a8deaee82c44..df664018c148 100644
> > --- a/Documentation/devicetree/bindings/mfd/samsung,exynos5433-lpass.txt
> > +++ b/Documentation/devicetree/bindings/mfd/samsung,exynos5433-lpass.txt
> > @@ -5,6 +5,10 @@ Required properties:
> >   - compatible		: "samsung,exynos5433-lpass"
> >   - reg			: should contain the LPASS top SFR region location
> >  			  and size
> > + - clock-names		: should contain following required clocks: "sfr0_ctrl"
> > + - clocks		: should contain clock specifiers of all clocks, which
> > +			  input names have been specified in clock-names
> > +			  property, in same order.
> >   - #address-cells	: should be 1
> >   - #size-cells		: should be 1
> >   - ranges		: must be present
> > @@ -24,6 +28,8 @@ Example:
> >  audio-subsystem {
> >  	compatible = "samsung,exynos5433-lpass";
> >  	reg = <0x11400000 0x100>, <0x11500000 0x08>;
> > +	clocks = <&cmu_aud CLK_PCLK_SFR0_CTRL>;
> > +	clock-names = "sfr0_ctrl";
> >  	#address-cells = <1>;
> >  	#size-cells = <1>;
> >  	ranges;
> > diff --git a/drivers/mfd/exynos-lpass.c b/drivers/mfd/exynos-lpass.c
> > index 17915daa2e80..44d8ea1a978b 100644
> > --- a/drivers/mfd/exynos-lpass.c
> > +++ b/drivers/mfd/exynos-lpass.c
> > @@ -14,6 +14,7 @@
> >   * only version 2 as published by the Free Software Foundation.
> >   */
> >  
> > +#include <linux/clk.h>
> >  #include <linux/delay.h>
> >  #include <linux/io.h>
> >  #include <linux/module.h>
> > @@ -52,6 +53,7 @@
> >  struct exynos_lpass {
> >  	/* pointer to the LPASS TOP regmap */
> >  	struct regmap *top;
> > +	struct clk *sfr0_clk;
> >  };
> >  
> >  static void exynos_lpass_core_sw_reset(struct exynos_lpass *lpass, int mask)
> > @@ -71,6 +73,8 @@ static void exynos_lpass_core_sw_reset(struct exynos_lpass *lpass, int mask)
> >  
> >  static void exynos_lpass_enable(struct exynos_lpass *lpass)
> >  {
> > +	clk_prepare_enable(lpass->sfr0_clk);
> > +
> >  	/* Unmask SFR, DMA and I2S interrupt */
> >  	regmap_write(lpass->top, SFR_LPASS_INTR_CA5_MASK,
> >  		     LPASS_INTR_SFR | LPASS_INTR_DMA | LPASS_INTR_I2S);
> > @@ -88,6 +92,8 @@ static void exynos_lpass_disable(struct exynos_lpass *lpass)
> >  	/* Mask any unmasked IP interrupt sources */
> >  	regmap_write(lpass->top, SFR_LPASS_INTR_CPU_MASK, 0);
> >  	regmap_write(lpass->top, SFR_LPASS_INTR_CA5_MASK, 0);
> > +
> > +	clk_disable_unprepare(lpass->sfr0_clk);
> >  }
> >  
> >  static const struct regmap_config exynos_lpass_reg_conf = {
> > @@ -114,6 +120,10 @@ static int exynos_lpass_probe(struct platform_device *pdev)
> >  	if (IS_ERR(base_top))
> >  		return PTR_ERR(base_top);
> >  
> > +	lpass->sfr0_clk = clk_get(dev, "sfr0_ctrl");
> > +	if (IS_ERR(lpass->sfr0_clk))
> > +		return PTR_ERR(lpass->sfr0_clk);
> 
> devm_clk_get() or implement the remove() or the unbind should be
> suppressed.
> 
> Not related to this particular patch, but:
> 1. regmap_exit() is also missing (anyone would like to add it?),
> 2. Also I wonder, whether we would like to disable the LPASS on
>    unbind...

I forgot about one thing - please mention in the commit message that
this breaks the ABI or requires changes in DTS to provide the clock.

Best regards,
Krzysztof

[PATCH 7/7] mfd: exynos-lpass: Add runtime PM support

[Marek Szyprowski]

Convert exisitng lpass-suspend/resume callbacks into runtime PM callbacks.
This way Exynos LPASS driver will be ready for use with power domains
enabled. LPASS will be runtime resumed/suspended as a result of its child
devices runtime PM transitions.

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
---
 drivers/mfd/exynos-lpass.c | 10 ++++++++--
 1 file changed, 8 insertions(+), 2 deletions(-)

diff --git a/drivers/mfd/exynos-lpass.c b/drivers/mfd/exynos-lpass.c
index 44d8ea1a978b..d383b2f6f207 100644
--- a/drivers/mfd/exynos-lpass.c
+++ b/drivers/mfd/exynos-lpass.c
@@ -22,6 +22,7 @@
 #include <linux/of.h>
 #include <linux/of_platform.h>
 #include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
 #include <linux/regmap.h>
 #include <linux/types.h>
 
@@ -132,6 +133,8 @@ static int exynos_lpass_probe(struct platform_device *pdev)
 	}
 
 	platform_set_drvdata(pdev, lpass);
+	pm_runtime_set_active(dev);
+	pm_runtime_enable(dev);
 	exynos_lpass_enable(lpass);
 
 	return of_platform_populate(dev->of_node, NULL, NULL, dev);
@@ -155,8 +158,11 @@ static int __maybe_unused exynos_lpass_resume(struct device *dev)
 	return 0;
 }
 
-static SIMPLE_DEV_PM_OPS(lpass_pm_ops, exynos_lpass_suspend,
-					exynos_lpass_resume);
+static const struct dev_pm_ops lpass_pm_ops = {
+	SET_RUNTIME_PM_OPS(exynos_lpass_suspend, exynos_lpass_resume, NULL)
+	SET_LATE_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
+				     pm_runtime_force_resume)
+};
 
 static const struct of_device_id exynos_lpass_of_match[] = {
 	{ .compatible = "samsung,exynos5433-lpass" },
-- 
1.9.1

[PATCH 7/7] mfd: exynos-lpass: Add runtime PM support

[Krzysztof Kozlowski]

On Wed, Jan 25, 2017 at 12:50:31PM +0100, Marek Szyprowski wrote:
> Convert exisitng lpass-suspend/resume callbacks into runtime PM callbacks.
> This way Exynos LPASS driver will be ready for use with power domains
> enabled. LPASS will be runtime resumed/suspended as a result of its child
> devices runtime PM transitions.
> 
> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
> ---
>  drivers/mfd/exynos-lpass.c | 10 ++++++++--
>  1 file changed, 8 insertions(+), 2 deletions(-)
> 

Acked-by: Krzysztof Kozlowski <krzk@kernel.org>

Best regards,
Krzysztof