* [PATCH v4 1/9] arm64: allwinner: Kconfig: add essential pinctrl driver for H5
2017-02-07 18:30 [PATCH v4 0/9] Allwinner H5 and Orange Pi PC2 support Icenowy Zheng
@ 2017-02-07 18:30 ` Icenowy Zheng
2017-02-07 18:30 ` [PATCH v4 2/9] clk: sunxi-ng: rename sun8i-h3 driver to sunxi-h3-h5 Icenowy Zheng
` (7 subsequent siblings)
8 siblings, 0 replies; 13+ messages in thread
From: Icenowy Zheng @ 2017-02-07 18:30 UTC (permalink / raw)
To: linux-arm-kernel
H5 SoC has two pin controllers, one (in user manual called "CPUx") needs
a slightly advanced driver, and the other (called "CPUs") is just equal
to the on in H3, and the H3 driver can be just reused.
Select the two necessary pinctrl drivers when building kernel for
Allwinner SoCs.
Also add H5 in the option's description.
Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
---
arch/arm64/Kconfig.platforms | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
index 715ef1256838..e11523d204b5 100644
--- a/arch/arm64/Kconfig.platforms
+++ b/arch/arm64/Kconfig.platforms
@@ -5,8 +5,11 @@ config ARCH_SUNXI
select GENERIC_IRQ_CHIP
select PINCTRL
select PINCTRL_SUN50I_A64
+ select PINCTRL_SUN50I_H5
+ select PINCTRL_SUN8I_H3_R
help
- This enables support for Allwinner sunxi based SoCs like the A64.
+ This enables support for Allwinner sunxi based SoCs like the A64
+ and H5.
config ARCH_ALPINE
bool "Annapurna Labs Alpine platform"
--
2.11.0
^ permalink raw reply related [flat|nested] 13+ messages in thread* [PATCH v4 2/9] clk: sunxi-ng: rename sun8i-h3 driver to sunxi-h3-h5
2017-02-07 18:30 [PATCH v4 0/9] Allwinner H5 and Orange Pi PC2 support Icenowy Zheng
2017-02-07 18:30 ` [PATCH v4 1/9] arm64: allwinner: Kconfig: add essential pinctrl driver for H5 Icenowy Zheng
@ 2017-02-07 18:30 ` Icenowy Zheng
2017-02-08 8:01 ` Maxime Ripard
2017-02-07 18:30 ` [PATCH v4 3/9] clk: sunxi-ng: add support for Allwinner H5 SoC Icenowy Zheng
` (6 subsequent siblings)
8 siblings, 1 reply; 13+ messages in thread
From: Icenowy Zheng @ 2017-02-07 18:30 UTC (permalink / raw)
To: linux-arm-kernel
As the CCU in the Allwinner H5 SoC is very similar to the one in H3,
rename the H3 driver to sunxi-h3-h5 so that it can be extended with H5
support.
Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
---
Changes in v4:
- Fixed an indent issue.
drivers/clk/sunxi-ng/Kconfig | 4 +-
drivers/clk/sunxi-ng/Makefile | 2 +-
.../sunxi-ng/{ccu-sun8i-h3.c => ccu-sunxi-h3-h5.c} | 42 +++---
.../sunxi-ng/{ccu-sun8i-h3.h => ccu-sunxi-h3-h5.h} | 10 +-
include/dt-bindings/clock/sun8i-h3-ccu.h | 146 +--------------------
.../clock/{sun8i-h3-ccu.h => sunxi-h3-h5-ccu.h} | 8 +-
include/dt-bindings/reset/sun8i-h3-ccu.h | 104 +--------------
.../reset/{sun8i-h3-ccu.h => sunxi-h3-h5-ccu.h} | 8 +-
8 files changed, 42 insertions(+), 282 deletions(-)
rename drivers/clk/sunxi-ng/{ccu-sun8i-h3.c => ccu-sunxi-h3-h5.c} (96%)
rename drivers/clk/sunxi-ng/{ccu-sun8i-h3.h => ccu-sunxi-h3-h5.h} (88%)
rewrite include/dt-bindings/clock/sun8i-h3-ccu.h (100%)
mode change 100644 => 120000
copy include/dt-bindings/clock/{sun8i-h3-ccu.h => sunxi-h3-h5-ccu.h} (96%)
rewrite include/dt-bindings/reset/sun8i-h3-ccu.h (100%)
mode change 100644 => 120000
copy include/dt-bindings/reset/{sun8i-h3-ccu.h => sunxi-h3-h5-ccu.h} (95%)
diff --git a/drivers/clk/sunxi-ng/Kconfig b/drivers/clk/sunxi-ng/Kconfig
index 67659091860d..edc5bbbcb5bb 100644
--- a/drivers/clk/sunxi-ng/Kconfig
+++ b/drivers/clk/sunxi-ng/Kconfig
@@ -108,8 +108,8 @@ config SUN8I_A33_CCU
select SUNXI_CCU_PHASE
default MACH_SUN8I
-config SUN8I_H3_CCU
- bool "Support for the Allwinner H3 CCU"
+config SUNXI_H3_H5_CCU
+ bool "Support for the Allwinner H3/H5 CCU"
select SUNXI_CCU_DIV
select SUNXI_CCU_NK
select SUNXI_CCU_NKM
diff --git a/drivers/clk/sunxi-ng/Makefile b/drivers/clk/sunxi-ng/Makefile
index 6feaac0c5600..22649859b5a9 100644
--- a/drivers/clk/sunxi-ng/Makefile
+++ b/drivers/clk/sunxi-ng/Makefile
@@ -23,7 +23,7 @@ obj-$(CONFIG_SUN5I_CCU) += ccu-sun5i.o
obj-$(CONFIG_SUN6I_A31_CCU) += ccu-sun6i-a31.o
obj-$(CONFIG_SUN8I_A23_CCU) += ccu-sun8i-a23.o
obj-$(CONFIG_SUN8I_A33_CCU) += ccu-sun8i-a33.o
-obj-$(CONFIG_SUN8I_H3_CCU) += ccu-sun8i-h3.o
+obj-$(CONFIG_SUNXI_H3_H5_CCU) += ccu-sunxi-h3-h5.o
obj-$(CONFIG_SUN8I_V3S_CCU) += ccu-sun8i-v3s.o
obj-$(CONFIG_SUN9I_A80_CCU) += ccu-sun9i-a80.o
obj-$(CONFIG_SUN9I_A80_CCU) += ccu-sun9i-a80-de.o
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c b/drivers/clk/sunxi-ng/ccu-sunxi-h3-h5.c
similarity index 96%
rename from drivers/clk/sunxi-ng/ccu-sun8i-h3.c
rename to drivers/clk/sunxi-ng/ccu-sunxi-h3-h5.c
index a26c8a19fe93..e2d065973794 100644
--- a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
+++ b/drivers/clk/sunxi-ng/ccu-sunxi-h3-h5.c
@@ -27,7 +27,7 @@
#include "ccu_nm.h"
#include "ccu_phase.h"
-#include "ccu-sun8i-h3.h"
+#include "ccu-sunxi-h3-h5.h"
static SUNXI_CCU_NKMP_WITH_GATE_LOCK(pll_cpux_clk, "pll-cpux",
"osc24M", 0x000,
@@ -47,7 +47,7 @@ static SUNXI_CCU_NKMP_WITH_GATE_LOCK(pll_cpux_clk, "pll-cpux",
* We don't have any need for the variable divider for now, so we just
* hardcode it to match with the clock names
*/
-#define SUN8I_H3_PLL_AUDIO_REG 0x008
+#define SUNXI_H3_H5_PLL_AUDIO_REG 0x008
static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_audio_base_clk, "pll-audio-base",
"osc24M", 0x008,
@@ -300,7 +300,7 @@ static SUNXI_CCU_GATE(bus_uart2_clk, "bus-uart2", "apb2",
0x06c, BIT(18), 0);
static SUNXI_CCU_GATE(bus_uart3_clk, "bus-uart3", "apb2",
0x06c, BIT(19), 0);
-static SUNXI_CCU_GATE(bus_scr_clk, "bus-scr", "apb2",
+static SUNXI_CCU_GATE(bus_scr0_clk, "bus-scr0", "apb2",
0x06c, BIT(20), 0);
static SUNXI_CCU_GATE(bus_ephy_clk, "bus-ephy", "ahb1",
@@ -484,7 +484,7 @@ static SUNXI_CCU_M_WITH_MUX_GATE(mbus_clk, "mbus", mbus_parents,
static SUNXI_CCU_M_WITH_GATE(gpu_clk, "gpu", "pll-gpu",
0x1a0, 0, 3, BIT(31), 0);
-static struct ccu_common *sun8i_h3_ccu_clks[] = {
+static struct ccu_common *sunxi_h3_h5_ccu_clks[] = {
&pll_cpux_clk.common,
&pll_audio_base_clk.common,
&pll_video_clk.common,
@@ -546,7 +546,7 @@ static struct ccu_common *sun8i_h3_ccu_clks[] = {
&bus_uart1_clk.common,
&bus_uart2_clk.common,
&bus_uart3_clk.common,
- &bus_scr_clk.common,
+ &bus_scr0_clk.common,
&bus_ephy_clk.common,
&bus_dbg_clk.common,
&ths_clk.common,
@@ -677,7 +677,7 @@ static struct clk_hw_onecell_data sun8i_h3_hw_clks = {
[CLK_BUS_UART1] = &bus_uart1_clk.common.hw,
[CLK_BUS_UART2] = &bus_uart2_clk.common.hw,
[CLK_BUS_UART3] = &bus_uart3_clk.common.hw,
- [CLK_BUS_SCR] = &bus_scr_clk.common.hw,
+ [CLK_BUS_SCR0] = &bus_scr0_clk.common.hw,
[CLK_BUS_EPHY] = &bus_ephy_clk.common.hw,
[CLK_BUS_DBG] = &bus_dbg_clk.common.hw,
[CLK_THS] = &ths_clk.common.hw,
@@ -730,7 +730,7 @@ static struct clk_hw_onecell_data sun8i_h3_hw_clks = {
.num = CLK_NUMBER,
};
-static struct ccu_reset_map sun8i_h3_ccu_resets[] = {
+static struct ccu_reset_map sunxi_h3_h5_ccu_resets[] = {
[RST_USB_PHY0] = { 0x0cc, BIT(0) },
[RST_USB_PHY1] = { 0x0cc, BIT(1) },
[RST_USB_PHY2] = { 0x0cc, BIT(2) },
@@ -790,27 +790,28 @@ static struct ccu_reset_map sun8i_h3_ccu_resets[] = {
[RST_BUS_UART1] = { 0x2d8, BIT(17) },
[RST_BUS_UART2] = { 0x2d8, BIT(18) },
[RST_BUS_UART3] = { 0x2d8, BIT(19) },
- [RST_BUS_SCR] = { 0x2d8, BIT(20) },
+ [RST_BUS_SCR0] = { 0x2d8, BIT(20) },
};
static const struct sunxi_ccu_desc sun8i_h3_ccu_desc = {
- .ccu_clks = sun8i_h3_ccu_clks,
- .num_ccu_clks = ARRAY_SIZE(sun8i_h3_ccu_clks),
+ .ccu_clks = sunxi_h3_h5_ccu_clks,
+ .num_ccu_clks = ARRAY_SIZE(sunxi_h3_h5_ccu_clks),
.hw_clks = &sun8i_h3_hw_clks,
- .resets = sun8i_h3_ccu_resets,
- .num_resets = ARRAY_SIZE(sun8i_h3_ccu_resets),
+ .resets = sunxi_h3_h5_ccu_resets,
+ .num_resets = ARRAY_SIZE(sunxi_h3_h5_ccu_resets),
};
-static struct ccu_mux_nb sun8i_h3_cpu_nb = {
+static struct ccu_mux_nb sunxi_h3_h5_cpu_nb = {
.common = &cpux_clk.common,
.cm = &cpux_clk.mux,
.delay_us = 1, /* > 8 clock cycles at 24 MHz */
.bypass_index = 1, /* index of 24 MHz oscillator */
};
-static void __init sun8i_h3_ccu_setup(struct device_node *node)
+static void __init sunxi_h3_h5_ccu_init(struct device_node *node,
+ const struct sunxi_ccu_desc *desc)
{
void __iomem *reg;
u32 val;
@@ -823,14 +824,19 @@ static void __init sun8i_h3_ccu_setup(struct device_node *node)
}
/* Force the PLL-Audio-1x divider to 4 */
- val = readl(reg + SUN8I_H3_PLL_AUDIO_REG);
+ val = readl(reg + SUNXI_H3_H5_PLL_AUDIO_REG);
val &= ~GENMASK(19, 16);
- writel(val | (3 << 16), reg + SUN8I_H3_PLL_AUDIO_REG);
+ writel(val | (3 << 16), reg + SUNXI_H3_H5_PLL_AUDIO_REG);
- sunxi_ccu_probe(node, reg, &sun8i_h3_ccu_desc);
+ sunxi_ccu_probe(node, reg, desc);
ccu_mux_notifier_register(pll_cpux_clk.common.hw.clk,
- &sun8i_h3_cpu_nb);
+ &sunxi_h3_h5_cpu_nb);
+}
+
+static void __init sun8i_h3_ccu_setup(struct device_node *node)
+{
+ sunxi_h3_h5_ccu_init(node, &sun8i_h3_ccu_desc);
}
CLK_OF_DECLARE(sun8i_h3_ccu, "allwinner,sun8i-h3-ccu",
sun8i_h3_ccu_setup);
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-h3.h b/drivers/clk/sunxi-ng/ccu-sunxi-h3-h5.h
similarity index 88%
rename from drivers/clk/sunxi-ng/ccu-sun8i-h3.h
rename to drivers/clk/sunxi-ng/ccu-sunxi-h3-h5.h
index 78be712c7487..e2a4656d2cf3 100644
--- a/drivers/clk/sunxi-ng/ccu-sun8i-h3.h
+++ b/drivers/clk/sunxi-ng/ccu-sunxi-h3-h5.h
@@ -14,11 +14,11 @@
* GNU General Public License for more details.
*/
-#ifndef _CCU_SUN8I_H3_H_
-#define _CCU_SUN8I_H3_H_
+#ifndef _CCU_SUNXI_H3_H5_H_
+#define _CCU_SUNXI_H3_H5_H_
-#include <dt-bindings/clock/sun8i-h3-ccu.h>
-#include <dt-bindings/reset/sun8i-h3-ccu.h>
+#include <dt-bindings/clock/sunxi-h3-h5-ccu.h>
+#include <dt-bindings/reset/sunxi-h3-h5-ccu.h>
#define CLK_PLL_CPUX 0
#define CLK_PLL_AUDIO_BASE 1
@@ -59,4 +59,4 @@
#define CLK_NUMBER (CLK_GPU + 1)
-#endif /* _CCU_SUN8I_H3_H_ */
+#endif /* _CCU_SUNXI_H3_H5_H_ */
diff --git a/include/dt-bindings/clock/sun8i-h3-ccu.h b/include/dt-bindings/clock/sun8i-h3-ccu.h
deleted file mode 100644
index efb7ba2bd515..000000000000
--- a/include/dt-bindings/clock/sun8i-h3-ccu.h
+++ /dev/null
@@ -1,145 +0,0 @@
-/*
- * Copyright (C) 2016 Maxime Ripard <maxime.ripard@free-electrons.com>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
-
-#ifndef _DT_BINDINGS_CLK_SUN8I_H3_H_
-#define _DT_BINDINGS_CLK_SUN8I_H3_H_
-
-#define CLK_CPUX 14
-
-#define CLK_BUS_CE 20
-#define CLK_BUS_DMA 21
-#define CLK_BUS_MMC0 22
-#define CLK_BUS_MMC1 23
-#define CLK_BUS_MMC2 24
-#define CLK_BUS_NAND 25
-#define CLK_BUS_DRAM 26
-#define CLK_BUS_EMAC 27
-#define CLK_BUS_TS 28
-#define CLK_BUS_HSTIMER 29
-#define CLK_BUS_SPI0 30
-#define CLK_BUS_SPI1 31
-#define CLK_BUS_OTG 32
-#define CLK_BUS_EHCI0 33
-#define CLK_BUS_EHCI1 34
-#define CLK_BUS_EHCI2 35
-#define CLK_BUS_EHCI3 36
-#define CLK_BUS_OHCI0 37
-#define CLK_BUS_OHCI1 38
-#define CLK_BUS_OHCI2 39
-#define CLK_BUS_OHCI3 40
-#define CLK_BUS_VE 41
-#define CLK_BUS_TCON0 42
-#define CLK_BUS_TCON1 43
-#define CLK_BUS_DEINTERLACE 44
-#define CLK_BUS_CSI 45
-#define CLK_BUS_TVE 46
-#define CLK_BUS_HDMI 47
-#define CLK_BUS_DE 48
-#define CLK_BUS_GPU 49
-#define CLK_BUS_MSGBOX 50
-#define CLK_BUS_SPINLOCK 51
-#define CLK_BUS_CODEC 52
-#define CLK_BUS_SPDIF 53
-#define CLK_BUS_PIO 54
-#define CLK_BUS_THS 55
-#define CLK_BUS_I2S0 56
-#define CLK_BUS_I2S1 57
-#define CLK_BUS_I2S2 58
-#define CLK_BUS_I2C0 59
-#define CLK_BUS_I2C1 60
-#define CLK_BUS_I2C2 61
-#define CLK_BUS_UART0 62
-#define CLK_BUS_UART1 63
-#define CLK_BUS_UART2 64
-#define CLK_BUS_UART3 65
-#define CLK_BUS_SCR 66
-#define CLK_BUS_EPHY 67
-#define CLK_BUS_DBG 68
-
-#define CLK_THS 69
-#define CLK_NAND 70
-#define CLK_MMC0 71
-#define CLK_MMC0_SAMPLE 72
-#define CLK_MMC0_OUTPUT 73
-#define CLK_MMC1 74
-#define CLK_MMC1_SAMPLE 75
-#define CLK_MMC1_OUTPUT 76
-#define CLK_MMC2 77
-#define CLK_MMC2_SAMPLE 78
-#define CLK_MMC2_OUTPUT 79
-#define CLK_TS 80
-#define CLK_CE 81
-#define CLK_SPI0 82
-#define CLK_SPI1 83
-#define CLK_I2S0 84
-#define CLK_I2S1 85
-#define CLK_I2S2 86
-#define CLK_SPDIF 87
-#define CLK_USB_PHY0 88
-#define CLK_USB_PHY1 89
-#define CLK_USB_PHY2 90
-#define CLK_USB_PHY3 91
-#define CLK_USB_OHCI0 92
-#define CLK_USB_OHCI1 93
-#define CLK_USB_OHCI2 94
-#define CLK_USB_OHCI3 95
-
-#define CLK_DRAM_VE 97
-#define CLK_DRAM_CSI 98
-#define CLK_DRAM_DEINTERLACE 99
-#define CLK_DRAM_TS 100
-#define CLK_DE 101
-#define CLK_TCON0 102
-#define CLK_TVE 103
-#define CLK_DEINTERLACE 104
-#define CLK_CSI_MISC 105
-#define CLK_CSI_SCLK 106
-#define CLK_CSI_MCLK 107
-#define CLK_VE 108
-#define CLK_AC_DIG 109
-#define CLK_AVS 110
-#define CLK_HDMI 111
-#define CLK_HDMI_DDC 112
-
-#define CLK_GPU 114
-
-#endif /* _DT_BINDINGS_CLK_SUN8I_H3_H_ */
diff --git a/include/dt-bindings/clock/sun8i-h3-ccu.h b/include/dt-bindings/clock/sun8i-h3-ccu.h
new file mode 120000
index 000000000000..ef38232141e4
--- /dev/null
+++ b/include/dt-bindings/clock/sun8i-h3-ccu.h
@@ -0,0 +1 @@
+sunxi-h3-h5-ccu.h
\ No newline at end of file
diff --git a/include/dt-bindings/clock/sun8i-h3-ccu.h b/include/dt-bindings/clock/sunxi-h3-h5-ccu.h
similarity index 96%
copy from include/dt-bindings/clock/sun8i-h3-ccu.h
copy to include/dt-bindings/clock/sunxi-h3-h5-ccu.h
index efb7ba2bd515..1715a5e12525 100644
--- a/include/dt-bindings/clock/sun8i-h3-ccu.h
+++ b/include/dt-bindings/clock/sunxi-h3-h5-ccu.h
@@ -40,8 +40,8 @@
* OTHER DEALINGS IN THE SOFTWARE.
*/
-#ifndef _DT_BINDINGS_CLK_SUN8I_H3_H_
-#define _DT_BINDINGS_CLK_SUN8I_H3_H_
+#ifndef _DT_BINDINGS_CLK_SUNXI_H3_H5_H_
+#define _DT_BINDINGS_CLK_SUNXI_H3_H5_H_
#define CLK_CPUX 14
@@ -91,7 +91,7 @@
#define CLK_BUS_UART1 63
#define CLK_BUS_UART2 64
#define CLK_BUS_UART3 65
-#define CLK_BUS_SCR 66
+#define CLK_BUS_SCR0 66
#define CLK_BUS_EPHY 67
#define CLK_BUS_DBG 68
@@ -142,4 +142,4 @@
#define CLK_GPU 114
-#endif /* _DT_BINDINGS_CLK_SUN8I_H3_H_ */
+#endif /* _DT_BINDINGS_CLK_SUNXI_H3_H5_H_ */
diff --git a/include/dt-bindings/reset/sun8i-h3-ccu.h b/include/dt-bindings/reset/sun8i-h3-ccu.h
deleted file mode 100644
index 6b7af80c26ec..000000000000
--- a/include/dt-bindings/reset/sun8i-h3-ccu.h
+++ /dev/null
@@ -1,103 +0,0 @@
-/*
- * Copyright (C) 2016 Maxime Ripard <maxime.ripard@free-electrons.com>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
-
-#ifndef _DT_BINDINGS_RST_SUN8I_H3_H_
-#define _DT_BINDINGS_RST_SUN8I_H3_H_
-
-#define RST_USB_PHY0 0
-#define RST_USB_PHY1 1
-#define RST_USB_PHY2 2
-#define RST_USB_PHY3 3
-
-#define RST_MBUS 4
-
-#define RST_BUS_CE 5
-#define RST_BUS_DMA 6
-#define RST_BUS_MMC0 7
-#define RST_BUS_MMC1 8
-#define RST_BUS_MMC2 9
-#define RST_BUS_NAND 10
-#define RST_BUS_DRAM 11
-#define RST_BUS_EMAC 12
-#define RST_BUS_TS 13
-#define RST_BUS_HSTIMER 14
-#define RST_BUS_SPI0 15
-#define RST_BUS_SPI1 16
-#define RST_BUS_OTG 17
-#define RST_BUS_EHCI0 18
-#define RST_BUS_EHCI1 19
-#define RST_BUS_EHCI2 20
-#define RST_BUS_EHCI3 21
-#define RST_BUS_OHCI0 22
-#define RST_BUS_OHCI1 23
-#define RST_BUS_OHCI2 24
-#define RST_BUS_OHCI3 25
-#define RST_BUS_VE 26
-#define RST_BUS_TCON0 27
-#define RST_BUS_TCON1 28
-#define RST_BUS_DEINTERLACE 29
-#define RST_BUS_CSI 30
-#define RST_BUS_TVE 31
-#define RST_BUS_HDMI0 32
-#define RST_BUS_HDMI1 33
-#define RST_BUS_DE 34
-#define RST_BUS_GPU 35
-#define RST_BUS_MSGBOX 36
-#define RST_BUS_SPINLOCK 37
-#define RST_BUS_DBG 38
-#define RST_BUS_EPHY 39
-#define RST_BUS_CODEC 40
-#define RST_BUS_SPDIF 41
-#define RST_BUS_THS 42
-#define RST_BUS_I2S0 43
-#define RST_BUS_I2S1 44
-#define RST_BUS_I2S2 45
-#define RST_BUS_I2C0 46
-#define RST_BUS_I2C1 47
-#define RST_BUS_I2C2 48
-#define RST_BUS_UART0 49
-#define RST_BUS_UART1 50
-#define RST_BUS_UART2 51
-#define RST_BUS_UART3 52
-#define RST_BUS_SCR 53
-
-#endif /* _DT_BINDINGS_RST_SUN8I_H3_H_ */
diff --git a/include/dt-bindings/reset/sun8i-h3-ccu.h b/include/dt-bindings/reset/sun8i-h3-ccu.h
new file mode 120000
index 000000000000..ef38232141e4
--- /dev/null
+++ b/include/dt-bindings/reset/sun8i-h3-ccu.h
@@ -0,0 +1 @@
+sunxi-h3-h5-ccu.h
\ No newline at end of file
diff --git a/include/dt-bindings/reset/sun8i-h3-ccu.h b/include/dt-bindings/reset/sunxi-h3-h5-ccu.h
similarity index 95%
copy from include/dt-bindings/reset/sun8i-h3-ccu.h
copy to include/dt-bindings/reset/sunxi-h3-h5-ccu.h
index 6b7af80c26ec..7a5de896cf1f 100644
--- a/include/dt-bindings/reset/sun8i-h3-ccu.h
+++ b/include/dt-bindings/reset/sunxi-h3-h5-ccu.h
@@ -40,8 +40,8 @@
* OTHER DEALINGS IN THE SOFTWARE.
*/
-#ifndef _DT_BINDINGS_RST_SUN8I_H3_H_
-#define _DT_BINDINGS_RST_SUN8I_H3_H_
+#ifndef _DT_BINDINGS_RST_SUNXI_H3_H5_H_
+#define _DT_BINDINGS_RST_SUNXI_H3_H5_H_
#define RST_USB_PHY0 0
#define RST_USB_PHY1 1
@@ -98,6 +98,6 @@
#define RST_BUS_UART1 50
#define RST_BUS_UART2 51
#define RST_BUS_UART3 52
-#define RST_BUS_SCR 53
+#define RST_BUS_SCR0 53
-#endif /* _DT_BINDINGS_RST_SUN8I_H3_H_ */
+#endif /* _DT_BINDINGS_RST_SUNXI_H3_H5_H_ */
--
2.11.0
^ permalink raw reply related [flat|nested] 13+ messages in thread* [PATCH v4 3/9] clk: sunxi-ng: add support for Allwinner H5 SoC
2017-02-07 18:30 [PATCH v4 0/9] Allwinner H5 and Orange Pi PC2 support Icenowy Zheng
2017-02-07 18:30 ` [PATCH v4 1/9] arm64: allwinner: Kconfig: add essential pinctrl driver for H5 Icenowy Zheng
2017-02-07 18:30 ` [PATCH v4 2/9] clk: sunxi-ng: rename sun8i-h3 driver to sunxi-h3-h5 Icenowy Zheng
@ 2017-02-07 18:30 ` Icenowy Zheng
2017-02-08 8:00 ` Maxime Ripard
2017-02-07 18:30 ` [PATCH v4 4/9] ARM: dts: sun8i: convert H3 dtsi to use new sunxi-h3-h5 binding header Icenowy Zheng
` (5 subsequent siblings)
8 siblings, 1 reply; 13+ messages in thread
From: Icenowy Zheng @ 2017-02-07 18:30 UTC (permalink / raw)
To: linux-arm-kernel
Allwinner H5 is a SoC that features a CCU like H3, but with MMC phase
clocks removed (for new MMC controller) and a new bus gate/reset
imported.
Add support for it.
Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
---
Changes since v3:
- Add a dedicated reset line list for H5, as SCR1 reset is not valid
on H3.
.../devicetree/bindings/clock/sunxi-ccu.txt | 1 +
drivers/clk/sunxi-ng/Kconfig | 2 +-
drivers/clk/sunxi-ng/ccu-sunxi-h3-h5.c | 206 ++++++++++++++++++++-
drivers/clk/sunxi-ng/ccu-sunxi-h3-h5.h | 5 +-
include/dt-bindings/clock/sunxi-h3-h5-ccu.h | 3 +
include/dt-bindings/reset/sunxi-h3-h5-ccu.h | 3 +
6 files changed, 215 insertions(+), 5 deletions(-)
diff --git a/Documentation/devicetree/bindings/clock/sunxi-ccu.txt b/Documentation/devicetree/bindings/clock/sunxi-ccu.txt
index bae5668cf427..68512aa398a9 100644
--- a/Documentation/devicetree/bindings/clock/sunxi-ccu.txt
+++ b/Documentation/devicetree/bindings/clock/sunxi-ccu.txt
@@ -10,6 +10,7 @@ Required properties :
- "allwinner,sun8i-v3s-ccu"
- "allwinner,sun9i-a80-ccu"
- "allwinner,sun50i-a64-ccu"
+ - "allwinner,sun50i-h5-ccu"
- reg: Must contain the registers base address and length
- clocks: phandle to the oscillators feeding the CCU. Two are needed:
diff --git a/drivers/clk/sunxi-ng/Kconfig b/drivers/clk/sunxi-ng/Kconfig
index edc5bbbcb5bb..ec3e5f56b6ec 100644
--- a/drivers/clk/sunxi-ng/Kconfig
+++ b/drivers/clk/sunxi-ng/Kconfig
@@ -117,7 +117,7 @@ config SUNXI_H3_H5_CCU
select SUNXI_CCU_NM
select SUNXI_CCU_MP
select SUNXI_CCU_PHASE
- default MACH_SUN8I
+ default MACH_SUN8I || (ARM64 && ARCH_SUNXI)
config SUN8I_V3S_CCU
bool "Support for the Allwinner V3s CCU"
diff --git a/drivers/clk/sunxi-ng/ccu-sunxi-h3-h5.c b/drivers/clk/sunxi-ng/ccu-sunxi-h3-h5.c
index e2d065973794..360709966e8f 100644
--- a/drivers/clk/sunxi-ng/ccu-sunxi-h3-h5.c
+++ b/drivers/clk/sunxi-ng/ccu-sunxi-h3-h5.c
@@ -302,6 +302,8 @@ static SUNXI_CCU_GATE(bus_uart3_clk, "bus-uart3", "apb2",
0x06c, BIT(19), 0);
static SUNXI_CCU_GATE(bus_scr0_clk, "bus-scr0", "apb2",
0x06c, BIT(20), 0);
+static SUNXI_CCU_GATE(bus_scr1_clk, "bus-scr1", "apb2",
+ 0x06c, BIT(21), 0);
static SUNXI_CCU_GATE(bus_ephy_clk, "bus-ephy", "ahb1",
0x070, BIT(0), 0);
@@ -547,6 +549,7 @@ static struct ccu_common *sunxi_h3_h5_ccu_clks[] = {
&bus_uart2_clk.common,
&bus_uart3_clk.common,
&bus_scr0_clk.common,
+ &bus_scr1_clk.common,
&bus_ephy_clk.common,
&bus_dbg_clk.common,
&ths_clk.common,
@@ -730,7 +733,186 @@ static struct clk_hw_onecell_data sun8i_h3_hw_clks = {
.num = CLK_NUMBER,
};
-static struct ccu_reset_map sunxi_h3_h5_ccu_resets[] = {
+static struct clk_hw_onecell_data sun50i_h5_hw_clks = {
+ .hws = {
+ [CLK_PLL_CPUX] = &pll_cpux_clk.common.hw,
+ [CLK_PLL_AUDIO_BASE] = &pll_audio_base_clk.common.hw,
+ [CLK_PLL_AUDIO] = &pll_audio_clk.hw,
+ [CLK_PLL_AUDIO_2X] = &pll_audio_2x_clk.hw,
+ [CLK_PLL_AUDIO_4X] = &pll_audio_4x_clk.hw,
+ [CLK_PLL_AUDIO_8X] = &pll_audio_8x_clk.hw,
+ [CLK_PLL_VIDEO] = &pll_video_clk.common.hw,
+ [CLK_PLL_VE] = &pll_ve_clk.common.hw,
+ [CLK_PLL_DDR] = &pll_ddr_clk.common.hw,
+ [CLK_PLL_PERIPH0] = &pll_periph0_clk.common.hw,
+ [CLK_PLL_PERIPH0_2X] = &pll_periph0_2x_clk.hw,
+ [CLK_PLL_GPU] = &pll_gpu_clk.common.hw,
+ [CLK_PLL_PERIPH1] = &pll_periph1_clk.common.hw,
+ [CLK_PLL_DE] = &pll_de_clk.common.hw,
+ [CLK_CPUX] = &cpux_clk.common.hw,
+ [CLK_AXI] = &axi_clk.common.hw,
+ [CLK_AHB1] = &ahb1_clk.common.hw,
+ [CLK_APB1] = &apb1_clk.common.hw,
+ [CLK_APB2] = &apb2_clk.common.hw,
+ [CLK_AHB2] = &ahb2_clk.common.hw,
+ [CLK_BUS_CE] = &bus_ce_clk.common.hw,
+ [CLK_BUS_DMA] = &bus_dma_clk.common.hw,
+ [CLK_BUS_MMC0] = &bus_mmc0_clk.common.hw,
+ [CLK_BUS_MMC1] = &bus_mmc1_clk.common.hw,
+ [CLK_BUS_MMC2] = &bus_mmc2_clk.common.hw,
+ [CLK_BUS_NAND] = &bus_nand_clk.common.hw,
+ [CLK_BUS_DRAM] = &bus_dram_clk.common.hw,
+ [CLK_BUS_EMAC] = &bus_emac_clk.common.hw,
+ [CLK_BUS_TS] = &bus_ts_clk.common.hw,
+ [CLK_BUS_HSTIMER] = &bus_hstimer_clk.common.hw,
+ [CLK_BUS_SPI0] = &bus_spi0_clk.common.hw,
+ [CLK_BUS_SPI1] = &bus_spi1_clk.common.hw,
+ [CLK_BUS_OTG] = &bus_otg_clk.common.hw,
+ [CLK_BUS_EHCI0] = &bus_ehci0_clk.common.hw,
+ [CLK_BUS_EHCI1] = &bus_ehci1_clk.common.hw,
+ [CLK_BUS_EHCI2] = &bus_ehci2_clk.common.hw,
+ [CLK_BUS_EHCI3] = &bus_ehci3_clk.common.hw,
+ [CLK_BUS_OHCI0] = &bus_ohci0_clk.common.hw,
+ [CLK_BUS_OHCI1] = &bus_ohci1_clk.common.hw,
+ [CLK_BUS_OHCI2] = &bus_ohci2_clk.common.hw,
+ [CLK_BUS_OHCI3] = &bus_ohci3_clk.common.hw,
+ [CLK_BUS_VE] = &bus_ve_clk.common.hw,
+ [CLK_BUS_TCON0] = &bus_tcon0_clk.common.hw,
+ [CLK_BUS_TCON1] = &bus_tcon1_clk.common.hw,
+ [CLK_BUS_DEINTERLACE] = &bus_deinterlace_clk.common.hw,
+ [CLK_BUS_CSI] = &bus_csi_clk.common.hw,
+ [CLK_BUS_TVE] = &bus_tve_clk.common.hw,
+ [CLK_BUS_HDMI] = &bus_hdmi_clk.common.hw,
+ [CLK_BUS_DE] = &bus_de_clk.common.hw,
+ [CLK_BUS_GPU] = &bus_gpu_clk.common.hw,
+ [CLK_BUS_MSGBOX] = &bus_msgbox_clk.common.hw,
+ [CLK_BUS_SPINLOCK] = &bus_spinlock_clk.common.hw,
+ [CLK_BUS_CODEC] = &bus_codec_clk.common.hw,
+ [CLK_BUS_SPDIF] = &bus_spdif_clk.common.hw,
+ [CLK_BUS_PIO] = &bus_pio_clk.common.hw,
+ [CLK_BUS_THS] = &bus_ths_clk.common.hw,
+ [CLK_BUS_I2S0] = &bus_i2s0_clk.common.hw,
+ [CLK_BUS_I2S1] = &bus_i2s1_clk.common.hw,
+ [CLK_BUS_I2S2] = &bus_i2s2_clk.common.hw,
+ [CLK_BUS_I2C0] = &bus_i2c0_clk.common.hw,
+ [CLK_BUS_I2C1] = &bus_i2c1_clk.common.hw,
+ [CLK_BUS_I2C2] = &bus_i2c2_clk.common.hw,
+ [CLK_BUS_UART0] = &bus_uart0_clk.common.hw,
+ [CLK_BUS_UART1] = &bus_uart1_clk.common.hw,
+ [CLK_BUS_UART2] = &bus_uart2_clk.common.hw,
+ [CLK_BUS_UART3] = &bus_uart3_clk.common.hw,
+ [CLK_BUS_SCR0] = &bus_scr0_clk.common.hw,
+ [CLK_BUS_SCR1] = &bus_scr1_clk.common.hw,
+ [CLK_BUS_EPHY] = &bus_ephy_clk.common.hw,
+ [CLK_BUS_DBG] = &bus_dbg_clk.common.hw,
+ [CLK_THS] = &ths_clk.common.hw,
+ [CLK_NAND] = &nand_clk.common.hw,
+ [CLK_MMC0] = &mmc0_clk.common.hw,
+ [CLK_MMC1] = &mmc1_clk.common.hw,
+ [CLK_MMC2] = &mmc2_clk.common.hw,
+ [CLK_TS] = &ts_clk.common.hw,
+ [CLK_CE] = &ce_clk.common.hw,
+ [CLK_SPI0] = &spi0_clk.common.hw,
+ [CLK_SPI1] = &spi1_clk.common.hw,
+ [CLK_I2S0] = &i2s0_clk.common.hw,
+ [CLK_I2S1] = &i2s1_clk.common.hw,
+ [CLK_I2S2] = &i2s2_clk.common.hw,
+ [CLK_SPDIF] = &spdif_clk.common.hw,
+ [CLK_USB_PHY0] = &usb_phy0_clk.common.hw,
+ [CLK_USB_PHY1] = &usb_phy1_clk.common.hw,
+ [CLK_USB_PHY2] = &usb_phy2_clk.common.hw,
+ [CLK_USB_PHY3] = &usb_phy3_clk.common.hw,
+ [CLK_USB_OHCI0] = &usb_ohci0_clk.common.hw,
+ [CLK_USB_OHCI1] = &usb_ohci1_clk.common.hw,
+ [CLK_USB_OHCI2] = &usb_ohci2_clk.common.hw,
+ [CLK_USB_OHCI3] = &usb_ohci3_clk.common.hw,
+ [CLK_DRAM] = &dram_clk.common.hw,
+ [CLK_DRAM_VE] = &dram_ve_clk.common.hw,
+ [CLK_DRAM_CSI] = &dram_csi_clk.common.hw,
+ [CLK_DRAM_DEINTERLACE] = &dram_deinterlace_clk.common.hw,
+ [CLK_DRAM_TS] = &dram_ts_clk.common.hw,
+ [CLK_DE] = &de_clk.common.hw,
+ [CLK_TCON0] = &tcon_clk.common.hw,
+ [CLK_TVE] = &tve_clk.common.hw,
+ [CLK_DEINTERLACE] = &deinterlace_clk.common.hw,
+ [CLK_CSI_MISC] = &csi_misc_clk.common.hw,
+ [CLK_CSI_SCLK] = &csi_sclk_clk.common.hw,
+ [CLK_CSI_MCLK] = &csi_mclk_clk.common.hw,
+ [CLK_VE] = &ve_clk.common.hw,
+ [CLK_AC_DIG] = &ac_dig_clk.common.hw,
+ [CLK_AVS] = &avs_clk.common.hw,
+ [CLK_HDMI] = &hdmi_clk.common.hw,
+ [CLK_HDMI_DDC] = &hdmi_ddc_clk.common.hw,
+ [CLK_MBUS] = &mbus_clk.common.hw,
+ [CLK_GPU] = &gpu_clk.common.hw,
+ },
+ .num = CLK_NUMBER,
+};
+
+static struct ccu_reset_map sun8i_h3_ccu_resets[] = {
+ [RST_USB_PHY0] = { 0x0cc, BIT(0) },
+ [RST_USB_PHY1] = { 0x0cc, BIT(1) },
+ [RST_USB_PHY2] = { 0x0cc, BIT(2) },
+ [RST_USB_PHY3] = { 0x0cc, BIT(3) },
+
+ [RST_MBUS] = { 0x0fc, BIT(31) },
+
+ [RST_BUS_CE] = { 0x2c0, BIT(5) },
+ [RST_BUS_DMA] = { 0x2c0, BIT(6) },
+ [RST_BUS_MMC0] = { 0x2c0, BIT(8) },
+ [RST_BUS_MMC1] = { 0x2c0, BIT(9) },
+ [RST_BUS_MMC2] = { 0x2c0, BIT(10) },
+ [RST_BUS_NAND] = { 0x2c0, BIT(13) },
+ [RST_BUS_DRAM] = { 0x2c0, BIT(14) },
+ [RST_BUS_EMAC] = { 0x2c0, BIT(17) },
+ [RST_BUS_TS] = { 0x2c0, BIT(18) },
+ [RST_BUS_HSTIMER] = { 0x2c0, BIT(19) },
+ [RST_BUS_SPI0] = { 0x2c0, BIT(20) },
+ [RST_BUS_SPI1] = { 0x2c0, BIT(21) },
+ [RST_BUS_OTG] = { 0x2c0, BIT(23) },
+ [RST_BUS_EHCI0] = { 0x2c0, BIT(24) },
+ [RST_BUS_EHCI1] = { 0x2c0, BIT(25) },
+ [RST_BUS_EHCI2] = { 0x2c0, BIT(26) },
+ [RST_BUS_EHCI3] = { 0x2c0, BIT(27) },
+ [RST_BUS_OHCI0] = { 0x2c0, BIT(28) },
+ [RST_BUS_OHCI1] = { 0x2c0, BIT(29) },
+ [RST_BUS_OHCI2] = { 0x2c0, BIT(30) },
+ [RST_BUS_OHCI3] = { 0x2c0, BIT(31) },
+
+ [RST_BUS_VE] = { 0x2c4, BIT(0) },
+ [RST_BUS_TCON0] = { 0x2c4, BIT(3) },
+ [RST_BUS_TCON1] = { 0x2c4, BIT(4) },
+ [RST_BUS_DEINTERLACE] = { 0x2c4, BIT(5) },
+ [RST_BUS_CSI] = { 0x2c4, BIT(8) },
+ [RST_BUS_TVE] = { 0x2c4, BIT(9) },
+ [RST_BUS_HDMI0] = { 0x2c4, BIT(10) },
+ [RST_BUS_HDMI1] = { 0x2c4, BIT(11) },
+ [RST_BUS_DE] = { 0x2c4, BIT(12) },
+ [RST_BUS_GPU] = { 0x2c4, BIT(20) },
+ [RST_BUS_MSGBOX] = { 0x2c4, BIT(21) },
+ [RST_BUS_SPINLOCK] = { 0x2c4, BIT(22) },
+ [RST_BUS_DBG] = { 0x2c4, BIT(31) },
+
+ [RST_BUS_EPHY] = { 0x2c8, BIT(2) },
+
+ [RST_BUS_CODEC] = { 0x2d0, BIT(0) },
+ [RST_BUS_SPDIF] = { 0x2d0, BIT(1) },
+ [RST_BUS_THS] = { 0x2d0, BIT(8) },
+ [RST_BUS_I2S0] = { 0x2d0, BIT(12) },
+ [RST_BUS_I2S1] = { 0x2d0, BIT(13) },
+ [RST_BUS_I2S2] = { 0x2d0, BIT(14) },
+
+ [RST_BUS_I2C0] = { 0x2d8, BIT(0) },
+ [RST_BUS_I2C1] = { 0x2d8, BIT(1) },
+ [RST_BUS_I2C2] = { 0x2d8, BIT(2) },
+ [RST_BUS_UART0] = { 0x2d8, BIT(16) },
+ [RST_BUS_UART1] = { 0x2d8, BIT(17) },
+ [RST_BUS_UART2] = { 0x2d8, BIT(18) },
+ [RST_BUS_UART3] = { 0x2d8, BIT(19) },
+ [RST_BUS_SCR0] = { 0x2d8, BIT(20) },
+};
+
+static struct ccu_reset_map sun50i_h5_ccu_resets[] = {
[RST_USB_PHY0] = { 0x0cc, BIT(0) },
[RST_USB_PHY1] = { 0x0cc, BIT(1) },
[RST_USB_PHY2] = { 0x0cc, BIT(2) },
@@ -791,6 +973,7 @@ static struct ccu_reset_map sunxi_h3_h5_ccu_resets[] = {
[RST_BUS_UART2] = { 0x2d8, BIT(18) },
[RST_BUS_UART3] = { 0x2d8, BIT(19) },
[RST_BUS_SCR0] = { 0x2d8, BIT(20) },
+ [RST_BUS_SCR1] = { 0x2d8, BIT(21) },
};
static const struct sunxi_ccu_desc sun8i_h3_ccu_desc = {
@@ -799,8 +982,18 @@ static const struct sunxi_ccu_desc sun8i_h3_ccu_desc = {
.hw_clks = &sun8i_h3_hw_clks,
- .resets = sunxi_h3_h5_ccu_resets,
- .num_resets = ARRAY_SIZE(sunxi_h3_h5_ccu_resets),
+ .resets = sun8i_h3_ccu_resets,
+ .num_resets = ARRAY_SIZE(sun8i_h3_ccu_resets),
+};
+
+static const struct sunxi_ccu_desc sun50i_h5_ccu_desc = {
+ .ccu_clks = sunxi_h3_h5_ccu_clks,
+ .num_ccu_clks = ARRAY_SIZE(sunxi_h3_h5_ccu_clks),
+
+ .hw_clks = &sun50i_h5_hw_clks,
+
+ .resets = sun50i_h5_ccu_resets,
+ .num_resets = ARRAY_SIZE(sun50i_h5_ccu_resets),
};
static struct ccu_mux_nb sunxi_h3_h5_cpu_nb = {
@@ -840,3 +1033,10 @@ static void __init sun8i_h3_ccu_setup(struct device_node *node)
}
CLK_OF_DECLARE(sun8i_h3_ccu, "allwinner,sun8i-h3-ccu",
sun8i_h3_ccu_setup);
+
+static void __init sun50i_h5_ccu_setup(struct device_node *node)
+{
+ sunxi_h3_h5_ccu_init(node, &sun50i_h5_ccu_desc);
+}
+CLK_OF_DECLARE(sun50i_h5_ccu, "allwinner,sun50i-h5-ccu",
+ sun50i_h5_ccu_setup);
diff --git a/drivers/clk/sunxi-ng/ccu-sunxi-h3-h5.h b/drivers/clk/sunxi-ng/ccu-sunxi-h3-h5.h
index e2a4656d2cf3..e5a78cc66d6b 100644
--- a/drivers/clk/sunxi-ng/ccu-sunxi-h3-h5.h
+++ b/drivers/clk/sunxi-ng/ccu-sunxi-h3-h5.h
@@ -57,6 +57,9 @@
/* And the GPU module clock is exported */
-#define CLK_NUMBER (CLK_GPU + 1)
+/* New clocks imported in H5 */
+/* The SCR1 bus gate is exported */
+
+#define CLK_NUMBER (CLK_BUS_SCR1 + 1)
#endif /* _CCU_SUNXI_H3_H5_H_ */
diff --git a/include/dt-bindings/clock/sunxi-h3-h5-ccu.h b/include/dt-bindings/clock/sunxi-h3-h5-ccu.h
index 1715a5e12525..4899eacef71d 100644
--- a/include/dt-bindings/clock/sunxi-h3-h5-ccu.h
+++ b/include/dt-bindings/clock/sunxi-h3-h5-ccu.h
@@ -142,4 +142,7 @@
#define CLK_GPU 114
+/* New clocks imported in H5 */
+#define CLK_BUS_SCR1 115
+
#endif /* _DT_BINDINGS_CLK_SUNXI_H3_H5_H_ */
diff --git a/include/dt-bindings/reset/sunxi-h3-h5-ccu.h b/include/dt-bindings/reset/sunxi-h3-h5-ccu.h
index 7a5de896cf1f..1084c157c062 100644
--- a/include/dt-bindings/reset/sunxi-h3-h5-ccu.h
+++ b/include/dt-bindings/reset/sunxi-h3-h5-ccu.h
@@ -100,4 +100,7 @@
#define RST_BUS_UART3 52
#define RST_BUS_SCR0 53
+/* New resets imported in H5 */
+#define RST_BUS_SCR1 54
+
#endif /* _DT_BINDINGS_RST_SUNXI_H3_H5_H_ */
--
2.11.0
^ permalink raw reply related [flat|nested] 13+ messages in thread* [PATCH v4 3/9] clk: sunxi-ng: add support for Allwinner H5 SoC
2017-02-07 18:30 ` [PATCH v4 3/9] clk: sunxi-ng: add support for Allwinner H5 SoC Icenowy Zheng
@ 2017-02-08 8:00 ` Maxime Ripard
0 siblings, 0 replies; 13+ messages in thread
From: Maxime Ripard @ 2017-02-08 8:00 UTC (permalink / raw)
To: linux-arm-kernel
Hi,
On Wed, Feb 08, 2017 at 02:30:36AM +0800, Icenowy Zheng wrote:
> Allwinner H5 is a SoC that features a CCU like H3, but with MMC phase
> clocks removed (for new MMC controller) and a new bus gate/reset
> imported.
>
> Add support for it.
>
> Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
> ---
> Changes since v3:
> - Add a dedicated reset line list for H5, as SCR1 reset is not valid
> on H3.
>
> .../devicetree/bindings/clock/sunxi-ccu.txt | 1 +
> drivers/clk/sunxi-ng/Kconfig | 2 +-
> drivers/clk/sunxi-ng/ccu-sunxi-h3-h5.c | 206 ++++++++++++++++++++-
> drivers/clk/sunxi-ng/ccu-sunxi-h3-h5.h | 5 +-
> include/dt-bindings/clock/sunxi-h3-h5-ccu.h | 3 +
> include/dt-bindings/reset/sunxi-h3-h5-ccu.h | 3 +
> 6 files changed, 215 insertions(+), 5 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/clock/sunxi-ccu.txt b/Documentation/devicetree/bindings/clock/sunxi-ccu.txt
> index bae5668cf427..68512aa398a9 100644
> --- a/Documentation/devicetree/bindings/clock/sunxi-ccu.txt
> +++ b/Documentation/devicetree/bindings/clock/sunxi-ccu.txt
> @@ -10,6 +10,7 @@ Required properties :
> - "allwinner,sun8i-v3s-ccu"
> - "allwinner,sun9i-a80-ccu"
> - "allwinner,sun50i-a64-ccu"
> + - "allwinner,sun50i-h5-ccu"
>
> - reg: Must contain the registers base address and length
> - clocks: phandle to the oscillators feeding the CCU. Two are needed:
> diff --git a/drivers/clk/sunxi-ng/Kconfig b/drivers/clk/sunxi-ng/Kconfig
> index edc5bbbcb5bb..ec3e5f56b6ec 100644
> --- a/drivers/clk/sunxi-ng/Kconfig
> +++ b/drivers/clk/sunxi-ng/Kconfig
> @@ -117,7 +117,7 @@ config SUNXI_H3_H5_CCU
> select SUNXI_CCU_NM
> select SUNXI_CCU_MP
> select SUNXI_CCU_PHASE
> - default MACH_SUN8I
> + default MACH_SUN8I || (ARM64 && ARCH_SUNXI)
>
> config SUN8I_V3S_CCU
> bool "Support for the Allwinner V3s CCU"
> diff --git a/drivers/clk/sunxi-ng/ccu-sunxi-h3-h5.c b/drivers/clk/sunxi-ng/ccu-sunxi-h3-h5.c
> index e2d065973794..360709966e8f 100644
> --- a/drivers/clk/sunxi-ng/ccu-sunxi-h3-h5.c
> +++ b/drivers/clk/sunxi-ng/ccu-sunxi-h3-h5.c
> @@ -302,6 +302,8 @@ static SUNXI_CCU_GATE(bus_uart3_clk, "bus-uart3", "apb2",
> 0x06c, BIT(19), 0);
> static SUNXI_CCU_GATE(bus_scr0_clk, "bus-scr0", "apb2",
> 0x06c, BIT(20), 0);
> +static SUNXI_CCU_GATE(bus_scr1_clk, "bus-scr1", "apb2",
> + 0x06c, BIT(21), 0);
>
> static SUNXI_CCU_GATE(bus_ephy_clk, "bus-ephy", "ahb1",
> 0x070, BIT(0), 0);
> @@ -547,6 +549,7 @@ static struct ccu_common *sunxi_h3_h5_ccu_clks[] = {
> &bus_uart2_clk.common,
> &bus_uart3_clk.common,
> &bus_scr0_clk.common,
> + &bus_scr1_clk.common,
There's only one SCR gate in the H3.
> &bus_ephy_clk.common,
> &bus_dbg_clk.common,
> &ths_clk.common,
> @@ -730,7 +733,186 @@ static struct clk_hw_onecell_data sun8i_h3_hw_clks = {
> .num = CLK_NUMBER,
> };
>
> -static struct ccu_reset_map sunxi_h3_h5_ccu_resets[] = {
> +static struct clk_hw_onecell_data sun50i_h5_hw_clks = {
> + .hws = {
> + [CLK_PLL_CPUX] = &pll_cpux_clk.common.hw,
> + [CLK_PLL_AUDIO_BASE] = &pll_audio_base_clk.common.hw,
> + [CLK_PLL_AUDIO] = &pll_audio_clk.hw,
> + [CLK_PLL_AUDIO_2X] = &pll_audio_2x_clk.hw,
> + [CLK_PLL_AUDIO_4X] = &pll_audio_4x_clk.hw,
> + [CLK_PLL_AUDIO_8X] = &pll_audio_8x_clk.hw,
> + [CLK_PLL_VIDEO] = &pll_video_clk.common.hw,
> + [CLK_PLL_VE] = &pll_ve_clk.common.hw,
> + [CLK_PLL_DDR] = &pll_ddr_clk.common.hw,
> + [CLK_PLL_PERIPH0] = &pll_periph0_clk.common.hw,
> + [CLK_PLL_PERIPH0_2X] = &pll_periph0_2x_clk.hw,
> + [CLK_PLL_GPU] = &pll_gpu_clk.common.hw,
> + [CLK_PLL_PERIPH1] = &pll_periph1_clk.common.hw,
> + [CLK_PLL_DE] = &pll_de_clk.common.hw,
> + [CLK_CPUX] = &cpux_clk.common.hw,
> + [CLK_AXI] = &axi_clk.common.hw,
> + [CLK_AHB1] = &ahb1_clk.common.hw,
> + [CLK_APB1] = &apb1_clk.common.hw,
> + [CLK_APB2] = &apb2_clk.common.hw,
> + [CLK_AHB2] = &ahb2_clk.common.hw,
> + [CLK_BUS_CE] = &bus_ce_clk.common.hw,
> + [CLK_BUS_DMA] = &bus_dma_clk.common.hw,
> + [CLK_BUS_MMC0] = &bus_mmc0_clk.common.hw,
> + [CLK_BUS_MMC1] = &bus_mmc1_clk.common.hw,
> + [CLK_BUS_MMC2] = &bus_mmc2_clk.common.hw,
> + [CLK_BUS_NAND] = &bus_nand_clk.common.hw,
> + [CLK_BUS_DRAM] = &bus_dram_clk.common.hw,
> + [CLK_BUS_EMAC] = &bus_emac_clk.common.hw,
> + [CLK_BUS_TS] = &bus_ts_clk.common.hw,
> + [CLK_BUS_HSTIMER] = &bus_hstimer_clk.common.hw,
> + [CLK_BUS_SPI0] = &bus_spi0_clk.common.hw,
> + [CLK_BUS_SPI1] = &bus_spi1_clk.common.hw,
> + [CLK_BUS_OTG] = &bus_otg_clk.common.hw,
> + [CLK_BUS_EHCI0] = &bus_ehci0_clk.common.hw,
> + [CLK_BUS_EHCI1] = &bus_ehci1_clk.common.hw,
> + [CLK_BUS_EHCI2] = &bus_ehci2_clk.common.hw,
> + [CLK_BUS_EHCI3] = &bus_ehci3_clk.common.hw,
> + [CLK_BUS_OHCI0] = &bus_ohci0_clk.common.hw,
> + [CLK_BUS_OHCI1] = &bus_ohci1_clk.common.hw,
> + [CLK_BUS_OHCI2] = &bus_ohci2_clk.common.hw,
> + [CLK_BUS_OHCI3] = &bus_ohci3_clk.common.hw,
> + [CLK_BUS_VE] = &bus_ve_clk.common.hw,
> + [CLK_BUS_TCON0] = &bus_tcon0_clk.common.hw,
> + [CLK_BUS_TCON1] = &bus_tcon1_clk.common.hw,
> + [CLK_BUS_DEINTERLACE] = &bus_deinterlace_clk.common.hw,
> + [CLK_BUS_CSI] = &bus_csi_clk.common.hw,
> + [CLK_BUS_TVE] = &bus_tve_clk.common.hw,
> + [CLK_BUS_HDMI] = &bus_hdmi_clk.common.hw,
> + [CLK_BUS_DE] = &bus_de_clk.common.hw,
> + [CLK_BUS_GPU] = &bus_gpu_clk.common.hw,
> + [CLK_BUS_MSGBOX] = &bus_msgbox_clk.common.hw,
> + [CLK_BUS_SPINLOCK] = &bus_spinlock_clk.common.hw,
> + [CLK_BUS_CODEC] = &bus_codec_clk.common.hw,
> + [CLK_BUS_SPDIF] = &bus_spdif_clk.common.hw,
> + [CLK_BUS_PIO] = &bus_pio_clk.common.hw,
> + [CLK_BUS_THS] = &bus_ths_clk.common.hw,
> + [CLK_BUS_I2S0] = &bus_i2s0_clk.common.hw,
> + [CLK_BUS_I2S1] = &bus_i2s1_clk.common.hw,
> + [CLK_BUS_I2S2] = &bus_i2s2_clk.common.hw,
> + [CLK_BUS_I2C0] = &bus_i2c0_clk.common.hw,
> + [CLK_BUS_I2C1] = &bus_i2c1_clk.common.hw,
> + [CLK_BUS_I2C2] = &bus_i2c2_clk.common.hw,
> + [CLK_BUS_UART0] = &bus_uart0_clk.common.hw,
> + [CLK_BUS_UART1] = &bus_uart1_clk.common.hw,
> + [CLK_BUS_UART2] = &bus_uart2_clk.common.hw,
> + [CLK_BUS_UART3] = &bus_uart3_clk.common.hw,
> + [CLK_BUS_SCR0] = &bus_scr0_clk.common.hw,
> + [CLK_BUS_SCR1] = &bus_scr1_clk.common.hw,
> + [CLK_BUS_EPHY] = &bus_ephy_clk.common.hw,
> + [CLK_BUS_DBG] = &bus_dbg_clk.common.hw,
> + [CLK_THS] = &ths_clk.common.hw,
> + [CLK_NAND] = &nand_clk.common.hw,
> + [CLK_MMC0] = &mmc0_clk.common.hw,
> + [CLK_MMC1] = &mmc1_clk.common.hw,
> + [CLK_MMC2] = &mmc2_clk.common.hw,
> + [CLK_TS] = &ts_clk.common.hw,
> + [CLK_CE] = &ce_clk.common.hw,
> + [CLK_SPI0] = &spi0_clk.common.hw,
> + [CLK_SPI1] = &spi1_clk.common.hw,
> + [CLK_I2S0] = &i2s0_clk.common.hw,
> + [CLK_I2S1] = &i2s1_clk.common.hw,
> + [CLK_I2S2] = &i2s2_clk.common.hw,
> + [CLK_SPDIF] = &spdif_clk.common.hw,
> + [CLK_USB_PHY0] = &usb_phy0_clk.common.hw,
> + [CLK_USB_PHY1] = &usb_phy1_clk.common.hw,
> + [CLK_USB_PHY2] = &usb_phy2_clk.common.hw,
> + [CLK_USB_PHY3] = &usb_phy3_clk.common.hw,
> + [CLK_USB_OHCI0] = &usb_ohci0_clk.common.hw,
> + [CLK_USB_OHCI1] = &usb_ohci1_clk.common.hw,
> + [CLK_USB_OHCI2] = &usb_ohci2_clk.common.hw,
> + [CLK_USB_OHCI3] = &usb_ohci3_clk.common.hw,
> + [CLK_DRAM] = &dram_clk.common.hw,
> + [CLK_DRAM_VE] = &dram_ve_clk.common.hw,
> + [CLK_DRAM_CSI] = &dram_csi_clk.common.hw,
> + [CLK_DRAM_DEINTERLACE] = &dram_deinterlace_clk.common.hw,
> + [CLK_DRAM_TS] = &dram_ts_clk.common.hw,
> + [CLK_DE] = &de_clk.common.hw,
> + [CLK_TCON0] = &tcon_clk.common.hw,
> + [CLK_TVE] = &tve_clk.common.hw,
> + [CLK_DEINTERLACE] = &deinterlace_clk.common.hw,
> + [CLK_CSI_MISC] = &csi_misc_clk.common.hw,
> + [CLK_CSI_SCLK] = &csi_sclk_clk.common.hw,
> + [CLK_CSI_MCLK] = &csi_mclk_clk.common.hw,
> + [CLK_VE] = &ve_clk.common.hw,
> + [CLK_AC_DIG] = &ac_dig_clk.common.hw,
> + [CLK_AVS] = &avs_clk.common.hw,
> + [CLK_HDMI] = &hdmi_clk.common.hw,
> + [CLK_HDMI_DDC] = &hdmi_ddc_clk.common.hw,
> + [CLK_MBUS] = &mbus_clk.common.hw,
> + [CLK_GPU] = &gpu_clk.common.hw,
> + },
> + .num = CLK_NUMBER,
> +};
> +
> +static struct ccu_reset_map sun8i_h3_ccu_resets[] = {
> + [RST_USB_PHY0] = { 0x0cc, BIT(0) },
> + [RST_USB_PHY1] = { 0x0cc, BIT(1) },
> + [RST_USB_PHY2] = { 0x0cc, BIT(2) },
> + [RST_USB_PHY3] = { 0x0cc, BIT(3) },
> +
> + [RST_MBUS] = { 0x0fc, BIT(31) },
> +
> + [RST_BUS_CE] = { 0x2c0, BIT(5) },
> + [RST_BUS_DMA] = { 0x2c0, BIT(6) },
> + [RST_BUS_MMC0] = { 0x2c0, BIT(8) },
> + [RST_BUS_MMC1] = { 0x2c0, BIT(9) },
> + [RST_BUS_MMC2] = { 0x2c0, BIT(10) },
> + [RST_BUS_NAND] = { 0x2c0, BIT(13) },
> + [RST_BUS_DRAM] = { 0x2c0, BIT(14) },
> + [RST_BUS_EMAC] = { 0x2c0, BIT(17) },
> + [RST_BUS_TS] = { 0x2c0, BIT(18) },
> + [RST_BUS_HSTIMER] = { 0x2c0, BIT(19) },
> + [RST_BUS_SPI0] = { 0x2c0, BIT(20) },
> + [RST_BUS_SPI1] = { 0x2c0, BIT(21) },
> + [RST_BUS_OTG] = { 0x2c0, BIT(23) },
> + [RST_BUS_EHCI0] = { 0x2c0, BIT(24) },
> + [RST_BUS_EHCI1] = { 0x2c0, BIT(25) },
> + [RST_BUS_EHCI2] = { 0x2c0, BIT(26) },
> + [RST_BUS_EHCI3] = { 0x2c0, BIT(27) },
> + [RST_BUS_OHCI0] = { 0x2c0, BIT(28) },
> + [RST_BUS_OHCI1] = { 0x2c0, BIT(29) },
> + [RST_BUS_OHCI2] = { 0x2c0, BIT(30) },
> + [RST_BUS_OHCI3] = { 0x2c0, BIT(31) },
> +
> + [RST_BUS_VE] = { 0x2c4, BIT(0) },
> + [RST_BUS_TCON0] = { 0x2c4, BIT(3) },
> + [RST_BUS_TCON1] = { 0x2c4, BIT(4) },
> + [RST_BUS_DEINTERLACE] = { 0x2c4, BIT(5) },
> + [RST_BUS_CSI] = { 0x2c4, BIT(8) },
> + [RST_BUS_TVE] = { 0x2c4, BIT(9) },
> + [RST_BUS_HDMI0] = { 0x2c4, BIT(10) },
> + [RST_BUS_HDMI1] = { 0x2c4, BIT(11) },
> + [RST_BUS_DE] = { 0x2c4, BIT(12) },
> + [RST_BUS_GPU] = { 0x2c4, BIT(20) },
> + [RST_BUS_MSGBOX] = { 0x2c4, BIT(21) },
> + [RST_BUS_SPINLOCK] = { 0x2c4, BIT(22) },
> + [RST_BUS_DBG] = { 0x2c4, BIT(31) },
> +
> + [RST_BUS_EPHY] = { 0x2c8, BIT(2) },
> +
> + [RST_BUS_CODEC] = { 0x2d0, BIT(0) },
> + [RST_BUS_SPDIF] = { 0x2d0, BIT(1) },
> + [RST_BUS_THS] = { 0x2d0, BIT(8) },
> + [RST_BUS_I2S0] = { 0x2d0, BIT(12) },
> + [RST_BUS_I2S1] = { 0x2d0, BIT(13) },
> + [RST_BUS_I2S2] = { 0x2d0, BIT(14) },
> +
> + [RST_BUS_I2C0] = { 0x2d8, BIT(0) },
> + [RST_BUS_I2C1] = { 0x2d8, BIT(1) },
> + [RST_BUS_I2C2] = { 0x2d8, BIT(2) },
> + [RST_BUS_UART0] = { 0x2d8, BIT(16) },
> + [RST_BUS_UART1] = { 0x2d8, BIT(17) },
> + [RST_BUS_UART2] = { 0x2d8, BIT(18) },
> + [RST_BUS_UART3] = { 0x2d8, BIT(19) },
> + [RST_BUS_SCR0] = { 0x2d8, BIT(20) },
> +};
> +
> +static struct ccu_reset_map sun50i_h5_ccu_resets[] = {
> [RST_USB_PHY0] = { 0x0cc, BIT(0) },
> [RST_USB_PHY1] = { 0x0cc, BIT(1) },
> [RST_USB_PHY2] = { 0x0cc, BIT(2) },
> @@ -791,6 +973,7 @@ static struct ccu_reset_map sunxi_h3_h5_ccu_resets[] = {
> [RST_BUS_UART2] = { 0x2d8, BIT(18) },
> [RST_BUS_UART3] = { 0x2d8, BIT(19) },
> [RST_BUS_SCR0] = { 0x2d8, BIT(20) },
> + [RST_BUS_SCR1] = { 0x2d8, BIT(21) },
> };
>
> static const struct sunxi_ccu_desc sun8i_h3_ccu_desc = {
> @@ -799,8 +982,18 @@ static const struct sunxi_ccu_desc sun8i_h3_ccu_desc = {
>
> .hw_clks = &sun8i_h3_hw_clks,
>
> - .resets = sunxi_h3_h5_ccu_resets,
> - .num_resets = ARRAY_SIZE(sunxi_h3_h5_ccu_resets),
> + .resets = sun8i_h3_ccu_resets,
> + .num_resets = ARRAY_SIZE(sun8i_h3_ccu_resets),
> +};
> +
> +static const struct sunxi_ccu_desc sun50i_h5_ccu_desc = {
> + .ccu_clks = sunxi_h3_h5_ccu_clks,
> + .num_ccu_clks = ARRAY_SIZE(sunxi_h3_h5_ccu_clks),
> +
> + .hw_clks = &sun50i_h5_hw_clks,
> +
> + .resets = sun50i_h5_ccu_resets,
> + .num_resets = ARRAY_SIZE(sun50i_h5_ccu_resets),
> };
>
> static struct ccu_mux_nb sunxi_h3_h5_cpu_nb = {
> @@ -840,3 +1033,10 @@ static void __init sun8i_h3_ccu_setup(struct device_node *node)
> }
> CLK_OF_DECLARE(sun8i_h3_ccu, "allwinner,sun8i-h3-ccu",
> sun8i_h3_ccu_setup);
> +
> +static void __init sun50i_h5_ccu_setup(struct device_node *node)
> +{
> + sunxi_h3_h5_ccu_init(node, &sun50i_h5_ccu_desc);
> +}
> +CLK_OF_DECLARE(sun50i_h5_ccu, "allwinner,sun50i-h5-ccu",
> + sun50i_h5_ccu_setup);
> diff --git a/drivers/clk/sunxi-ng/ccu-sunxi-h3-h5.h b/drivers/clk/sunxi-ng/ccu-sunxi-h3-h5.h
> index e2a4656d2cf3..e5a78cc66d6b 100644
> --- a/drivers/clk/sunxi-ng/ccu-sunxi-h3-h5.h
> +++ b/drivers/clk/sunxi-ng/ccu-sunxi-h3-h5.h
> @@ -57,6 +57,9 @@
>
> /* And the GPU module clock is exported */
>
> -#define CLK_NUMBER (CLK_GPU + 1)
> +/* New clocks imported in H5 */
H5 clocks seems more natural, and you don't have to put it twice.
> +/* The SCR1 bus gate is exported */
> +
> +#define CLK_NUMBER (CLK_BUS_SCR1 + 1)
This introduces an off-by-one error on the H3
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 801 bytes
Desc: not available
URL: <http://lists.infradead.org/pipermail/linux-arm-kernel/attachments/20170208/c9ae8cab/attachment.sig>
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH v4 4/9] ARM: dts: sun8i: convert H3 dtsi to use new sunxi-h3-h5 binding header
2017-02-07 18:30 [PATCH v4 0/9] Allwinner H5 and Orange Pi PC2 support Icenowy Zheng
` (2 preceding siblings ...)
2017-02-07 18:30 ` [PATCH v4 3/9] clk: sunxi-ng: add support for Allwinner H5 SoC Icenowy Zheng
@ 2017-02-07 18:30 ` Icenowy Zheng
2017-02-07 18:30 ` [PATCH v4 5/9] dt-bindings: remove transitional headers for Allwinner H3 CCU Icenowy Zheng
` (4 subsequent siblings)
8 siblings, 0 replies; 13+ messages in thread
From: Icenowy Zheng @ 2017-02-07 18:30 UTC (permalink / raw)
To: linux-arm-kernel
As part of the process that adds H5 support to the original H3 CCU
driver, the device tree binding header changed its name.
Convert the H3 DTSI to use the new binding header.
The only names for H3 changed are {CLK,RST}_BUS_SCR to
{CLK,RST}_BUS_SCR0, not currently used now; so only the header
file's name is changed.
Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
---
New patch in v4.
arch/arm/boot/dts/sun8i-h3.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi
index 48f9a0419b82..735e9cef334f 100644
--- a/arch/arm/boot/dts/sun8i-h3.dtsi
+++ b/arch/arm/boot/dts/sun8i-h3.dtsi
@@ -42,10 +42,10 @@
#include "skeleton.dtsi"
-#include <dt-bindings/clock/sun8i-h3-ccu.h>
+#include <dt-bindings/clock/sunxi-h3-h5-ccu.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/pinctrl/sun4i-a10.h>
-#include <dt-bindings/reset/sun8i-h3-ccu.h>
+#include <dt-bindings/reset/sunxi-h3-h5-ccu.h>
/ {
interrupt-parent = <&gic>;
--
2.11.0
^ permalink raw reply related [flat|nested] 13+ messages in thread* [PATCH v4 5/9] dt-bindings: remove transitional headers for Allwinner H3 CCU
2017-02-07 18:30 [PATCH v4 0/9] Allwinner H5 and Orange Pi PC2 support Icenowy Zheng
` (3 preceding siblings ...)
2017-02-07 18:30 ` [PATCH v4 4/9] ARM: dts: sun8i: convert H3 dtsi to use new sunxi-h3-h5 binding header Icenowy Zheng
@ 2017-02-07 18:30 ` Icenowy Zheng
2017-02-08 8:00 ` Maxime Ripard
2017-02-07 18:30 ` [PATCH v4 6/9] arm: dts: sun8i: split Allwinner H3 .dtsi Icenowy Zheng
` (3 subsequent siblings)
8 siblings, 1 reply; 13+ messages in thread
From: Icenowy Zheng @ 2017-02-07 18:30 UTC (permalink / raw)
To: linux-arm-kernel
As we have already changed the DTSI file, the trnasitional dt-bindings
header sun8i-h3-ccu.h for clock and reset will not be needed any more.
Remove them.
Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
---
include/dt-bindings/clock/sun8i-h3-ccu.h | 1 -
include/dt-bindings/reset/sun8i-h3-ccu.h | 1 -
2 files changed, 2 deletions(-)
delete mode 120000 include/dt-bindings/clock/sun8i-h3-ccu.h
delete mode 120000 include/dt-bindings/reset/sun8i-h3-ccu.h
diff --git a/include/dt-bindings/clock/sun8i-h3-ccu.h b/include/dt-bindings/clock/sun8i-h3-ccu.h
deleted file mode 120000
index ef38232141e4..000000000000
--- a/include/dt-bindings/clock/sun8i-h3-ccu.h
+++ /dev/null
@@ -1 +0,0 @@
-sunxi-h3-h5-ccu.h
\ No newline at end of file
diff --git a/include/dt-bindings/reset/sun8i-h3-ccu.h b/include/dt-bindings/reset/sun8i-h3-ccu.h
deleted file mode 120000
index ef38232141e4..000000000000
--- a/include/dt-bindings/reset/sun8i-h3-ccu.h
+++ /dev/null
@@ -1 +0,0 @@
-sunxi-h3-h5-ccu.h
\ No newline at end of file
--
2.11.0
^ permalink raw reply related [flat|nested] 13+ messages in thread* [PATCH v4 6/9] arm: dts: sun8i: split Allwinner H3 .dtsi
2017-02-07 18:30 [PATCH v4 0/9] Allwinner H5 and Orange Pi PC2 support Icenowy Zheng
` (4 preceding siblings ...)
2017-02-07 18:30 ` [PATCH v4 5/9] dt-bindings: remove transitional headers for Allwinner H3 CCU Icenowy Zheng
@ 2017-02-07 18:30 ` Icenowy Zheng
2017-02-07 18:30 ` [PATCH v4 7/9] ASoC: sunxi: allow the analog codec driver to be built on ARM64 Icenowy Zheng
` (2 subsequent siblings)
8 siblings, 0 replies; 13+ messages in thread
From: Icenowy Zheng @ 2017-02-07 18:30 UTC (permalink / raw)
To: linux-arm-kernel
From: Andre Przywara <andre.przywara@arm.com>
The new Allwinner H5 SoC is pin-compatible to the H3 SoC, but with the
Cortex-A7 cores replaced by Cortex-A53 cores and the MMC controller
updated. So we should really share almost the whole .dtsi.
In preparation for that move the peripheral parts of the existing
sun8i-h3.dtsi into a new sun8i-h3-h5.dtsi.
The actual sun8i-h3.dtsi then includes that and defines the H3 specific
parts on top of it.
On the way get rid of skeleton.dtsi, as recommended in that very file.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
[Icenowy: also split out mmc, as well as pio and ccu's compatible]
Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
---
Changes in v3:
- Use label-based syntax to reference nodes in H3 DTSI file.
Changes in v2:
- Rebase on current linux-next (because of the add of audio codec)
arch/arm/boot/dts/sun8i-h3.dtsi | 789 ++++-----------------
.../boot/dts/{sun8i-h3.dtsi => sunxi-h3-h5.dtsi} | 87 +--
2 files changed, 148 insertions(+), 728 deletions(-)
rewrite arch/arm/boot/dts/sun8i-h3.dtsi (81%)
copy arch/arm/boot/dts/{sun8i-h3.dtsi => sunxi-h3-h5.dtsi} (88%)
diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi
dissimilarity index 81%
index 735e9cef334f..f3a3033789b9 100644
--- a/arch/arm/boot/dts/sun8i-h3.dtsi
+++ b/arch/arm/boot/dts/sun8i-h3.dtsi
@@ -1,648 +1,141 @@
-/*
- * Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
-
-#include "skeleton.dtsi"
-
-#include <dt-bindings/clock/sunxi-h3-h5-ccu.h>
-#include <dt-bindings/interrupt-controller/arm-gic.h>
-#include <dt-bindings/pinctrl/sun4i-a10.h>
-#include <dt-bindings/reset/sunxi-h3-h5-ccu.h>
-
-/ {
- interrupt-parent = <&gic>;
-
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
-
- cpu at 0 {
- compatible = "arm,cortex-a7";
- device_type = "cpu";
- reg = <0>;
- };
-
- cpu at 1 {
- compatible = "arm,cortex-a7";
- device_type = "cpu";
- reg = <1>;
- };
-
- cpu at 2 {
- compatible = "arm,cortex-a7";
- device_type = "cpu";
- reg = <2>;
- };
-
- cpu at 3 {
- compatible = "arm,cortex-a7";
- device_type = "cpu";
- reg = <3>;
- };
- };
-
- timer {
- compatible = "arm,armv7-timer";
- interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
- };
-
- clocks {
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- osc24M: osc24M_clk {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <24000000>;
- clock-output-names = "osc24M";
- };
-
- osc32k: osc32k_clk {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <32768>;
- clock-output-names = "osc32k";
- };
-
- apb0: apb0_clk {
- compatible = "fixed-factor-clock";
- #clock-cells = <0>;
- clock-div = <1>;
- clock-mult = <1>;
- clocks = <&osc24M>;
- clock-output-names = "apb0";
- };
-
- apb0_gates: clk at 01f01428 {
- compatible = "allwinner,sun8i-h3-apb0-gates-clk",
- "allwinner,sun4i-a10-gates-clk";
- reg = <0x01f01428 0x4>;
- #clock-cells = <1>;
- clocks = <&apb0>;
- clock-indices = <0>, <1>;
- clock-output-names = "apb0_pio", "apb0_ir";
- };
-
- ir_clk: ir_clk at 01f01454 {
- compatible = "allwinner,sun4i-a10-mod0-clk";
- reg = <0x01f01454 0x4>;
- #clock-cells = <0>;
- clocks = <&osc32k>, <&osc24M>;
- clock-output-names = "ir";
- };
- };
-
- soc {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- dma: dma-controller at 01c02000 {
- compatible = "allwinner,sun8i-h3-dma";
- reg = <0x01c02000 0x1000>;
- interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&ccu CLK_BUS_DMA>;
- resets = <&ccu RST_BUS_DMA>;
- #dma-cells = <1>;
- };
-
- mmc0: mmc at 01c0f000 {
- compatible = "allwinner,sun7i-a20-mmc";
- reg = <0x01c0f000 0x1000>;
- clocks = <&ccu CLK_BUS_MMC0>,
- <&ccu CLK_MMC0>,
- <&ccu CLK_MMC0_OUTPUT>,
- <&ccu CLK_MMC0_SAMPLE>;
- clock-names = "ahb",
- "mmc",
- "output",
- "sample";
- resets = <&ccu RST_BUS_MMC0>;
- reset-names = "ahb";
- interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
- status = "disabled";
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- mmc1: mmc at 01c10000 {
- compatible = "allwinner,sun7i-a20-mmc";
- reg = <0x01c10000 0x1000>;
- clocks = <&ccu CLK_BUS_MMC1>,
- <&ccu CLK_MMC1>,
- <&ccu CLK_MMC1_OUTPUT>,
- <&ccu CLK_MMC1_SAMPLE>;
- clock-names = "ahb",
- "mmc",
- "output",
- "sample";
- resets = <&ccu RST_BUS_MMC1>;
- reset-names = "ahb";
- interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
- status = "disabled";
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- mmc2: mmc at 01c11000 {
- compatible = "allwinner,sun7i-a20-mmc";
- reg = <0x01c11000 0x1000>;
- clocks = <&ccu CLK_BUS_MMC2>,
- <&ccu CLK_MMC2>,
- <&ccu CLK_MMC2_OUTPUT>,
- <&ccu CLK_MMC2_SAMPLE>;
- clock-names = "ahb",
- "mmc",
- "output",
- "sample";
- resets = <&ccu RST_BUS_MMC2>;
- reset-names = "ahb";
- interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
- status = "disabled";
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- usbphy: phy at 01c19400 {
- compatible = "allwinner,sun8i-h3-usb-phy";
- reg = <0x01c19400 0x2c>,
- <0x01c1a800 0x4>,
- <0x01c1b800 0x4>,
- <0x01c1c800 0x4>,
- <0x01c1d800 0x4>;
- reg-names = "phy_ctrl",
- "pmu0",
- "pmu1",
- "pmu2",
- "pmu3";
- clocks = <&ccu CLK_USB_PHY0>,
- <&ccu CLK_USB_PHY1>,
- <&ccu CLK_USB_PHY2>,
- <&ccu CLK_USB_PHY3>;
- clock-names = "usb0_phy",
- "usb1_phy",
- "usb2_phy",
- "usb3_phy";
- resets = <&ccu RST_USB_PHY0>,
- <&ccu RST_USB_PHY1>,
- <&ccu RST_USB_PHY2>,
- <&ccu RST_USB_PHY3>;
- reset-names = "usb0_reset",
- "usb1_reset",
- "usb2_reset",
- "usb3_reset";
- status = "disabled";
- #phy-cells = <1>;
- };
-
- ehci1: usb at 01c1b000 {
- compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
- reg = <0x01c1b000 0x100>;
- interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&ccu CLK_BUS_EHCI1>, <&ccu CLK_BUS_OHCI1>;
- resets = <&ccu RST_BUS_EHCI1>, <&ccu RST_BUS_OHCI1>;
- phys = <&usbphy 1>;
- phy-names = "usb";
- status = "disabled";
- };
-
- ohci1: usb at 01c1b400 {
- compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
- reg = <0x01c1b400 0x100>;
- interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&ccu CLK_BUS_EHCI1>, <&ccu CLK_BUS_OHCI1>,
- <&ccu CLK_USB_OHCI1>;
- resets = <&ccu RST_BUS_EHCI1>, <&ccu RST_BUS_OHCI1>;
- phys = <&usbphy 1>;
- phy-names = "usb";
- status = "disabled";
- };
-
- ehci2: usb at 01c1c000 {
- compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
- reg = <0x01c1c000 0x100>;
- interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&ccu CLK_BUS_EHCI2>, <&ccu CLK_BUS_OHCI2>;
- resets = <&ccu RST_BUS_EHCI2>, <&ccu RST_BUS_OHCI2>;
- phys = <&usbphy 2>;
- phy-names = "usb";
- status = "disabled";
- };
-
- ohci2: usb at 01c1c400 {
- compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
- reg = <0x01c1c400 0x100>;
- interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&ccu CLK_BUS_EHCI2>, <&ccu CLK_BUS_OHCI2>,
- <&ccu CLK_USB_OHCI2>;
- resets = <&ccu RST_BUS_EHCI2>, <&ccu RST_BUS_OHCI2>;
- phys = <&usbphy 2>;
- phy-names = "usb";
- status = "disabled";
- };
-
- ehci3: usb at 01c1d000 {
- compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
- reg = <0x01c1d000 0x100>;
- interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&ccu CLK_BUS_EHCI3>, <&ccu CLK_BUS_OHCI3>;
- resets = <&ccu RST_BUS_EHCI3>, <&ccu RST_BUS_OHCI3>;
- phys = <&usbphy 3>;
- phy-names = "usb";
- status = "disabled";
- };
-
- ohci3: usb at 01c1d400 {
- compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
- reg = <0x01c1d400 0x100>;
- interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&ccu CLK_BUS_EHCI3>, <&ccu CLK_BUS_OHCI3>,
- <&ccu CLK_USB_OHCI3>;
- resets = <&ccu RST_BUS_EHCI3>, <&ccu RST_BUS_OHCI3>;
- phys = <&usbphy 3>;
- phy-names = "usb";
- status = "disabled";
- };
-
- ccu: clock at 01c20000 {
- compatible = "allwinner,sun8i-h3-ccu";
- reg = <0x01c20000 0x400>;
- clocks = <&osc24M>, <&osc32k>;
- clock-names = "hosc", "losc";
- #clock-cells = <1>;
- #reset-cells = <1>;
- };
-
- pio: pinctrl at 01c20800 {
- compatible = "allwinner,sun8i-h3-pinctrl";
- reg = <0x01c20800 0x400>;
- interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc32k>;
- clock-names = "apb", "hosc", "losc";
- gpio-controller;
- #gpio-cells = <3>;
- interrupt-controller;
- #interrupt-cells = <3>;
-
- i2c0_pins: i2c0 {
- pins = "PA11", "PA12";
- function = "i2c0";
- };
-
- i2c1_pins: i2c1 {
- pins = "PA18", "PA19";
- function = "i2c1";
- };
-
- i2c2_pins: i2c2 {
- pins = "PE12", "PE13";
- function = "i2c2";
- };
-
- mmc0_pins_a: mmc0 at 0 {
- pins = "PF0", "PF1", "PF2", "PF3",
- "PF4", "PF5";
- function = "mmc0";
- drive-strength = <30>;
- bias-pull-up;
- };
-
- mmc0_cd_pin: mmc0_cd_pin at 0 {
- pins = "PF6";
- function = "gpio_in";
- bias-pull-up;
- };
-
- mmc1_pins_a: mmc1 at 0 {
- pins = "PG0", "PG1", "PG2", "PG3",
- "PG4", "PG5";
- function = "mmc1";
- drive-strength = <30>;
- bias-pull-up;
- };
-
- mmc2_8bit_pins: mmc2_8bit {
- pins = "PC5", "PC6", "PC8",
- "PC9", "PC10", "PC11",
- "PC12", "PC13", "PC14",
- "PC15", "PC16";
- function = "mmc2";
- drive-strength = <30>;
- bias-pull-up;
- };
-
- spdif_tx_pins_a: spdif at 0 {
- pins = "PA17";
- function = "spdif";
- };
-
- spi0_pins: spi0 {
- pins = "PC0", "PC1", "PC2", "PC3";
- function = "spi0";
- };
-
- spi1_pins: spi1 {
- pins = "PA15", "PA16", "PA14", "PA13";
- function = "spi1";
- };
-
- uart0_pins_a: uart0 at 0 {
- pins = "PA4", "PA5";
- function = "uart0";
- };
-
- uart1_pins: uart1 {
- pins = "PG6", "PG7";
- function = "uart1";
- };
-
- uart1_rts_cts_pins: uart1_rts_cts {
- pins = "PG8", "PG9";
- function = "uart1";
- };
-
- uart2_pins: uart2 {
- pins = "PA0", "PA1";
- function = "uart2";
- };
-
- uart3_pins: uart3 {
- pins = "PA13", "PA14";
- function = "uart3";
- };
- };
-
- timer at 01c20c00 {
- compatible = "allwinner,sun4i-a10-timer";
- reg = <0x01c20c00 0xa0>;
- interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&osc24M>;
- };
-
- spi0: spi at 01c68000 {
- compatible = "allwinner,sun8i-h3-spi";
- reg = <0x01c68000 0x1000>;
- interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
- clock-names = "ahb", "mod";
- dmas = <&dma 23>, <&dma 23>;
- dma-names = "rx", "tx";
- pinctrl-names = "default";
- pinctrl-0 = <&spi0_pins>;
- resets = <&ccu RST_BUS_SPI0>;
- status = "disabled";
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- spi1: spi at 01c69000 {
- compatible = "allwinner,sun8i-h3-spi";
- reg = <0x01c69000 0x1000>;
- interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>;
- clock-names = "ahb", "mod";
- dmas = <&dma 24>, <&dma 24>;
- dma-names = "rx", "tx";
- pinctrl-names = "default";
- pinctrl-0 = <&spi1_pins>;
- resets = <&ccu RST_BUS_SPI1>;
- status = "disabled";
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- wdt0: watchdog at 01c20ca0 {
- compatible = "allwinner,sun6i-a31-wdt";
- reg = <0x01c20ca0 0x20>;
- interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
- };
-
- spdif: spdif at 01c21000 {
- #sound-dai-cells = <0>;
- compatible = "allwinner,sun8i-h3-spdif";
- reg = <0x01c21000 0x400>;
- interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>;
- resets = <&ccu RST_BUS_SPDIF>;
- clock-names = "apb", "spdif";
- dmas = <&dma 2>;
- dma-names = "tx";
- status = "disabled";
- };
-
- pwm: pwm at 01c21400 {
- compatible = "allwinner,sun8i-h3-pwm";
- reg = <0x01c21400 0x8>;
- clocks = <&osc24M>;
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- codec: codec at 01c22c00 {
- #sound-dai-cells = <0>;
- compatible = "allwinner,sun8i-h3-codec";
- reg = <0x01c22c00 0x400>;
- interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>;
- clock-names = "apb", "codec";
- resets = <&ccu RST_BUS_CODEC>;
- dmas = <&dma 15>, <&dma 15>;
- dma-names = "rx", "tx";
- allwinner,codec-analog-controls = <&codec_analog>;
- status = "disabled";
- };
-
- uart0: serial at 01c28000 {
- compatible = "snps,dw-apb-uart";
- reg = <0x01c28000 0x400>;
- interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
- reg-shift = <2>;
- reg-io-width = <4>;
- clocks = <&ccu CLK_BUS_UART0>;
- resets = <&ccu RST_BUS_UART0>;
- dmas = <&dma 6>, <&dma 6>;
- dma-names = "rx", "tx";
- status = "disabled";
- };
-
- uart1: serial at 01c28400 {
- compatible = "snps,dw-apb-uart";
- reg = <0x01c28400 0x400>;
- interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
- reg-shift = <2>;
- reg-io-width = <4>;
- clocks = <&ccu CLK_BUS_UART1>;
- resets = <&ccu RST_BUS_UART1>;
- dmas = <&dma 7>, <&dma 7>;
- dma-names = "rx", "tx";
- status = "disabled";
- };
-
- uart2: serial at 01c28800 {
- compatible = "snps,dw-apb-uart";
- reg = <0x01c28800 0x400>;
- interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
- reg-shift = <2>;
- reg-io-width = <4>;
- clocks = <&ccu CLK_BUS_UART2>;
- resets = <&ccu RST_BUS_UART2>;
- dmas = <&dma 8>, <&dma 8>;
- dma-names = "rx", "tx";
- status = "disabled";
- };
-
- uart3: serial at 01c28c00 {
- compatible = "snps,dw-apb-uart";
- reg = <0x01c28c00 0x400>;
- interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
- reg-shift = <2>;
- reg-io-width = <4>;
- clocks = <&ccu CLK_BUS_UART3>;
- resets = <&ccu RST_BUS_UART3>;
- dmas = <&dma 9>, <&dma 9>;
- dma-names = "rx", "tx";
- status = "disabled";
- };
-
- i2c0: i2c at 01c2ac00 {
- compatible = "allwinner,sun6i-a31-i2c";
- reg = <0x01c2ac00 0x400>;
- interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&ccu CLK_BUS_I2C0>;
- resets = <&ccu RST_BUS_I2C0>;
- pinctrl-names = "default";
- pinctrl-0 = <&i2c0_pins>;
- status = "disabled";
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- i2c1: i2c at 01c2b000 {
- compatible = "allwinner,sun6i-a31-i2c";
- reg = <0x01c2b000 0x400>;
- interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&ccu CLK_BUS_I2C1>;
- resets = <&ccu RST_BUS_I2C1>;
- pinctrl-names = "default";
- pinctrl-0 = <&i2c1_pins>;
- status = "disabled";
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- i2c2: i2c at 01c2b400 {
- compatible = "allwinner,sun6i-a31-i2c";
- reg = <0x01c2b000 0x400>;
- interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&ccu CLK_BUS_I2C2>;
- resets = <&ccu RST_BUS_I2C2>;
- pinctrl-names = "default";
- pinctrl-0 = <&i2c2_pins>;
- status = "disabled";
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- gic: interrupt-controller at 01c81000 {
- compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
- reg = <0x01c81000 0x1000>,
- <0x01c82000 0x1000>,
- <0x01c84000 0x2000>,
- <0x01c86000 0x2000>;
- interrupt-controller;
- #interrupt-cells = <3>;
- interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
- };
-
- rtc: rtc at 01f00000 {
- compatible = "allwinner,sun6i-a31-rtc";
- reg = <0x01f00000 0x54>;
- interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
- };
-
- apb0_reset: reset at 01f014b0 {
- reg = <0x01f014b0 0x4>;
- compatible = "allwinner,sun6i-a31-clock-reset";
- #reset-cells = <1>;
- };
-
- codec_analog: codec-analog at 01f015c0 {
- compatible = "allwinner,sun8i-h3-codec-analog";
- reg = <0x01f015c0 0x4>;
- };
-
- ir: ir at 01f02000 {
- compatible = "allwinner,sun5i-a13-ir";
- clocks = <&apb0_gates 1>, <&ir_clk>;
- clock-names = "apb", "ir";
- resets = <&apb0_reset 1>;
- interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
- reg = <0x01f02000 0x40>;
- status = "disabled";
- };
-
- r_pio: pinctrl at 01f02c00 {
- compatible = "allwinner,sun8i-h3-r-pinctrl";
- reg = <0x01f02c00 0x400>;
- interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&apb0_gates 0>, <&osc24M>, <&osc32k>;
- clock-names = "apb", "hosc", "losc";
- resets = <&apb0_reset 0>;
- gpio-controller;
- #gpio-cells = <3>;
- interrupt-controller;
- #interrupt-cells = <3>;
-
- ir_pins_a: ir at 0 {
- pins = "PL11";
- function = "s_cir_rx";
- };
- };
- };
-};
+/*
+ * Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include "sunxi-h3-h5.dtsi"
+
+/ {
+ interrupt-parent = <&gic>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu at 0 {
+ compatible = "arm,cortex-a7";
+ device_type = "cpu";
+ reg = <0>;
+ };
+
+ cpu at 1 {
+ compatible = "arm,cortex-a7";
+ device_type = "cpu";
+ reg = <1>;
+ };
+
+ cpu at 2 {
+ compatible = "arm,cortex-a7";
+ device_type = "cpu";
+ reg = <2>;
+ };
+
+ cpu at 3 {
+ compatible = "arm,cortex-a7";
+ device_type = "cpu";
+ reg = <3>;
+ };
+ };
+
+ timer {
+ compatible = "arm,armv7-timer";
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+ };
+
+ soc {
+ gic: interrupt-controller at 01c81000 {
+ compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
+ reg = <0x01c81000 0x1000>,
+ <0x01c82000 0x1000>,
+ <0x01c84000 0x2000>,
+ <0x01c86000 0x2000>;
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+ };
+ };
+};
+
+&ccu {
+ compatible = "allwinner,sun8i-h3-ccu";
+};
+
+&mmc0 {
+ compatible = "allwinner,sun7i-a20-mmc";
+ clocks = <&ccu CLK_BUS_MMC0>,
+ <&ccu CLK_MMC0>,
+ <&ccu CLK_MMC0_OUTPUT>,
+ <&ccu CLK_MMC0_SAMPLE>;
+ clock-names = "ahb",
+ "mmc",
+ "output",
+ "sample";
+};
+
+&mmc1 {
+ compatible = "allwinner,sun7i-a20-mmc";
+ clocks = <&ccu CLK_BUS_MMC1>,
+ <&ccu CLK_MMC1>,
+ <&ccu CLK_MMC1_OUTPUT>,
+ <&ccu CLK_MMC1_SAMPLE>;
+ clock-names = "ahb",
+ "mmc",
+ "output",
+ "sample";
+};
+
+&mmc2 {
+ compatible = "allwinner,sun7i-a20-mmc";
+ clocks = <&ccu CLK_BUS_MMC2>,
+ <&ccu CLK_MMC2>,
+ <&ccu CLK_MMC2_OUTPUT>,
+ <&ccu CLK_MMC2_SAMPLE>;
+ clock-names = "ahb",
+ "mmc",
+ "output",
+ "sample";
+};
+
+&pio {
+ compatible = "allwinner,sun8i-h3-pinctrl";
+};
diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
similarity index 88%
copy from arch/arm/boot/dts/sun8i-h3.dtsi
copy to arch/arm/boot/dts/sunxi-h3-h5.dtsi
index 735e9cef334f..966dc4211c4d 100644
--- a/arch/arm/boot/dts/sun8i-h3.dtsi
+++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
@@ -40,52 +40,14 @@
* OTHER DEALINGS IN THE SOFTWARE.
*/
-#include "skeleton.dtsi"
-
#include <dt-bindings/clock/sunxi-h3-h5-ccu.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/pinctrl/sun4i-a10.h>
#include <dt-bindings/reset/sunxi-h3-h5-ccu.h>
/ {
- interrupt-parent = <&gic>;
-
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
-
- cpu at 0 {
- compatible = "arm,cortex-a7";
- device_type = "cpu";
- reg = <0>;
- };
-
- cpu at 1 {
- compatible = "arm,cortex-a7";
- device_type = "cpu";
- reg = <1>;
- };
-
- cpu at 2 {
- compatible = "arm,cortex-a7";
- device_type = "cpu";
- reg = <2>;
- };
-
- cpu at 3 {
- compatible = "arm,cortex-a7";
- device_type = "cpu";
- reg = <3>;
- };
- };
-
- timer {
- compatible = "arm,armv7-timer";
- interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
- };
+ #address-cells = <1>;
+ #size-cells = <1>;
clocks {
#address-cells = <1>;
@@ -150,16 +112,8 @@
};
mmc0: mmc at 01c0f000 {
- compatible = "allwinner,sun7i-a20-mmc";
+ /* compatible and clocks are in per SoC .dtsi file */
reg = <0x01c0f000 0x1000>;
- clocks = <&ccu CLK_BUS_MMC0>,
- <&ccu CLK_MMC0>,
- <&ccu CLK_MMC0_OUTPUT>,
- <&ccu CLK_MMC0_SAMPLE>;
- clock-names = "ahb",
- "mmc",
- "output",
- "sample";
resets = <&ccu RST_BUS_MMC0>;
reset-names = "ahb";
interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
@@ -169,16 +123,8 @@
};
mmc1: mmc at 01c10000 {
- compatible = "allwinner,sun7i-a20-mmc";
+ /* compatible and clocks are in per SoC .dtsi file */
reg = <0x01c10000 0x1000>;
- clocks = <&ccu CLK_BUS_MMC1>,
- <&ccu CLK_MMC1>,
- <&ccu CLK_MMC1_OUTPUT>,
- <&ccu CLK_MMC1_SAMPLE>;
- clock-names = "ahb",
- "mmc",
- "output",
- "sample";
resets = <&ccu RST_BUS_MMC1>;
reset-names = "ahb";
interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
@@ -188,16 +134,8 @@
};
mmc2: mmc at 01c11000 {
- compatible = "allwinner,sun7i-a20-mmc";
+ /* compatible and clocks are in per SoC .dtsi file */
reg = <0x01c11000 0x1000>;
- clocks = <&ccu CLK_BUS_MMC2>,
- <&ccu CLK_MMC2>,
- <&ccu CLK_MMC2_OUTPUT>,
- <&ccu CLK_MMC2_SAMPLE>;
- clock-names = "ahb",
- "mmc",
- "output",
- "sample";
resets = <&ccu RST_BUS_MMC2>;
reset-names = "ahb";
interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
@@ -308,7 +246,7 @@
};
ccu: clock at 01c20000 {
- compatible = "allwinner,sun8i-h3-ccu";
+ /* compatible is in per SoC .dtsi file */
reg = <0x01c20000 0x400>;
clocks = <&osc24M>, <&osc32k>;
clock-names = "hosc", "losc";
@@ -317,7 +255,7 @@
};
pio: pinctrl at 01c20800 {
- compatible = "allwinner,sun8i-h3-pinctrl";
+ /* compatible is in per SoC .dtsi file */
reg = <0x01c20800 0x400>;
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
@@ -588,17 +526,6 @@
#size-cells = <0>;
};
- gic: interrupt-controller at 01c81000 {
- compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
- reg = <0x01c81000 0x1000>,
- <0x01c82000 0x1000>,
- <0x01c84000 0x2000>,
- <0x01c86000 0x2000>;
- interrupt-controller;
- #interrupt-cells = <3>;
- interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
- };
-
rtc: rtc at 01f00000 {
compatible = "allwinner,sun6i-a31-rtc";
reg = <0x01f00000 0x54>;
--
2.11.0
^ permalink raw reply related [flat|nested] 13+ messages in thread* [PATCH v4 7/9] ASoC: sunxi: allow the analog codec driver to be built on ARM64
2017-02-07 18:30 [PATCH v4 0/9] Allwinner H5 and Orange Pi PC2 support Icenowy Zheng
` (5 preceding siblings ...)
2017-02-07 18:30 ` [PATCH v4 6/9] arm: dts: sun8i: split Allwinner H3 .dtsi Icenowy Zheng
@ 2017-02-07 18:30 ` Icenowy Zheng
2017-02-07 18:30 ` [PATCH v4 8/9] arm64: dts: allwinner: add Allwinner H5 .dtsi Icenowy Zheng
2017-02-07 18:30 ` [PATCH v4 9/9] arm64: dts: sunxi: add support for the Orange Pi PC 2 board Icenowy Zheng
8 siblings, 0 replies; 13+ messages in thread
From: Icenowy Zheng @ 2017-02-07 18:30 UTC (permalink / raw)
To: linux-arm-kernel
As the 64-bit Allwinner H5 SoC has the same analog codec part (also the
same digital part) as H3, enable the driver to be built on ARM64
Allwinner platform, so that it can be used on H5.
Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
---
sound/soc/sunxi/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/sound/soc/sunxi/Kconfig b/sound/soc/sunxi/Kconfig
index 6c344e16aca4..49b71719c9b9 100644
--- a/sound/soc/sunxi/Kconfig
+++ b/sound/soc/sunxi/Kconfig
@@ -11,7 +11,7 @@ config SND_SUN4I_CODEC
config SND_SUN8I_CODEC_ANALOG
tristate "Allwinner sun8i Codec Analog Controls Support"
- depends on MACH_SUN8I || COMPILE_TEST
+ depends on MACH_SUN8I || (ARM64 && ARCH_SUNXI) || COMPILE_TEST
select REGMAP
help
Say Y or M if you want to add support for the analog controls for
--
2.11.0
^ permalink raw reply related [flat|nested] 13+ messages in thread* [PATCH v4 8/9] arm64: dts: allwinner: add Allwinner H5 .dtsi
2017-02-07 18:30 [PATCH v4 0/9] Allwinner H5 and Orange Pi PC2 support Icenowy Zheng
` (6 preceding siblings ...)
2017-02-07 18:30 ` [PATCH v4 7/9] ASoC: sunxi: allow the analog codec driver to be built on ARM64 Icenowy Zheng
@ 2017-02-07 18:30 ` Icenowy Zheng
2017-02-07 18:30 ` [PATCH v4 9/9] arm64: dts: sunxi: add support for the Orange Pi PC 2 board Icenowy Zheng
8 siblings, 0 replies; 13+ messages in thread
From: Icenowy Zheng @ 2017-02-07 18:30 UTC (permalink / raw)
To: linux-arm-kernel
From: Andre Przywara <andre.przywara@arm.com>
The Allwinner H5 SoC is pin-compatible to the H3 SoC, but uses
Cortex-A53 cores instead.
Based on the now shared base .dtsi describing the common peripherals
describe the H5 specific nodes on top of that.
That symlinks in the sunxi-h3-h5.dtsi from the arch/arm tree.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
[Icenowy: add H5 pinctrl compatible, and changes for my h3-h5 dtsi
refactor, commit message change to met new arm64 naming scheme,
drop H3 pinctrl compatible because of interrupt bank change, drop
H3 ccu compatible because of clock change]
Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
---
Changes in v3:
- Dropped sun5i-a13-mmc, sun8i-h3-ccu compatibles.
- Used sun50i-{h5,a64}-emmc compatible for mmc2.
Changes in v2:
- Dropped sun8i-h3-pinctrl compatible, as the interrupt of H3 and H5 is
in fact different. arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi | 139 +++++++++++++++++++++++++
arch/arm64/boot/dts/allwinner/sunxi-h3-h5.dtsi | 1 +
2 files changed, 140 insertions(+)
create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi
create mode 120000 arch/arm64/boot/dts/allwinner/sunxi-h3-h5.dtsi
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi
new file mode 100644
index 000000000000..b651bd6986e8
--- /dev/null
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi
@@ -0,0 +1,139 @@
+/*
+ * Copyright (C) 2016 ARM Ltd.
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include "sunxi-h3-h5.dtsi"
+
+/ {
+ interrupt-parent = <&gic>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu at 0 {
+ compatible = "arm,cortex-a53", "arm,armv8";
+ device_type = "cpu";
+ reg = <0>;
+ enable-method = "psci";
+ };
+
+ cpu at 1 {
+ compatible = "arm,cortex-a53", "arm,armv8";
+ device_type = "cpu";
+ reg = <1>;
+ enable-method = "psci";
+ };
+
+ cpu at 2 {
+ compatible = "arm,cortex-a53", "arm,armv8";
+ device_type = "cpu";
+ reg = <2>;
+ enable-method = "psci";
+ };
+
+ cpu at 3 {
+ compatible = "arm,cortex-a53", "arm,armv8";
+ device_type = "cpu";
+ reg = <3>;
+ enable-method = "psci";
+ };
+ };
+
+ psci {
+ compatible = "arm,psci-0.2";
+ method = "smc";
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 13
+ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14
+ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11
+ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10
+ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+ };
+
+ soc {
+ gic: interrupt-controller at 1c81000 {
+ compatible = "arm,gic-400";
+ reg = <0x01c81000 0x1000>,
+ <0x01c82000 0x2000>,
+ <0x01c84000 0x2000>,
+ <0x01c86000 0x2000>;
+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ };
+ };
+};
+
+&ccu {
+ compatible = "allwinner,sun50i-h5-ccu";
+};
+
+&mmc0 {
+ compatible = "allwinner,sun50i-h5-mmc",
+ "allwinner,sun50i-a64-mmc";
+ clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
+ clock-names = "ahb", "mmc";
+};
+
+&mmc1 {
+ compatible = "allwinner,sun50i-h5-mmc",
+ "allwinner,sun50i-a64-mmc";
+ clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
+ clock-names = "ahb", "mmc";
+};
+
+&mmc2 {
+ compatible = "allwinner,sun50i-h5-emmc",
+ "allwinner,sun50i-a64-emmc";
+ clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
+ clock-names = "ahb", "mmc";
+};
+
+&pio {
+ compatible = "allwinner,sun50i-h5-pinctrl";
+};
diff --git a/arch/arm64/boot/dts/allwinner/sunxi-h3-h5.dtsi b/arch/arm64/boot/dts/allwinner/sunxi-h3-h5.dtsi
new file mode 120000
index 000000000000..036f01dc2b9b
--- /dev/null
+++ b/arch/arm64/boot/dts/allwinner/sunxi-h3-h5.dtsi
@@ -0,0 +1 @@
+../../../../arm/boot/dts/sunxi-h3-h5.dtsi
\ No newline at end of file
--
2.11.0
^ permalink raw reply related [flat|nested] 13+ messages in thread* [PATCH v4 9/9] arm64: dts: sunxi: add support for the Orange Pi PC 2 board
2017-02-07 18:30 [PATCH v4 0/9] Allwinner H5 and Orange Pi PC2 support Icenowy Zheng
` (7 preceding siblings ...)
2017-02-07 18:30 ` [PATCH v4 8/9] arm64: dts: allwinner: add Allwinner H5 .dtsi Icenowy Zheng
@ 2017-02-07 18:30 ` Icenowy Zheng
8 siblings, 0 replies; 13+ messages in thread
From: Icenowy Zheng @ 2017-02-07 18:30 UTC (permalink / raw)
To: linux-arm-kernel
From: Andre Przywara <andre.przywara@arm.com>
The Orange Pi PC 2 is a typical single board computer using the
Allwinner H5 SoC. Apart from the usual suspects it features three
separately driven USB ports and a Gigabit Ethernet port.
Also it has a SPI NOR flash soldered, from which the board can boot
from. This enables the SBC to behave like a "real computer" with
built-in firmware.
Add the board specific .dts file, which includes the H5 .dtsi and
enables the peripherals that we support so far.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
[Icenowy: dropped all GPIO pinctrl nodes, change red LED gpio]
Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
---
Changes in v2:
- Dropped all GPIO pinctrl nodes.
- Changed red LED gpio to the correct one.
- Added audio codec configuration copied from Orange Pi PC.
arch/arm64/boot/dts/allwinner/Makefile | 1 +
.../boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts | 164 +++++++++++++++++++++
2 files changed, 165 insertions(+)
create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts
diff --git a/arch/arm64/boot/dts/allwinner/Makefile b/arch/arm64/boot/dts/allwinner/Makefile
index bc6f342be59f..244e8b7565f9 100644
--- a/arch/arm64/boot/dts/allwinner/Makefile
+++ b/arch/arm64/boot/dts/allwinner/Makefile
@@ -1,5 +1,6 @@
dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-bananapi-m64.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-pine64-plus.dtb sun50i-a64-pine64.dtb
+dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-orangepi-pc2.dtb
always := $(dtb-y)
subdir-y := $(dts-dirs)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts
new file mode 100644
index 000000000000..79784cba806c
--- /dev/null
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts
@@ -0,0 +1,164 @@
+/*
+ * Copyright (C) 2016 ARM Ltd.
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "sun50i-h5.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/pinctrl/sun4i-a10.h>
+
+/ {
+ model = "Xunlong Orange Pi PC 2";
+ compatible = "xunlong,orangepi-pc2", "allwinner,sun50i-h5";
+
+ reg_vcc3v3: vcc3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ pwr_led {
+ label = "orangepi:green:pwr";
+ gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>;
+ default-state = "on";
+ };
+
+ status_led {
+ label = "orangepi:red:status";
+ gpios = <&pio 0 20 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ r_gpio_keys {
+ compatible = "gpio-keys";
+
+ sw4 {
+ label = "sw4";
+ linux,code = <BTN_0>;
+ gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>;
+ };
+ };
+};
+
+&codec {
+ allwinner,audio-routing =
+ "Line Out", "LINEOUT",
+ "MIC1", "Mic",
+ "Mic", "MBIAS";
+ status = "okay";
+};
+
+&ehci1 {
+ status = "okay";
+};
+
+&ehci2 {
+ status = "okay";
+};
+
+&ehci3 {
+ status = "okay";
+};
+
+&ir {
+ pinctrl-names = "default";
+ pinctrl-0 = <&ir_pins_a>;
+ status = "okay";
+};
+
+&mmc0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>;
+ vmmc-supply = <®_vcc3v3>;
+ bus-width = <4>;
+ cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */
+ cd-inverted;
+ status = "okay";
+};
+
+&ohci1 {
+ status = "okay";
+};
+
+&ohci2 {
+ status = "okay";
+};
+
+&ohci3 {
+ status = "okay";
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins_a>;
+ status = "okay";
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1_pins>;
+ status = "disabled";
+};
+
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart2_pins>;
+ status = "disabled";
+};
+
+&usbphy {
+ /* USB VBUS is always on */
+ status = "okay";
+};
--
2.11.0
^ permalink raw reply related [flat|nested] 13+ messages in thread