From: marc.zyngier@arm.com (Marc Zyngier)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v3 18/18] arm64: arch_timer: Add HISILICON_ERRATUM_161010101 ACPI matching data
Date: Tue, 4 Apr 2017 18:18:26 +0100 [thread overview]
Message-ID: <20170404171826.25030-19-marc.zyngier@arm.com> (raw)
In-Reply-To: <20170404171826.25030-1-marc.zyngier@arm.com>
In order to deal with ACPI enabled platforms suffering from the
HISILICON_ERRATUM_161010101, let's add the required OEM data that
allow the workaround to be enabled.
Tested-by: dann frazier <dann.frazier@canonical.com>
Tested-by: Hanjun Guo <hanjun.guo@linaro.org>
Reviewed-by: Hanjun Guo <hanjun.guo@linaro.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
---
drivers/clocksource/arm_arch_timer.c | 33 +++++++++++++++++++++++++++++++++
1 file changed, 33 insertions(+)
diff --git a/drivers/clocksource/arm_arch_timer.c b/drivers/clocksource/arm_arch_timer.c
index 887f6d00a71d..bf9e9d76375e 100644
--- a/drivers/clocksource/arm_arch_timer.c
+++ b/drivers/clocksource/arm_arch_timer.c
@@ -270,6 +270,29 @@ static u64 notrace hisi_161010101_read_cntvct_el0(void)
{
return __hisi_161010101_read_reg(cntvct_el0);
}
+
+static struct ate_acpi_oem_info hisi_161010101_oem_info[] = {
+ /*
+ * Note that trailing spaces are required to properly match
+ * the OEM table information.
+ */
+ {
+ .oem_id = "HISI ",
+ .oem_table_id = "HIP05 ",
+ .oem_revision = 0,
+ },
+ {
+ .oem_id = "HISI ",
+ .oem_table_id = "HIP06 ",
+ .oem_revision = 0,
+ },
+ {
+ .oem_id = "HISI ",
+ .oem_table_id = "HIP07 ",
+ .oem_revision = 0,
+ },
+ { /* Sentinel indicating the end of the OEM array */ },
+};
#endif
#ifdef CONFIG_ARM64_ERRATUM_858921
@@ -347,6 +370,16 @@ static const struct arch_timer_erratum_workaround ool_workarounds[] = {
.set_next_event_phys = erratum_set_next_event_tval_phys,
.set_next_event_virt = erratum_set_next_event_tval_virt,
},
+ {
+ .match_type = ate_match_acpi_oem_info,
+ .id = hisi_161010101_oem_info,
+ .desc = "HiSilicon erratum 161010101",
+ .read_cntp_tval_el0 = hisi_161010101_read_cntp_tval_el0,
+ .read_cntv_tval_el0 = hisi_161010101_read_cntv_tval_el0,
+ .read_cntvct_el0 = hisi_161010101_read_cntvct_el0,
+ .set_next_event_phys = erratum_set_next_event_tval_phys,
+ .set_next_event_virt = erratum_set_next_event_tval_virt,
+ },
#endif
#ifdef CONFIG_ARM64_ERRATUM_858921
{
--
2.11.0
next prev parent reply other threads:[~2017-04-04 17:18 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-04-04 17:18 [PATCH v3 00/18] clocksource/arch_timer: Errata workaround infrastructure rework Marc Zyngier
2017-04-04 17:18 ` [PATCH v3 01/18] arm64: Allow checking of a CPU-local erratum Marc Zyngier
2017-04-04 17:18 ` [PATCH v3 02/18] arm64: Add CNTVCT_EL0 trap handler Marc Zyngier
2017-04-04 17:18 ` [PATCH v3 03/18] arm64: Define Cortex-A73 MIDR Marc Zyngier
2017-04-04 17:18 ` [PATCH v3 04/18] arm64: cpu_errata: Allow an erratum to be match for all revisions of a core Marc Zyngier
2017-04-04 17:18 ` [PATCH v3 05/18] arm64: cpu_errata: Add capability to advertise Cortex-A73 erratum 858921 Marc Zyngier
2017-04-04 17:18 ` [PATCH v3 06/18] arm64: arch_timer: Add infrastructure for multiple erratum detection methods Marc Zyngier
2017-04-04 17:18 ` [PATCH v3 07/18] arm64: arch_timer: Add erratum handler for CPU-specific capability Marc Zyngier
2017-04-04 17:18 ` [PATCH v3 08/18] arm64: arch_timer: Move arch_timer_reg_read/write around Marc Zyngier
2017-04-04 17:18 ` [PATCH v3 09/18] arm64: arch_timer: Get rid of erratum_workaround_set_sne Marc Zyngier
2017-04-04 17:18 ` [PATCH v3 10/18] arm64: arch_timer: Rework the set_next_event workarounds Marc Zyngier
2017-04-04 17:18 ` [PATCH v3 11/18] arm64: arch_timer: Make workaround methods optional Marc Zyngier
2017-04-04 17:18 ` [PATCH v3 12/18] arm64: arch_timer: Allows a CPU-specific erratum to only affect a subset of CPUs Marc Zyngier
2017-04-04 17:18 ` [PATCH v3 13/18] arm64: arch_timer: Move clocksource_counter and co around Marc Zyngier
2017-04-04 17:18 ` [PATCH v3 14/18] arm64: arch_timer: Save cntkctl_el1 as a per-cpu variable Marc Zyngier
2017-04-04 17:18 ` [PATCH v3 15/18] arm64: arch_timer: Enable CNTVCT_EL0 trap if workaround is enabled Marc Zyngier
[not found] ` <58FDB05B.6020108@huawei.com>
2017-04-24 8:13 ` Marc Zyngier
2017-04-24 8:18 ` Lixiaoping (Timmy)
2017-04-24 8:25 ` Lixiaoping (Timmy)
2017-04-24 8:40 ` Marc Zyngier
2017-04-24 9:14 ` Hanjun Guo
2017-04-24 9:18 ` Daniel Lezcano
2017-04-24 9:33 ` Marc Zyngier
2017-04-24 11:26 ` Catalin Marinas
2017-04-04 17:18 ` [PATCH v3 16/18] arm64: arch_timer: Workaround for Cortex-A73 erratum 858921 Marc Zyngier
2017-04-04 17:18 ` [PATCH v3 17/18] arm64: arch_timer: Allow erratum matching with ACPI OEM information Marc Zyngier
2017-04-04 17:18 ` Marc Zyngier [this message]
2017-04-06 16:27 ` [PATCH v3 00/18] clocksource/arch_timer: Errata workaround infrastructure rework Catalin Marinas
2017-04-06 21:15 ` Daniel Lezcano
2017-04-07 8:15 ` Thomas Gleixner
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20170404171826.25030-19-marc.zyngier@arm.com \
--to=marc.zyngier@arm.com \
--cc=linux-arm-kernel@lists.infradead.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox