[PATCH v2 0/2] clk: davinci: some more fixes

[PATCH v2 0/2] clk: davinci: some more fixes

[Sekhar Nori]

Hi,

Some more fixes to make DM646x and DM365 EVMs boot after
common clock framework conversion. With this, I have tested
all DaVinci SoCs.

See individual patches for v2 changes.

Sekhar Nori (2):
  clk: davinci: pll-dm646x: keep PLL2 SYSCLK1 always enabled
  clk: davinci: psc-dm365: fix few clocks

 drivers/clk/davinci/pll-dm646x.c |  2 +-
 drivers/clk/davinci/psc-dm365.c  | 19 ++++++++++++++++---
 2 files changed, 17 insertions(+), 4 deletions(-)

-- 
2.16.2

[PATCH v2 1/2] clk: davinci: pll-dm646x: keep PLL2 SYSCLK1 always enabled

[Sekhar Nori]

PLL2 SYSCLK1 on DM646x is connected to DDR2 PHY and cannot
be disabled. Mark it so to prevent unused clock disable
infrastructure from disabling it.

Signed-off-by: Sekhar Nori <nsekhar@ti.com>
---
v2: rebased to apply to v4.17-rc1. No functional change.

 drivers/clk/davinci/pll-dm646x.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/davinci/pll-dm646x.c b/drivers/clk/davinci/pll-dm646x.c
index a61cc3256418..0ae827e3ce80 100644
--- a/drivers/clk/davinci/pll-dm646x.c
+++ b/drivers/clk/davinci/pll-dm646x.c
@@ -72,7 +72,7 @@ static const struct davinci_pll_clk_info dm646x_pll2_info = {
 	.flags = 0,
 };
 
-SYSCLK(1, pll2_sysclk1, pll2_pllen, 4, 0);
+SYSCLK(1, pll2_sysclk1, pll2_pllen, 4, SYSCLK_ALWAYS_ENABLED);
 
 int dm646x_pll2_init(struct device *dev, void __iomem *base)
 {
-- 
2.16.2

[PATCH v2 1/2] clk: davinci: pll-dm646x: keep PLL2 SYSCLK1 always enabled

[David Lechner]

On 05/15/2018 06:22 AM, Sekhar Nori wrote:
> PLL2 SYSCLK1 on DM646x is connected to DDR2 PHY and cannot
> be disabled. Mark it so to prevent unused clock disable
> infrastructure from disabling it.
> 
> Signed-off-by: Sekhar Nori <nsekhar@ti.com>
> ---
> v2: rebased to apply to v4.17-rc1. No functional change.
> 
>   drivers/clk/davinci/pll-dm646x.c | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/clk/davinci/pll-dm646x.c b/drivers/clk/davinci/pll-dm646x.c
> index a61cc3256418..0ae827e3ce80 100644
> --- a/drivers/clk/davinci/pll-dm646x.c
> +++ b/drivers/clk/davinci/pll-dm646x.c
> @@ -72,7 +72,7 @@ static const struct davinci_pll_clk_info dm646x_pll2_info = {
>   	.flags = 0,
>   };
>   
> -SYSCLK(1, pll2_sysclk1, pll2_pllen, 4, 0);
> +SYSCLK(1, pll2_sysclk1, pll2_pllen, 4, SYSCLK_ALWAYS_ENABLED);
>   
>   int dm646x_pll2_init(struct device *dev, void __iomem *base)
>   {
> 

Reviewed-by: David Lechner <david@lechnology.com>

[PATCH v2 2/2] clk: davinci: psc-dm365: fix few clocks

[Sekhar Nori]

Fix parent of EMAC and voice codec PSC clocks. Documentation is clear
on EMAC clock parent, but its not fully clear on parent of voice codec
clock. The implementation chosen is matches arch/arm/mach-davinci/dm365.c.
Add a comment explaining this for posterity.

There is only one power domain on DM365. Fix the power domain of voice
codec and vpss dac modules.

While at it, add a comment explaining how the parent of vpss dac clock was
derived. Note that this patch does not touch the parent of vpss dac clock.

Signed-off-by: Sekhar Nori <nsekhar@ti.com>
---
v2: add comments explaining parents of voice codec and vpss dac clocks

 drivers/clk/davinci/psc-dm365.c | 19 ++++++++++++++++---
 1 file changed, 16 insertions(+), 3 deletions(-)

diff --git a/drivers/clk/davinci/psc-dm365.c b/drivers/clk/davinci/psc-dm365.c
index 3ad915f37376..289af3913fb0 100644
--- a/drivers/clk/davinci/psc-dm365.c
+++ b/drivers/clk/davinci/psc-dm365.c
@@ -65,9 +65,22 @@ static const struct davinci_lpsc_clk_info dm365_psc_info[] = {
 	LPSC(31, 0, arm,         pll2_sysclk2, NULL,               LPSC_ALWAYS_ENABLED),
 	LPSC(38, 0, spi3,        pll1_sysclk4, spi3_clkdev,        0),
 	LPSC(39, 0, spi4,        pll1_auxclk,  spi4_clkdev,        0),
-	LPSC(40, 0, emac,        pll2_sysclk4, emac_clkdev,        0),
-	LPSC(44, 1, voice_codec, pll1_sysclk3, voice_codec_clkdev, 0),
-	LPSC(46, 1, vpss_dac,    pll1_sysclk3, vpss_dac_clkdev,    0),
+	LPSC(40, 0, emac,        pll1_sysclk4, emac_clkdev,        0),
+	/*
+	 * The TRM (ARM Subsystem User's Guide) shows two clocks input into
+	 * voice codec module (PLL2 SYSCLK4 with a DIV2 and PLL1 SYSCLK4). Its
+	 * not fully clear from documentation which clock should be considered
+	 * as parent for PSC. The clock chosen here is to maintain
+	 * compatibility with existing code in arch/arm/mach-davinci/dm365.c
+	 */
+	LPSC(44, 0, voice_codec, pll2_sysclk4, voice_codec_clkdev, 0),
+	/*
+	 * Its not fully clear from TRM (ARM Subsystem User's Guide) as to what
+	 * the parent of VPSS DAC LPSC should actually be. PLL1 SYSCLK3 feeds
+	 * into HDVICP and MJCP. The clock chosen here is to remain compatible
+	 * with code existing in arch/arm/mach-davinci/dm365.c
+	 */
+	LPSC(46, 0, vpss_dac,    pll1_sysclk3, vpss_dac_clkdev,    0),
 	LPSC(47, 0, vpss_master, pll1_sysclk5, vpss_master_clkdev, 0),
 	LPSC(50, 0, mjcp,        pll1_sysclk3, NULL,               0),
 	{ }
-- 
2.16.2

[PATCH v2 2/2] clk: davinci: psc-dm365: fix few clocks

[David Lechner]

On 05/15/2018 06:22 AM, Sekhar Nori wrote:
> Fix parent of EMAC and voice codec PSC clocks. Documentation is clear
> on EMAC clock parent, but its not fully clear on parent of voice codec
> clock. The implementation chosen is matches arch/arm/mach-davinci/dm365.c.
> Add a comment explaining this for posterity.
> 
> There is only one power domain on DM365. Fix the power domain of voice
> codec and vpss dac modules.
> 
> While at it, add a comment explaining how the parent of vpss dac clock was
> derived. Note that this patch does not touch the parent of vpss dac clock.
> 
> Signed-off-by: Sekhar Nori <nsekhar@ti.com>
> ---
> v2: add comments explaining parents of voice codec and vpss dac clocks
> 
>   drivers/clk/davinci/psc-dm365.c | 19 ++++++++++++++++---
>   1 file changed, 16 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/clk/davinci/psc-dm365.c b/drivers/clk/davinci/psc-dm365.c
> index 3ad915f37376..289af3913fb0 100644
> --- a/drivers/clk/davinci/psc-dm365.c
> +++ b/drivers/clk/davinci/psc-dm365.c
> @@ -65,9 +65,22 @@ static const struct davinci_lpsc_clk_info dm365_psc_info[] = {
>   	LPSC(31, 0, arm,         pll2_sysclk2, NULL,               LPSC_ALWAYS_ENABLED),
>   	LPSC(38, 0, spi3,        pll1_sysclk4, spi3_clkdev,        0),
>   	LPSC(39, 0, spi4,        pll1_auxclk,  spi4_clkdev,        0),
> -	LPSC(40, 0, emac,        pll2_sysclk4, emac_clkdev,        0),
> -	LPSC(44, 1, voice_codec, pll1_sysclk3, voice_codec_clkdev, 0),
> -	LPSC(46, 1, vpss_dac,    pll1_sysclk3, vpss_dac_clkdev,    0),
> +	LPSC(40, 0, emac,        pll1_sysclk4, emac_clkdev,        0),
> +	/*
> +	 * The TRM (ARM Subsystem User's Guide) shows two clocks input into
> +	 * voice codec module (PLL2 SYSCLK4 with a DIV2 and PLL1 SYSCLK4). Its
> +	 * not fully clear from documentation which clock should be considered
> +	 * as parent for PSC. The clock chosen here is to maintain
> +	 * compatibility with existing code in arch/arm/mach-davinci/dm365.c
> +	 */
> +	LPSC(44, 0, voice_codec, pll2_sysclk4, voice_codec_clkdev, 0),
> +	/*
> +	 * Its not fully clear from TRM (ARM Subsystem User's Guide) as to what
> +	 * the parent of VPSS DAC LPSC should actually be. PLL1 SYSCLK3 feeds
> +	 * into HDVICP and MJCP. The clock chosen here is to remain compatible
> +	 * with code existing in arch/arm/mach-davinci/dm365.c
> +	 */
> +	LPSC(46, 0, vpss_dac,    pll1_sysclk3, vpss_dac_clkdev,    0),
>   	LPSC(47, 0, vpss_master, pll1_sysclk5, vpss_master_clkdev, 0),
>   	LPSC(50, 0, mjcp,        pll1_sysclk3, NULL,               0),
>   	{ }
> 

Reviewed-by: David Lechner <david@lechnology.com>